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split out into 2 functions, longer and compact fragment
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8
9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
10 from fpbase import MultiShiftRMerge, Trigger
11 #from fpbase import FPNumShiftMultiRight
12
13 class FPState(FPBase):
14 def __init__(self, state_from):
15 self.state_from = state_from
16
17 def set_inputs(self, inputs):
18 self.inputs = inputs
19 for k,v in inputs.items():
20 setattr(self, k, v)
21
22 def set_outputs(self, outputs):
23 self.outputs = outputs
24 for k,v in outputs.items():
25 setattr(self, k, v)
26
27
28 class FPGetOpMod:
29 def __init__(self, width):
30 self.in_op = FPOp(width)
31 self.out_op = Signal(width)
32 self.out_decode = Signal(reset_less=True)
33
34 def elaborate(self, platform):
35 m = Module()
36 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
37 m.submodules.get_op_in = self.in_op
38 #m.submodules.get_op_out = self.out_op
39 with m.If(self.out_decode):
40 m.d.comb += [
41 self.out_op.eq(self.in_op.v),
42 ]
43 return m
44
45
46 class FPGetOp(FPState):
47 """ gets operand
48 """
49
50 def __init__(self, in_state, out_state, in_op, width):
51 FPState.__init__(self, in_state)
52 self.out_state = out_state
53 self.mod = FPGetOpMod(width)
54 self.in_op = in_op
55 self.out_op = Signal(width)
56 self.out_decode = Signal(reset_less=True)
57
58 def setup(self, m, in_op):
59 """ links module to inputs and outputs
60 """
61 setattr(m.submodules, self.state_from, self.mod)
62 m.d.comb += self.mod.in_op.copy(in_op)
63 #m.d.comb += self.out_op.eq(self.mod.out_op)
64 m.d.comb += self.out_decode.eq(self.mod.out_decode)
65
66 def action(self, m):
67 with m.If(self.out_decode):
68 m.next = self.out_state
69 m.d.sync += [
70 self.in_op.ack.eq(0),
71 self.out_op.eq(self.mod.out_op)
72 ]
73 with m.Else():
74 m.d.sync += self.in_op.ack.eq(1)
75
76
77 class FPGet2OpMod(Trigger):
78 def __init__(self, width):
79 Trigger.__init__(self)
80 self.in_op1 = Signal(width, reset_less=True)
81 self.in_op2 = Signal(width, reset_less=True)
82 self.out_op1 = FPNumIn(None, width)
83 self.out_op2 = FPNumIn(None, width)
84
85 def elaborate(self, platform):
86 m = Trigger.elaborate(self, platform)
87 #m.submodules.get_op_in = self.in_op
88 m.submodules.get_op1_out = self.out_op1
89 m.submodules.get_op2_out = self.out_op2
90 with m.If(self.trigger):
91 m.d.comb += [
92 self.out_op1.decode(self.in_op1),
93 self.out_op2.decode(self.in_op2),
94 ]
95 return m
96
97
98 class FPGet2Op(FPState):
99 """ gets operands
100 """
101
102 def __init__(self, in_state, out_state, in_op1, in_op2, width):
103 FPState.__init__(self, in_state)
104 self.out_state = out_state
105 self.mod = FPGet2OpMod(width)
106 self.in_op1 = in_op1
107 self.in_op2 = in_op2
108 self.out_op1 = FPNumIn(None, width)
109 self.out_op2 = FPNumIn(None, width)
110 self.in_stb = Signal(reset_less=True)
111 self.out_ack = Signal(reset_less=True)
112 self.out_decode = Signal(reset_less=True)
113
114 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
115 """ links module to inputs and outputs
116 """
117 m.submodules.get_ops = self.mod
118 m.d.comb += self.mod.in_op1.eq(in_op1)
119 m.d.comb += self.mod.in_op2.eq(in_op2)
120 m.d.comb += self.mod.stb.eq(in_stb)
121 m.d.comb += self.out_ack.eq(self.mod.ack)
122 m.d.comb += self.out_decode.eq(self.mod.trigger)
123 m.d.comb += in_ack.eq(self.mod.ack)
124
125 def action(self, m):
126 with m.If(self.out_decode):
127 m.next = self.out_state
128 m.d.sync += [
129 self.mod.ack.eq(0),
130 #self.out_op1.v.eq(self.mod.out_op1.v),
131 #self.out_op2.v.eq(self.mod.out_op2.v),
132 self.out_op1.copy(self.mod.out_op1),
133 self.out_op2.copy(self.mod.out_op2)
134 ]
135 with m.Else():
136 m.d.sync += self.mod.ack.eq(1)
137
138
139 class FPAddSpecialCasesMod:
140 """ special cases: NaNs, infs, zeros, denormalised
141 NOTE: some of these are unique to add. see "Special Operations"
142 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
143 """
144
145 def __init__(self, width):
146 self.in_a = FPNumBase(width)
147 self.in_b = FPNumBase(width)
148 self.out_z = FPNumOut(width, False)
149 self.out_do_z = Signal(reset_less=True)
150
151 def elaborate(self, platform):
152 m = Module()
153
154 m.submodules.sc_in_a = self.in_a
155 m.submodules.sc_in_b = self.in_b
156 m.submodules.sc_out_z = self.out_z
157
158 s_nomatch = Signal()
159 m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
160
161 m_match = Signal()
162 m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
163
164 # if a is NaN or b is NaN return NaN
165 with m.If(self.in_a.is_nan | self.in_b.is_nan):
166 m.d.comb += self.out_do_z.eq(1)
167 m.d.comb += self.out_z.nan(0)
168
169 # XXX WEIRDNESS for FP16 non-canonical NaN handling
170 # under review
171
172 ## if a is zero and b is NaN return -b
173 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
174 # m.d.comb += self.out_do_z.eq(1)
175 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
176
177 ## if b is zero and a is NaN return -a
178 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
179 # m.d.comb += self.out_do_z.eq(1)
180 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
181
182 ## if a is -zero and b is NaN return -b
183 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
184 # m.d.comb += self.out_do_z.eq(1)
185 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
186
187 ## if b is -zero and a is NaN return -a
188 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
189 # m.d.comb += self.out_do_z.eq(1)
190 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
191
192 # if a is inf return inf (or NaN)
193 with m.Elif(self.in_a.is_inf):
194 m.d.comb += self.out_do_z.eq(1)
195 m.d.comb += self.out_z.inf(self.in_a.s)
196 # if a is inf and signs don't match return NaN
197 with m.If(self.in_b.exp_128 & s_nomatch):
198 m.d.comb += self.out_z.nan(0)
199
200 # if b is inf return inf
201 with m.Elif(self.in_b.is_inf):
202 m.d.comb += self.out_do_z.eq(1)
203 m.d.comb += self.out_z.inf(self.in_b.s)
204
205 # if a is zero and b zero return signed-a/b
206 with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
207 m.d.comb += self.out_do_z.eq(1)
208 m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
209 self.in_b.e,
210 self.in_b.m[3:-1])
211
212 # if a is zero return b
213 with m.Elif(self.in_a.is_zero):
214 m.d.comb += self.out_do_z.eq(1)
215 m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
216 self.in_b.m[3:-1])
217
218 # if b is zero return a
219 with m.Elif(self.in_b.is_zero):
220 m.d.comb += self.out_do_z.eq(1)
221 m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
222 self.in_a.m[3:-1])
223
224 # if a equal to -b return zero (+ve zero)
225 with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
226 m.d.comb += self.out_do_z.eq(1)
227 m.d.comb += self.out_z.zero(0)
228
229 # Denormalised Number checks
230 with m.Else():
231 m.d.comb += self.out_do_z.eq(0)
232
233 return m
234
235
236 class FPID:
237 def __init__(self, id_wid):
238 self.id_wid = id_wid
239 if self.id_wid:
240 self.in_mid = Signal(id_wid, reset_less=True)
241 self.out_mid = Signal(id_wid, reset_less=True)
242 else:
243 self.in_mid = None
244 self.out_mid = None
245
246 def idsync(self, m):
247 if self.id_wid is not None:
248 m.d.sync += self.out_mid.eq(self.in_mid)
249
250
251 class FPAddSpecialCases(FPState, FPID):
252 """ special cases: NaNs, infs, zeros, denormalised
253 NOTE: some of these are unique to add. see "Special Operations"
254 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
255 """
256
257 def __init__(self, width, id_wid):
258 FPState.__init__(self, "special_cases")
259 FPID.__init__(self, id_wid)
260 self.mod = FPAddSpecialCasesMod(width)
261 self.out_z = FPNumOut(width, False)
262 self.out_do_z = Signal(reset_less=True)
263
264 def setup(self, m, in_a, in_b, in_mid):
265 """ links module to inputs and outputs
266 """
267 m.submodules.specialcases = self.mod
268 m.d.comb += self.mod.in_a.copy(in_a)
269 m.d.comb += self.mod.in_b.copy(in_b)
270 #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
271 m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
272 if self.in_mid is not None:
273 m.d.comb += self.in_mid.eq(in_mid)
274
275 def action(self, m):
276 self.idsync(m)
277 with m.If(self.out_do_z):
278 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
279 m.next = "put_z"
280 with m.Else():
281 m.next = "denormalise"
282
283
284 class FPAddDeNormMod(FPState):
285
286 def __init__(self, width):
287 self.in_a = FPNumBase(width)
288 self.in_b = FPNumBase(width)
289 self.out_a = FPNumBase(width)
290 self.out_b = FPNumBase(width)
291
292 def elaborate(self, platform):
293 m = Module()
294 m.submodules.denorm_in_a = self.in_a
295 m.submodules.denorm_in_b = self.in_b
296 m.submodules.denorm_out_a = self.out_a
297 m.submodules.denorm_out_b = self.out_b
298 # hmmm, don't like repeating identical code
299 m.d.comb += self.out_a.copy(self.in_a)
300 with m.If(self.in_a.exp_n127):
301 m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
302 with m.Else():
303 m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
304
305 m.d.comb += self.out_b.copy(self.in_b)
306 with m.If(self.in_b.exp_n127):
307 m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
308 with m.Else():
309 m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
310
311 return m
312
313
314 class FPAddDeNorm(FPState, FPID):
315
316 def __init__(self, width, id_wid):
317 FPState.__init__(self, "denormalise")
318 FPID.__init__(self, id_wid)
319 self.mod = FPAddDeNormMod(width)
320 self.out_a = FPNumBase(width)
321 self.out_b = FPNumBase(width)
322
323 def setup(self, m, in_a, in_b, in_mid):
324 """ links module to inputs and outputs
325 """
326 m.submodules.denormalise = self.mod
327 m.d.comb += self.mod.in_a.copy(in_a)
328 m.d.comb += self.mod.in_b.copy(in_b)
329 if self.in_mid is not None:
330 m.d.comb += self.in_mid.eq(in_mid)
331
332 def action(self, m):
333 self.idsync(m)
334 # Denormalised Number checks
335 m.next = "align"
336 m.d.sync += self.out_a.copy(self.mod.out_a)
337 m.d.sync += self.out_b.copy(self.mod.out_b)
338
339
340 class FPAddAlignMultiMod(FPState):
341
342 def __init__(self, width):
343 self.in_a = FPNumBase(width)
344 self.in_b = FPNumBase(width)
345 self.out_a = FPNumIn(None, width)
346 self.out_b = FPNumIn(None, width)
347 self.exp_eq = Signal(reset_less=True)
348
349 def elaborate(self, platform):
350 # This one however (single-cycle) will do the shift
351 # in one go.
352
353 m = Module()
354
355 m.submodules.align_in_a = self.in_a
356 m.submodules.align_in_b = self.in_b
357 m.submodules.align_out_a = self.out_a
358 m.submodules.align_out_b = self.out_b
359
360 # NOTE: this does *not* do single-cycle multi-shifting,
361 # it *STAYS* in the align state until exponents match
362
363 # exponent of a greater than b: shift b down
364 m.d.comb += self.exp_eq.eq(0)
365 m.d.comb += self.out_a.copy(self.in_a)
366 m.d.comb += self.out_b.copy(self.in_b)
367 agtb = Signal(reset_less=True)
368 altb = Signal(reset_less=True)
369 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
370 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
371 with m.If(agtb):
372 m.d.comb += self.out_b.shift_down(self.in_b)
373 # exponent of b greater than a: shift a down
374 with m.Elif(altb):
375 m.d.comb += self.out_a.shift_down(self.in_a)
376 # exponents equal: move to next stage.
377 with m.Else():
378 m.d.comb += self.exp_eq.eq(1)
379 return m
380
381
382 class FPAddAlignMulti(FPState, FPID):
383
384 def __init__(self, width, id_wid):
385 FPID.__init__(self, id_wid)
386 FPState.__init__(self, "align")
387 self.mod = FPAddAlignMultiMod(width)
388 self.out_a = FPNumIn(None, width)
389 self.out_b = FPNumIn(None, width)
390 self.exp_eq = Signal(reset_less=True)
391
392 def setup(self, m, in_a, in_b, in_mid):
393 """ links module to inputs and outputs
394 """
395 m.submodules.align = self.mod
396 m.d.comb += self.mod.in_a.copy(in_a)
397 m.d.comb += self.mod.in_b.copy(in_b)
398 #m.d.comb += self.out_a.copy(self.mod.out_a)
399 #m.d.comb += self.out_b.copy(self.mod.out_b)
400 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 m.d.sync += self.out_a.copy(self.mod.out_a)
407 m.d.sync += self.out_b.copy(self.mod.out_b)
408 with m.If(self.exp_eq):
409 m.next = "add_0"
410
411
412 class FPAddAlignSingleMod:
413
414 def __init__(self, width):
415 self.width = width
416 self.in_a = FPNumBase(width)
417 self.in_b = FPNumBase(width)
418 self.out_a = FPNumIn(None, width)
419 self.out_b = FPNumIn(None, width)
420
421 def elaborate(self, platform):
422 """ Aligns A against B or B against A, depending on which has the
423 greater exponent. This is done in a *single* cycle using
424 variable-width bit-shift
425
426 the shifter used here is quite expensive in terms of gates.
427 Mux A or B in (and out) into temporaries, as only one of them
428 needs to be aligned against the other
429 """
430 m = Module()
431
432 m.submodules.align_in_a = self.in_a
433 m.submodules.align_in_b = self.in_b
434 m.submodules.align_out_a = self.out_a
435 m.submodules.align_out_b = self.out_b
436
437 # temporary (muxed) input and output to be shifted
438 t_inp = FPNumBase(self.width)
439 t_out = FPNumIn(None, self.width)
440 espec = (len(self.in_a.e), True)
441 msr = MultiShiftRMerge(self.in_a.m_width, espec)
442 m.submodules.align_t_in = t_inp
443 m.submodules.align_t_out = t_out
444 m.submodules.multishift_r = msr
445
446 ediff = Signal(espec, reset_less=True)
447 ediffr = Signal(espec, reset_less=True)
448 tdiff = Signal(espec, reset_less=True)
449 elz = Signal(reset_less=True)
450 egz = Signal(reset_less=True)
451
452 # connect multi-shifter to t_inp/out mantissa (and tdiff)
453 m.d.comb += msr.inp.eq(t_inp.m)
454 m.d.comb += msr.diff.eq(tdiff)
455 m.d.comb += t_out.m.eq(msr.m)
456 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
457 m.d.comb += t_out.s.eq(t_inp.s)
458
459 m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
460 m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
461 m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
462 m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
463
464 # default: A-exp == B-exp, A and B untouched (fall through)
465 m.d.comb += self.out_a.copy(self.in_a)
466 m.d.comb += self.out_b.copy(self.in_b)
467 # only one shifter (muxed)
468 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
469 # exponent of a greater than b: shift b down
470 with m.If(egz):
471 m.d.comb += [t_inp.copy(self.in_b),
472 tdiff.eq(ediff),
473 self.out_b.copy(t_out),
474 self.out_b.s.eq(self.in_b.s), # whoops forgot sign
475 ]
476 # exponent of b greater than a: shift a down
477 with m.Elif(elz):
478 m.d.comb += [t_inp.copy(self.in_a),
479 tdiff.eq(ediffr),
480 self.out_a.copy(t_out),
481 self.out_a.s.eq(self.in_a.s), # whoops forgot sign
482 ]
483 return m
484
485
486 class FPAddAlignSingle(FPState, FPID):
487
488 def __init__(self, width, id_wid):
489 FPState.__init__(self, "align")
490 FPID.__init__(self, id_wid)
491 self.mod = FPAddAlignSingleMod(width)
492 self.out_a = FPNumIn(None, width)
493 self.out_b = FPNumIn(None, width)
494
495 def setup(self, m, in_a, in_b, in_mid):
496 """ links module to inputs and outputs
497 """
498 m.submodules.align = self.mod
499 m.d.comb += self.mod.in_a.copy(in_a)
500 m.d.comb += self.mod.in_b.copy(in_b)
501 if self.in_mid is not None:
502 m.d.comb += self.in_mid.eq(in_mid)
503
504 def action(self, m):
505 self.idsync(m)
506 # NOTE: could be done as comb
507 m.d.sync += self.out_a.copy(self.mod.out_a)
508 m.d.sync += self.out_b.copy(self.mod.out_b)
509 m.next = "add_0"
510
511
512 class FPAddStage0Mod:
513
514 def __init__(self, width):
515 self.in_a = FPNumBase(width)
516 self.in_b = FPNumBase(width)
517 self.in_z = FPNumBase(width, False)
518 self.out_z = FPNumBase(width, False)
519 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
520
521 def elaborate(self, platform):
522 m = Module()
523 m.submodules.add0_in_a = self.in_a
524 m.submodules.add0_in_b = self.in_b
525 m.submodules.add0_out_z = self.out_z
526
527 m.d.comb += self.out_z.e.eq(self.in_a.e)
528
529 # store intermediate tests (and zero-extended mantissas)
530 seq = Signal(reset_less=True)
531 mge = Signal(reset_less=True)
532 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
533 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
534 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
535 mge.eq(self.in_a.m >= self.in_b.m),
536 am0.eq(Cat(self.in_a.m, 0)),
537 bm0.eq(Cat(self.in_b.m, 0))
538 ]
539 # same-sign (both negative or both positive) add mantissas
540 with m.If(seq):
541 m.d.comb += [
542 self.out_tot.eq(am0 + bm0),
543 self.out_z.s.eq(self.in_a.s)
544 ]
545 # a mantissa greater than b, use a
546 with m.Elif(mge):
547 m.d.comb += [
548 self.out_tot.eq(am0 - bm0),
549 self.out_z.s.eq(self.in_a.s)
550 ]
551 # b mantissa greater than a, use b
552 with m.Else():
553 m.d.comb += [
554 self.out_tot.eq(bm0 - am0),
555 self.out_z.s.eq(self.in_b.s)
556 ]
557 return m
558
559
560 class FPAddStage0(FPState, FPID):
561 """ First stage of add. covers same-sign (add) and subtract
562 special-casing when mantissas are greater or equal, to
563 give greatest accuracy.
564 """
565
566 def __init__(self, width, id_wid):
567 FPState.__init__(self, "add_0")
568 FPID.__init__(self, id_wid)
569 self.mod = FPAddStage0Mod(width)
570 self.out_z = FPNumBase(width, False)
571 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
572
573 def setup(self, m, in_a, in_b, in_mid):
574 """ links module to inputs and outputs
575 """
576 m.submodules.add0 = self.mod
577 m.d.comb += self.mod.in_a.copy(in_a)
578 m.d.comb += self.mod.in_b.copy(in_b)
579 if self.in_mid is not None:
580 m.d.comb += self.in_mid.eq(in_mid)
581
582 def action(self, m):
583 self.idsync(m)
584 # NOTE: these could be done as combinatorial (merge add0+add1)
585 m.d.sync += self.out_z.copy(self.mod.out_z)
586 m.d.sync += self.out_tot.eq(self.mod.out_tot)
587 m.next = "add_1"
588
589
590 class FPAddStage1Mod(FPState):
591 """ Second stage of add: preparation for normalisation.
592 detects when tot sum is too big (tot[27] is kinda a carry bit)
593 """
594
595 def __init__(self, width):
596 self.out_norm = Signal(reset_less=True)
597 self.in_z = FPNumBase(width, False)
598 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
599 self.out_z = FPNumBase(width, False)
600 self.out_of = Overflow()
601
602 def elaborate(self, platform):
603 m = Module()
604 #m.submodules.norm1_in_overflow = self.in_of
605 #m.submodules.norm1_out_overflow = self.out_of
606 #m.submodules.norm1_in_z = self.in_z
607 #m.submodules.norm1_out_z = self.out_z
608 m.d.comb += self.out_z.copy(self.in_z)
609 # tot[27] gets set when the sum overflows. shift result down
610 with m.If(self.in_tot[-1]):
611 m.d.comb += [
612 self.out_z.m.eq(self.in_tot[4:]),
613 self.out_of.m0.eq(self.in_tot[4]),
614 self.out_of.guard.eq(self.in_tot[3]),
615 self.out_of.round_bit.eq(self.in_tot[2]),
616 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
617 self.out_z.e.eq(self.in_z.e + 1)
618 ]
619 # tot[27] zero case
620 with m.Else():
621 m.d.comb += [
622 self.out_z.m.eq(self.in_tot[3:]),
623 self.out_of.m0.eq(self.in_tot[3]),
624 self.out_of.guard.eq(self.in_tot[2]),
625 self.out_of.round_bit.eq(self.in_tot[1]),
626 self.out_of.sticky.eq(self.in_tot[0])
627 ]
628 return m
629
630
631 class FPAddStage1(FPState, FPID):
632
633 def __init__(self, width, id_wid):
634 FPState.__init__(self, "add_1")
635 FPID.__init__(self, id_wid)
636 self.mod = FPAddStage1Mod(width)
637 self.out_z = FPNumBase(width, False)
638 self.out_of = Overflow()
639 self.norm_stb = Signal()
640
641 def setup(self, m, in_tot, in_z, in_mid):
642 """ links module to inputs and outputs
643 """
644 m.submodules.add1 = self.mod
645 m.submodules.add1_out_overflow = self.out_of
646
647 m.d.comb += self.mod.in_z.copy(in_z)
648 m.d.comb += self.mod.in_tot.eq(in_tot)
649
650 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
651
652 if self.in_mid is not None:
653 m.d.comb += self.in_mid.eq(in_mid)
654
655 def action(self, m):
656 self.idsync(m)
657 m.d.sync += self.out_of.copy(self.mod.out_of)
658 m.d.sync += self.out_z.copy(self.mod.out_z)
659 m.d.sync += self.norm_stb.eq(1)
660 m.next = "normalise_1"
661
662
663 class FPNorm1ModSingle:
664
665 def __init__(self, width):
666 self.width = width
667 self.in_select = Signal(reset_less=True)
668 self.out_norm = Signal(reset_less=True)
669 self.in_z = FPNumBase(width, False)
670 self.in_of = Overflow()
671 self.temp_z = FPNumBase(width, False)
672 self.temp_of = Overflow()
673 self.out_z = FPNumBase(width, False)
674 self.out_of = Overflow()
675
676 def elaborate(self, platform):
677 m = Module()
678
679 mwid = self.out_z.m_width+2
680 pe = PriorityEncoder(mwid)
681 m.submodules.norm_pe = pe
682
683 m.submodules.norm1_out_z = self.out_z
684 m.submodules.norm1_out_overflow = self.out_of
685 m.submodules.norm1_temp_z = self.temp_z
686 m.submodules.norm1_temp_of = self.temp_of
687 m.submodules.norm1_in_z = self.in_z
688 m.submodules.norm1_in_overflow = self.in_of
689
690 in_z = FPNumBase(self.width, False)
691 in_of = Overflow()
692 m.submodules.norm1_insel_z = in_z
693 m.submodules.norm1_insel_overflow = in_of
694
695 espec = (len(in_z.e), True)
696 ediff_n126 = Signal(espec, reset_less=True)
697 msr = MultiShiftRMerge(mwid, espec)
698 m.submodules.multishift_r = msr
699
700 # select which of temp or in z/of to use
701 with m.If(self.in_select):
702 m.d.comb += in_z.copy(self.in_z)
703 m.d.comb += in_of.copy(self.in_of)
704 with m.Else():
705 m.d.comb += in_z.copy(self.temp_z)
706 m.d.comb += in_of.copy(self.temp_of)
707 # initialise out from in (overridden below)
708 m.d.comb += self.out_z.copy(in_z)
709 m.d.comb += self.out_of.copy(in_of)
710 # normalisation increase/decrease conditions
711 decrease = Signal(reset_less=True)
712 increase = Signal(reset_less=True)
713 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
714 m.d.comb += increase.eq(in_z.exp_lt_n126)
715 m.d.comb += self.out_norm.eq(0) # loop-end condition
716 # decrease exponent
717 with m.If(decrease):
718 # *sigh* not entirely obvious: count leading zeros (clz)
719 # with a PriorityEncoder: to find from the MSB
720 # we reverse the order of the bits.
721 temp_m = Signal(mwid, reset_less=True)
722 temp_s = Signal(mwid+1, reset_less=True)
723 clz = Signal((len(in_z.e), True), reset_less=True)
724 # make sure that the amount to decrease by does NOT
725 # go below the minimum non-INF/NaN exponent
726 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
727 in_z.exp_sub_n126)
728 m.d.comb += [
729 # cat round and guard bits back into the mantissa
730 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
731 pe.i.eq(temp_m[::-1]), # inverted
732 clz.eq(limclz), # count zeros from MSB down
733 temp_s.eq(temp_m << clz), # shift mantissa UP
734 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
735 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
736 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
737 # overflow in bits 0..1: got shifted too (leave sticky)
738 self.out_of.guard.eq(temp_s[1]), # guard
739 self.out_of.round_bit.eq(temp_s[0]), # round
740 ]
741 # increase exponent
742 with m.Elif(increase):
743 temp_m = Signal(mwid+1, reset_less=True)
744 m.d.comb += [
745 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
746 in_z.m)),
747 ediff_n126.eq(in_z.N126 - in_z.e),
748 # connect multi-shifter to inp/out mantissa (and ediff)
749 msr.inp.eq(temp_m),
750 msr.diff.eq(ediff_n126),
751 self.out_z.m.eq(msr.m[3:]),
752 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
753 # overflow in bits 0..1: got shifted too (leave sticky)
754 self.out_of.guard.eq(temp_s[2]), # guard
755 self.out_of.round_bit.eq(temp_s[1]), # round
756 self.out_of.sticky.eq(temp_s[0]), # sticky
757 self.out_z.e.eq(in_z.e + ediff_n126),
758 ]
759
760 return m
761
762
763 class FPNorm1ModMulti:
764
765 def __init__(self, width, single_cycle=True):
766 self.width = width
767 self.in_select = Signal(reset_less=True)
768 self.out_norm = Signal(reset_less=True)
769 self.in_z = FPNumBase(width, False)
770 self.in_of = Overflow()
771 self.temp_z = FPNumBase(width, False)
772 self.temp_of = Overflow()
773 self.out_z = FPNumBase(width, False)
774 self.out_of = Overflow()
775
776 def elaborate(self, platform):
777 m = Module()
778
779 m.submodules.norm1_out_z = self.out_z
780 m.submodules.norm1_out_overflow = self.out_of
781 m.submodules.norm1_temp_z = self.temp_z
782 m.submodules.norm1_temp_of = self.temp_of
783 m.submodules.norm1_in_z = self.in_z
784 m.submodules.norm1_in_overflow = self.in_of
785
786 in_z = FPNumBase(self.width, False)
787 in_of = Overflow()
788 m.submodules.norm1_insel_z = in_z
789 m.submodules.norm1_insel_overflow = in_of
790
791 # select which of temp or in z/of to use
792 with m.If(self.in_select):
793 m.d.comb += in_z.copy(self.in_z)
794 m.d.comb += in_of.copy(self.in_of)
795 with m.Else():
796 m.d.comb += in_z.copy(self.temp_z)
797 m.d.comb += in_of.copy(self.temp_of)
798 # initialise out from in (overridden below)
799 m.d.comb += self.out_z.copy(in_z)
800 m.d.comb += self.out_of.copy(in_of)
801 # normalisation increase/decrease conditions
802 decrease = Signal(reset_less=True)
803 increase = Signal(reset_less=True)
804 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
805 m.d.comb += increase.eq(in_z.exp_lt_n126)
806 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
807 # decrease exponent
808 with m.If(decrease):
809 m.d.comb += [
810 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
811 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
812 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
813 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
814 self.out_of.round_bit.eq(0), # reset round bit
815 self.out_of.m0.eq(in_of.guard),
816 ]
817 # increase exponent
818 with m.Elif(increase):
819 m.d.comb += [
820 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
821 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
822 self.out_of.guard.eq(in_z.m[0]),
823 self.out_of.m0.eq(in_z.m[1]),
824 self.out_of.round_bit.eq(in_of.guard),
825 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
826 ]
827
828 return m
829
830
831 class FPNorm1(FPState, FPID):
832
833 def __init__(self, width, id_wid, single_cycle=True):
834 FPID.__init__(self, id_wid)
835 FPState.__init__(self, "normalise_1")
836 if single_cycle:
837 self.mod = FPNorm1ModSingle(width)
838 else:
839 self.mod = FPNorm1ModMulti(width)
840 self.stb = Signal(reset_less=True)
841 self.ack = Signal(reset=0, reset_less=True)
842 self.out_norm = Signal(reset_less=True)
843 self.in_accept = Signal(reset_less=True)
844 self.temp_z = FPNumBase(width)
845 self.temp_of = Overflow()
846 self.out_z = FPNumBase(width)
847 self.out_roundz = Signal(reset_less=True)
848
849 def setup(self, m, in_z, in_of, norm_stb, in_mid):
850 """ links module to inputs and outputs
851 """
852 m.submodules.normalise_1 = self.mod
853
854 m.d.comb += self.mod.in_z.copy(in_z)
855 m.d.comb += self.mod.in_of.copy(in_of)
856
857 m.d.comb += self.mod.in_select.eq(self.in_accept)
858 m.d.comb += self.mod.temp_z.copy(self.temp_z)
859 m.d.comb += self.mod.temp_of.copy(self.temp_of)
860
861 m.d.comb += self.out_z.copy(self.mod.out_z)
862 m.d.comb += self.out_norm.eq(self.mod.out_norm)
863
864 m.d.comb += self.stb.eq(norm_stb)
865 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
866
867 if self.in_mid is not None:
868 m.d.comb += self.in_mid.eq(in_mid)
869
870 def action(self, m):
871 self.idsync(m)
872 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
873 m.d.sync += self.temp_of.copy(self.mod.out_of)
874 m.d.sync += self.temp_z.copy(self.out_z)
875 with m.If(self.out_norm):
876 with m.If(self.in_accept):
877 m.d.sync += [
878 self.ack.eq(1),
879 ]
880 with m.Else():
881 m.d.sync += self.ack.eq(0)
882 with m.Else():
883 # normalisation not required (or done).
884 m.next = "round"
885 m.d.sync += self.ack.eq(1)
886 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
887
888
889 class FPRoundMod:
890
891 def __init__(self, width):
892 self.in_roundz = Signal(reset_less=True)
893 self.in_z = FPNumBase(width, False)
894 self.out_z = FPNumBase(width, False)
895
896 def elaborate(self, platform):
897 m = Module()
898 m.d.comb += self.out_z.copy(self.in_z)
899 with m.If(self.in_roundz):
900 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
901 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
902 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
903 return m
904
905
906 class FPRound(FPState, FPID):
907
908 def __init__(self, width, id_wid):
909 FPState.__init__(self, "round")
910 FPID.__init__(self, id_wid)
911 self.mod = FPRoundMod(width)
912 self.out_z = FPNumBase(width)
913
914 def setup(self, m, in_z, roundz, in_mid):
915 """ links module to inputs and outputs
916 """
917 m.submodules.roundz = self.mod
918
919 m.d.comb += self.mod.in_z.copy(in_z)
920 m.d.comb += self.mod.in_roundz.eq(roundz)
921 if self.in_mid is not None:
922 m.d.comb += self.in_mid.eq(in_mid)
923
924 def action(self, m):
925 self.idsync(m)
926 m.d.sync += self.out_z.copy(self.mod.out_z)
927 m.next = "corrections"
928
929
930 class FPCorrectionsMod:
931
932 def __init__(self, width):
933 self.in_z = FPNumOut(width, False)
934 self.out_z = FPNumOut(width, False)
935
936 def elaborate(self, platform):
937 m = Module()
938 m.submodules.corr_in_z = self.in_z
939 m.submodules.corr_out_z = self.out_z
940 m.d.comb += self.out_z.copy(self.in_z)
941 with m.If(self.in_z.is_denormalised):
942 m.d.comb += self.out_z.e.eq(self.in_z.N127)
943 return m
944
945
946 class FPCorrections(FPState, FPID):
947
948 def __init__(self, width, id_wid):
949 FPState.__init__(self, "corrections")
950 FPID.__init__(self, id_wid)
951 self.mod = FPCorrectionsMod(width)
952 self.out_z = FPNumBase(width)
953
954 def setup(self, m, in_z, in_mid):
955 """ links module to inputs and outputs
956 """
957 m.submodules.corrections = self.mod
958 m.d.comb += self.mod.in_z.copy(in_z)
959 if self.in_mid is not None:
960 m.d.comb += self.in_mid.eq(in_mid)
961
962 def action(self, m):
963 self.idsync(m)
964 m.d.sync += self.out_z.copy(self.mod.out_z)
965 m.next = "pack"
966
967
968 class FPPackMod:
969
970 def __init__(self, width):
971 self.in_z = FPNumOut(width, False)
972 self.out_z = FPNumOut(width, False)
973
974 def elaborate(self, platform):
975 m = Module()
976 m.submodules.pack_in_z = self.in_z
977 with m.If(self.in_z.is_overflowed):
978 m.d.comb += self.out_z.inf(self.in_z.s)
979 with m.Else():
980 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
981 return m
982
983
984 class FPPack(FPState, FPID):
985
986 def __init__(self, width, id_wid):
987 FPState.__init__(self, "pack")
988 FPID.__init__(self, id_wid)
989 self.mod = FPPackMod(width)
990 self.out_z = FPNumOut(width, False)
991
992 def setup(self, m, in_z, in_mid):
993 """ links module to inputs and outputs
994 """
995 m.submodules.pack = self.mod
996 m.d.comb += self.mod.in_z.copy(in_z)
997 if self.in_mid is not None:
998 m.d.comb += self.in_mid.eq(in_mid)
999
1000 def action(self, m):
1001 self.idsync(m)
1002 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1003 m.next = "pack_put_z"
1004
1005
1006 class FPPutZ(FPState):
1007
1008 def __init__(self, state, in_z, out_z, in_mid, out_mid):
1009 FPState.__init__(self, state)
1010 self.in_z = in_z
1011 self.out_z = out_z
1012 self.in_mid = in_mid
1013 self.out_mid = out_mid
1014
1015 def action(self, m):
1016 if self.in_mid is not None:
1017 m.d.sync += self.out_mid.eq(self.in_mid)
1018 m.d.sync += [
1019 self.out_z.v.eq(self.in_z.v)
1020 ]
1021 with m.If(self.out_z.stb & self.out_z.ack):
1022 m.d.sync += self.out_z.stb.eq(0)
1023 m.next = "get_ops"
1024 with m.Else():
1025 m.d.sync += self.out_z.stb.eq(1)
1026
1027
1028 class FPADDBaseMod(FPID):
1029
1030 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1031 """ IEEE754 FP Add
1032
1033 * width: bit-width of IEEE754. supported: 16, 32, 64
1034 * id_wid: an identifier that is sync-connected to the input
1035 * single_cycle: True indicates each stage to complete in 1 clock
1036 * compact: True indicates a reduced number of stages
1037 """
1038 FPID.__init__(self, id_wid)
1039 self.width = width
1040 self.single_cycle = single_cycle
1041 self.compact = compact
1042
1043 self.in_t = Trigger()
1044 self.in_a = Signal(width)
1045 self.in_b = Signal(width)
1046 self.out_z = FPOp(width)
1047
1048 self.states = []
1049
1050 def add_state(self, state):
1051 self.states.append(state)
1052 return state
1053
1054 def get_fragment(self, platform=None):
1055 """ creates the HDL code-fragment for FPAdd
1056 """
1057 m = Module()
1058 m.submodules.out_z = self.out_z
1059 m.submodules.in_t = self.in_t
1060 if self.compact:
1061 self.get_compact_fragment(m, platform)
1062 else:
1063 self.get_longer_fragment(m, platform)
1064
1065 with m.FSM() as fsm:
1066
1067 for state in self.states:
1068 with m.State(state.state_from):
1069 state.action(m)
1070
1071 return m
1072
1073 def get_longer_fragment(self, m, platform=None):
1074
1075 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1076 self.in_a, self.in_b, self.width))
1077 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1078 a = get.out_op1
1079 b = get.out_op2
1080
1081 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1082 sc.setup(m, a, b, self.in_mid)
1083
1084 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1085 dn.setup(m, a, b, sc.in_mid)
1086
1087 if self.single_cycle:
1088 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1089 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1090 else:
1091 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1092 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1093
1094 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1095 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1096
1097 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1098 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1099
1100 n1 = self.add_state(FPNorm1(self.width, self.id_wid))
1101 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1102
1103 rn = self.add_state(FPRound(self.width, self.id_wid))
1104 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1105
1106 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1107 cor.setup(m, rn.out_z, rn.in_mid)
1108
1109 pa = self.add_state(FPPack(self.width, self.id_wid))
1110 pa.setup(m, cor.out_z, rn.in_mid)
1111
1112 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1113 pa.in_mid, self.out_mid))
1114
1115 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1116 pa.in_mid, self.out_mid))
1117
1118 def get_compact_fragment(self, m, platform=None):
1119
1120 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1121 self.in_a, self.in_b, self.width))
1122 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1123 a = get.out_op1
1124 b = get.out_op2
1125
1126 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1127 sc.setup(m, a, b, self.in_mid)
1128
1129 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1130 dn.setup(m, a, b, sc.in_mid)
1131
1132 if self.single_cycle:
1133 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1134 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1135 else:
1136 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1137 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1138
1139 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1140 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1141
1142 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1143 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1144
1145 n1 = self.add_state(FPNorm1(self.width, self.id_wid))
1146 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1147
1148 rn = self.add_state(FPRound(self.width, self.id_wid))
1149 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1150
1151 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1152 cor.setup(m, rn.out_z, rn.in_mid)
1153
1154 pa = self.add_state(FPPack(self.width, self.id_wid))
1155 pa.setup(m, cor.out_z, rn.in_mid)
1156
1157 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1158 pa.in_mid, self.out_mid))
1159
1160 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1161 pa.in_mid, self.out_mid))
1162
1163
1164 class FPADDBase(FPState, FPID):
1165
1166 def __init__(self, width, id_wid=None, single_cycle=False):
1167 """ IEEE754 FP Add
1168
1169 * width: bit-width of IEEE754. supported: 16, 32, 64
1170 * id_wid: an identifier that is sync-connected to the input
1171 * single_cycle: True indicates each stage to complete in 1 clock
1172 """
1173 FPID.__init__(self, id_wid)
1174 FPState.__init__(self, "fpadd")
1175 self.width = width
1176 self.single_cycle = single_cycle
1177 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1178
1179 self.in_t = Trigger()
1180 self.in_a = Signal(width)
1181 self.in_b = Signal(width)
1182 #self.out_z = FPOp(width)
1183
1184 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1185 self.in_accept = Signal(reset_less=True)
1186 self.add_stb = Signal(reset_less=True)
1187 self.add_ack = Signal(reset=0, reset_less=True)
1188
1189 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1190 self.out_z = out_z
1191 self.out_mid = out_mid
1192 m.d.comb += [self.in_a.eq(a),
1193 self.in_b.eq(b),
1194 self.mod.in_a.eq(self.in_a),
1195 self.mod.in_b.eq(self.in_b),
1196 self.in_mid.eq(in_mid),
1197 self.mod.in_mid.eq(self.in_mid),
1198 self.z_done.eq(self.mod.out_z.trigger),
1199 #self.add_stb.eq(add_stb),
1200 self.mod.in_t.stb.eq(self.in_t.stb),
1201 self.in_t.ack.eq(self.mod.in_t.ack),
1202 self.out_mid.eq(self.mod.out_mid),
1203 self.out_z.v.eq(self.mod.out_z.v),
1204 self.out_z.stb.eq(self.mod.out_z.stb),
1205 self.mod.out_z.ack.eq(self.out_z.ack),
1206 ]
1207
1208 m.d.sync += self.add_stb.eq(add_stb)
1209 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1210 #m.d.sync += self.in_t.stb.eq(0)
1211
1212 m.submodules.fpadd = self.mod
1213
1214 def action(self, m):
1215
1216 # in_accept is set on incoming strobe HIGH and ack LOW.
1217 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1218
1219 #with m.If(self.in_t.ack):
1220 # m.d.sync += self.in_t.stb.eq(0)
1221 with m.If(~self.z_done):
1222 # not done: test for accepting an incoming operand pair
1223 with m.If(self.in_accept):
1224 m.d.sync += [
1225 self.add_ack.eq(1), # acknowledge receipt...
1226 self.in_t.stb.eq(1), # initiate add
1227 ]
1228 with m.Else():
1229 m.d.sync += [self.add_ack.eq(0),
1230 self.in_t.stb.eq(0),
1231 ]
1232 with m.Else():
1233 # done: acknowledge, and write out id and value
1234 m.d.sync += [self.add_ack.eq(1),
1235 self.in_t.stb.eq(0)
1236 ]
1237 m.next = "get_a"
1238
1239 return
1240
1241 if self.in_mid is not None:
1242 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1243
1244 m.d.sync += [
1245 self.out_z.v.eq(self.mod.out_z.v)
1246 ]
1247 # move to output state on detecting z ack
1248 with m.If(self.out_z.trigger):
1249 m.d.sync += self.out_z.stb.eq(0)
1250 m.next = "put_z"
1251 with m.Else():
1252 m.d.sync += self.out_z.stb.eq(1)
1253
1254
1255 class FPADD(FPID):
1256 """ FPADD: stages as follows:
1257
1258 FPGetOp (a)
1259 |
1260 FPGetOp (b)
1261 |
1262 FPAddBase---> FPAddBaseMod
1263 | |
1264 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1265
1266 FPAddBase is tricky: it is both a stage and *has* stages.
1267 Connection to FPAddBaseMod therefore requires an in stb/ack
1268 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1269 needs to be the thing that raises the incoming stb.
1270 """
1271
1272 def __init__(self, width, id_wid=None, single_cycle=False):
1273 """ IEEE754 FP Add
1274
1275 * width: bit-width of IEEE754. supported: 16, 32, 64
1276 * id_wid: an identifier that is sync-connected to the input
1277 * single_cycle: True indicates each stage to complete in 1 clock
1278 """
1279 FPID.__init__(self, id_wid)
1280 self.width = width
1281 self.id_wid = id_wid
1282 self.single_cycle = single_cycle
1283
1284 self.in_a = FPOp(width)
1285 self.in_b = FPOp(width)
1286 self.out_z = FPOp(width)
1287
1288 self.states = []
1289
1290 def add_state(self, state):
1291 self.states.append(state)
1292 return state
1293
1294 def get_fragment(self, platform=None):
1295 """ creates the HDL code-fragment for FPAdd
1296 """
1297 m = Module()
1298 m.submodules.in_a = self.in_a
1299 m.submodules.in_b = self.in_b
1300 m.submodules.out_z = self.out_z
1301
1302 geta = self.add_state(FPGetOp("get_a", "get_b",
1303 self.in_a, self.width))
1304 geta.setup(m, self.in_a)
1305 a = geta.out_op
1306
1307 getb = self.add_state(FPGetOp("get_b", "fpadd",
1308 self.in_b, self.width))
1309 getb.setup(m, self.in_b)
1310 b = getb.out_op
1311
1312 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1313 ab = self.add_state(ab)
1314 ab.setup(m, a, b, getb.out_decode, self.in_mid,
1315 self.out_z, self.out_mid)
1316
1317 #pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
1318 # ab.out_mid, self.out_mid))
1319
1320 with m.FSM() as fsm:
1321
1322 for state in self.states:
1323 with m.State(state.state_from):
1324 state.action(m)
1325
1326 return m
1327
1328
1329 if __name__ == "__main__":
1330 if True:
1331 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1332 main(alu, ports=alu.in_a.ports() + \
1333 alu.in_b.ports() + \
1334 alu.out_z.ports() + \
1335 [alu.in_mid, alu.out_mid])
1336 else:
1337 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1338 main(alu, ports=[alu.in_a, alu.in_b] + \
1339 alu.in_t.ports() + \
1340 alu.out_z.ports() + \
1341 [alu.in_mid, alu.out_mid])
1342
1343
1344 # works... but don't use, just do "python fname.py convert -t v"
1345 #print (verilog.convert(alu, ports=[
1346 # ports=alu.in_a.ports() + \
1347 # alu.in_b.ports() + \
1348 # alu.out_z.ports())