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use ospec in FPAddSpecialCasesDeNorm module
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.a.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPAddAlignSingleMod:
587
588 def __init__(self, width):
589 self.width = width
590 self.in_a = FPNumBase(width)
591 self.in_b = FPNumBase(width)
592 self.out_a = FPNumIn(None, width)
593 self.out_b = FPNumIn(None, width)
594
595 def setup(self, m, in_a, in_b):
596 """ links module to inputs and outputs
597 """
598 m.submodules.align = self
599 m.d.comb += self.in_a.eq(in_a)
600 m.d.comb += self.in_b.eq(in_b)
601
602 def elaborate(self, platform):
603 """ Aligns A against B or B against A, depending on which has the
604 greater exponent. This is done in a *single* cycle using
605 variable-width bit-shift
606
607 the shifter used here is quite expensive in terms of gates.
608 Mux A or B in (and out) into temporaries, as only one of them
609 needs to be aligned against the other
610 """
611 m = Module()
612
613 m.submodules.align_in_a = self.in_a
614 m.submodules.align_in_b = self.in_b
615 m.submodules.align_out_a = self.out_a
616 m.submodules.align_out_b = self.out_b
617
618 # temporary (muxed) input and output to be shifted
619 t_inp = FPNumBase(self.width)
620 t_out = FPNumIn(None, self.width)
621 espec = (len(self.in_a.e), True)
622 msr = MultiShiftRMerge(self.in_a.m_width, espec)
623 m.submodules.align_t_in = t_inp
624 m.submodules.align_t_out = t_out
625 m.submodules.multishift_r = msr
626
627 ediff = Signal(espec, reset_less=True)
628 ediffr = Signal(espec, reset_less=True)
629 tdiff = Signal(espec, reset_less=True)
630 elz = Signal(reset_less=True)
631 egz = Signal(reset_less=True)
632
633 # connect multi-shifter to t_inp/out mantissa (and tdiff)
634 m.d.comb += msr.inp.eq(t_inp.m)
635 m.d.comb += msr.diff.eq(tdiff)
636 m.d.comb += t_out.m.eq(msr.m)
637 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
638 m.d.comb += t_out.s.eq(t_inp.s)
639
640 m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
641 m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
642 m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
643 m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
644
645 # default: A-exp == B-exp, A and B untouched (fall through)
646 m.d.comb += self.out_a.eq(self.in_a)
647 m.d.comb += self.out_b.eq(self.in_b)
648 # only one shifter (muxed)
649 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
650 # exponent of a greater than b: shift b down
651 with m.If(egz):
652 m.d.comb += [t_inp.eq(self.in_b),
653 tdiff.eq(ediff),
654 self.out_b.eq(t_out),
655 self.out_b.s.eq(self.in_b.s), # whoops forgot sign
656 ]
657 # exponent of b greater than a: shift a down
658 with m.Elif(elz):
659 m.d.comb += [t_inp.eq(self.in_a),
660 tdiff.eq(ediffr),
661 self.out_a.eq(t_out),
662 self.out_a.s.eq(self.in_a.s), # whoops forgot sign
663 ]
664 return m
665
666
667 class FPAddAlignSingle(FPState, FPID):
668
669 def __init__(self, width, id_wid):
670 FPState.__init__(self, "align")
671 FPID.__init__(self, id_wid)
672 self.mod = FPAddAlignSingleMod(width)
673 self.out_a = FPNumIn(None, width)
674 self.out_b = FPNumIn(None, width)
675
676 def setup(self, m, in_a, in_b, in_mid):
677 """ links module to inputs and outputs
678 """
679 self.mod.setup(m, in_a, in_b)
680 if self.in_mid is not None:
681 m.d.comb += self.in_mid.eq(in_mid)
682
683 def action(self, m):
684 self.idsync(m)
685 # NOTE: could be done as comb
686 m.d.sync += self.out_a.eq(self.mod.out_a)
687 m.d.sync += self.out_b.eq(self.mod.out_b)
688 m.next = "add_0"
689
690
691 class FPAddAlignSingleAdd(FPState, FPID):
692
693 def __init__(self, width, id_wid):
694 FPState.__init__(self, "align")
695 FPID.__init__(self, id_wid)
696 self.mod = FPAddAlignSingleMod(width)
697 self.out_a = FPNumIn(None, width)
698 self.out_b = FPNumIn(None, width)
699
700 self.a0mod = FPAddStage0Mod(width)
701 self.a0_out_z = FPNumBase(width, False)
702 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
703 self.a0_out_z = FPNumBase(width, False)
704
705 self.a1mod = FPAddStage1Mod(width)
706 self.out_z = FPNumBase(width, False)
707 self.out_of = Overflow()
708
709 def setup(self, m, in_a, in_b, in_mid):
710 """ links module to inputs and outputs
711 """
712 self.mod.setup(m, in_a, in_b)
713 m.d.comb += self.out_a.eq(self.mod.out_a)
714 m.d.comb += self.out_b.eq(self.mod.out_b)
715
716 self.a0mod.setup(m, self.out_a, self.out_b)
717 m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
718 m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
719
720 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
721
722 if self.in_mid is not None:
723 m.d.comb += self.in_mid.eq(in_mid)
724
725 def action(self, m):
726 self.idsync(m)
727 m.d.sync += self.out_of.eq(self.a1mod.out_of)
728 m.d.sync += self.out_z.eq(self.a1mod.out_z)
729 m.next = "normalise_1"
730
731
732 class FPAddStage0Mod:
733
734 def __init__(self, width):
735 self.in_a = FPNumBase(width)
736 self.in_b = FPNumBase(width)
737 self.in_z = FPNumBase(width, False)
738 self.out_z = FPNumBase(width, False)
739 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
740
741 def setup(self, m, in_a, in_b):
742 """ links module to inputs and outputs
743 """
744 m.submodules.add0 = self
745 m.d.comb += self.in_a.eq(in_a)
746 m.d.comb += self.in_b.eq(in_b)
747
748 def elaborate(self, platform):
749 m = Module()
750 m.submodules.add0_in_a = self.in_a
751 m.submodules.add0_in_b = self.in_b
752 m.submodules.add0_out_z = self.out_z
753
754 m.d.comb += self.out_z.e.eq(self.in_a.e)
755
756 # store intermediate tests (and zero-extended mantissas)
757 seq = Signal(reset_less=True)
758 mge = Signal(reset_less=True)
759 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
760 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
761 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
762 mge.eq(self.in_a.m >= self.in_b.m),
763 am0.eq(Cat(self.in_a.m, 0)),
764 bm0.eq(Cat(self.in_b.m, 0))
765 ]
766 # same-sign (both negative or both positive) add mantissas
767 with m.If(seq):
768 m.d.comb += [
769 self.out_tot.eq(am0 + bm0),
770 self.out_z.s.eq(self.in_a.s)
771 ]
772 # a mantissa greater than b, use a
773 with m.Elif(mge):
774 m.d.comb += [
775 self.out_tot.eq(am0 - bm0),
776 self.out_z.s.eq(self.in_a.s)
777 ]
778 # b mantissa greater than a, use b
779 with m.Else():
780 m.d.comb += [
781 self.out_tot.eq(bm0 - am0),
782 self.out_z.s.eq(self.in_b.s)
783 ]
784 return m
785
786
787 class FPAddStage0(FPState, FPID):
788 """ First stage of add. covers same-sign (add) and subtract
789 special-casing when mantissas are greater or equal, to
790 give greatest accuracy.
791 """
792
793 def __init__(self, width, id_wid):
794 FPState.__init__(self, "add_0")
795 FPID.__init__(self, id_wid)
796 self.mod = FPAddStage0Mod(width)
797 self.out_z = FPNumBase(width, False)
798 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
799
800 def setup(self, m, in_a, in_b, in_mid):
801 """ links module to inputs and outputs
802 """
803 self.mod.setup(m, in_a, in_b)
804 if self.in_mid is not None:
805 m.d.comb += self.in_mid.eq(in_mid)
806
807 def action(self, m):
808 self.idsync(m)
809 # NOTE: these could be done as combinatorial (merge add0+add1)
810 m.d.sync += self.out_z.eq(self.mod.out_z)
811 m.d.sync += self.out_tot.eq(self.mod.out_tot)
812 m.next = "add_1"
813
814
815 class FPAddStage1Mod(FPState):
816 """ Second stage of add: preparation for normalisation.
817 detects when tot sum is too big (tot[27] is kinda a carry bit)
818 """
819
820 def __init__(self, width):
821 self.out_norm = Signal(reset_less=True)
822 self.in_z = FPNumBase(width, False)
823 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
824 self.out_z = FPNumBase(width, False)
825 self.out_of = Overflow()
826
827 def setup(self, m, in_tot, in_z):
828 """ links module to inputs and outputs
829 """
830 m.submodules.add1 = self
831 m.submodules.add1_out_overflow = self.out_of
832
833 m.d.comb += self.in_z.eq(in_z)
834 m.d.comb += self.in_tot.eq(in_tot)
835
836 def elaborate(self, platform):
837 m = Module()
838 #m.submodules.norm1_in_overflow = self.in_of
839 #m.submodules.norm1_out_overflow = self.out_of
840 #m.submodules.norm1_in_z = self.in_z
841 #m.submodules.norm1_out_z = self.out_z
842 m.d.comb += self.out_z.eq(self.in_z)
843 # tot[-1] (MSB) gets set when the sum overflows. shift result down
844 with m.If(self.in_tot[-1]):
845 m.d.comb += [
846 self.out_z.m.eq(self.in_tot[4:]),
847 self.out_of.m0.eq(self.in_tot[4]),
848 self.out_of.guard.eq(self.in_tot[3]),
849 self.out_of.round_bit.eq(self.in_tot[2]),
850 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
851 self.out_z.e.eq(self.in_z.e + 1)
852 ]
853 # tot[-1] (MSB) zero case
854 with m.Else():
855 m.d.comb += [
856 self.out_z.m.eq(self.in_tot[3:]),
857 self.out_of.m0.eq(self.in_tot[3]),
858 self.out_of.guard.eq(self.in_tot[2]),
859 self.out_of.round_bit.eq(self.in_tot[1]),
860 self.out_of.sticky.eq(self.in_tot[0])
861 ]
862 return m
863
864
865 class FPAddStage1(FPState, FPID):
866
867 def __init__(self, width, id_wid):
868 FPState.__init__(self, "add_1")
869 FPID.__init__(self, id_wid)
870 self.mod = FPAddStage1Mod(width)
871 self.out_z = FPNumBase(width, False)
872 self.out_of = Overflow()
873 self.norm_stb = Signal()
874
875 def setup(self, m, in_tot, in_z, in_mid):
876 """ links module to inputs and outputs
877 """
878 self.mod.setup(m, in_tot, in_z)
879
880 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
881
882 if self.in_mid is not None:
883 m.d.comb += self.in_mid.eq(in_mid)
884
885 def action(self, m):
886 self.idsync(m)
887 m.d.sync += self.out_of.eq(self.mod.out_of)
888 m.d.sync += self.out_z.eq(self.mod.out_z)
889 m.d.sync += self.norm_stb.eq(1)
890 m.next = "normalise_1"
891
892
893 class FPNormaliseModSingle:
894
895 def __init__(self, width):
896 self.width = width
897 self.in_z = FPNumBase(width, False)
898 self.out_z = FPNumBase(width, False)
899
900 def setup(self, m, in_z, out_z, modname):
901 """ links module to inputs and outputs
902 """
903 m.submodules.normalise = self
904 m.d.comb += self.in_z.eq(in_z)
905 m.d.comb += out_z.eq(self.out_z)
906
907 def elaborate(self, platform):
908 m = Module()
909
910 mwid = self.out_z.m_width+2
911 pe = PriorityEncoder(mwid)
912 m.submodules.norm_pe = pe
913
914 m.submodules.norm1_out_z = self.out_z
915 m.submodules.norm1_in_z = self.in_z
916
917 in_z = FPNumBase(self.width, False)
918 in_of = Overflow()
919 m.submodules.norm1_insel_z = in_z
920 m.submodules.norm1_insel_overflow = in_of
921
922 espec = (len(in_z.e), True)
923 ediff_n126 = Signal(espec, reset_less=True)
924 msr = MultiShiftRMerge(mwid, espec)
925 m.submodules.multishift_r = msr
926
927 m.d.comb += in_z.eq(self.in_z)
928 m.d.comb += in_of.eq(self.in_of)
929 # initialise out from in (overridden below)
930 m.d.comb += self.out_z.eq(in_z)
931 m.d.comb += self.out_of.eq(in_of)
932 # normalisation increase/decrease conditions
933 decrease = Signal(reset_less=True)
934 m.d.comb += decrease.eq(in_z.m_msbzero)
935 # decrease exponent
936 with m.If(decrease):
937 # *sigh* not entirely obvious: count leading zeros (clz)
938 # with a PriorityEncoder: to find from the MSB
939 # we reverse the order of the bits.
940 temp_m = Signal(mwid, reset_less=True)
941 temp_s = Signal(mwid+1, reset_less=True)
942 clz = Signal((len(in_z.e), True), reset_less=True)
943 m.d.comb += [
944 # cat round and guard bits back into the mantissa
945 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
946 pe.i.eq(temp_m[::-1]), # inverted
947 clz.eq(pe.o), # count zeros from MSB down
948 temp_s.eq(temp_m << clz), # shift mantissa UP
949 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
950 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
951 ]
952
953 return m
954
955
956 class FPNorm1ModSingle:
957
958 def __init__(self, width):
959 self.width = width
960 self.out_norm = Signal(reset_less=True)
961 self.in_z = FPNumBase(width, False)
962 self.in_of = Overflow()
963 self.out_z = FPNumBase(width, False)
964 self.out_of = Overflow()
965
966 def setup(self, m, in_z, in_of, out_z):
967 """ links module to inputs and outputs
968 """
969 m.submodules.normalise_1 = self
970
971 m.d.comb += self.in_z.eq(in_z)
972 m.d.comb += self.in_of.eq(in_of)
973
974 m.d.comb += out_z.eq(self.out_z)
975
976 def elaborate(self, platform):
977 m = Module()
978
979 mwid = self.out_z.m_width+2
980 pe = PriorityEncoder(mwid)
981 m.submodules.norm_pe = pe
982
983 m.submodules.norm1_out_z = self.out_z
984 m.submodules.norm1_out_overflow = self.out_of
985 m.submodules.norm1_in_z = self.in_z
986 m.submodules.norm1_in_overflow = self.in_of
987
988 in_z = FPNumBase(self.width, False)
989 in_of = Overflow()
990 m.submodules.norm1_insel_z = in_z
991 m.submodules.norm1_insel_overflow = in_of
992
993 espec = (len(in_z.e), True)
994 ediff_n126 = Signal(espec, reset_less=True)
995 msr = MultiShiftRMerge(mwid, espec)
996 m.submodules.multishift_r = msr
997
998 m.d.comb += in_z.eq(self.in_z)
999 m.d.comb += in_of.eq(self.in_of)
1000 # initialise out from in (overridden below)
1001 m.d.comb += self.out_z.eq(in_z)
1002 m.d.comb += self.out_of.eq(in_of)
1003 # normalisation increase/decrease conditions
1004 decrease = Signal(reset_less=True)
1005 increase = Signal(reset_less=True)
1006 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1007 m.d.comb += increase.eq(in_z.exp_lt_n126)
1008 # decrease exponent
1009 with m.If(decrease):
1010 # *sigh* not entirely obvious: count leading zeros (clz)
1011 # with a PriorityEncoder: to find from the MSB
1012 # we reverse the order of the bits.
1013 temp_m = Signal(mwid, reset_less=True)
1014 temp_s = Signal(mwid+1, reset_less=True)
1015 clz = Signal((len(in_z.e), True), reset_less=True)
1016 # make sure that the amount to decrease by does NOT
1017 # go below the minimum non-INF/NaN exponent
1018 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1019 in_z.exp_sub_n126)
1020 m.d.comb += [
1021 # cat round and guard bits back into the mantissa
1022 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1023 pe.i.eq(temp_m[::-1]), # inverted
1024 clz.eq(limclz), # count zeros from MSB down
1025 temp_s.eq(temp_m << clz), # shift mantissa UP
1026 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1027 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1028 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1029 # overflow in bits 0..1: got shifted too (leave sticky)
1030 self.out_of.guard.eq(temp_s[1]), # guard
1031 self.out_of.round_bit.eq(temp_s[0]), # round
1032 ]
1033 # increase exponent
1034 with m.Elif(increase):
1035 temp_m = Signal(mwid+1, reset_less=True)
1036 m.d.comb += [
1037 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1038 in_z.m)),
1039 ediff_n126.eq(in_z.N126 - in_z.e),
1040 # connect multi-shifter to inp/out mantissa (and ediff)
1041 msr.inp.eq(temp_m),
1042 msr.diff.eq(ediff_n126),
1043 self.out_z.m.eq(msr.m[3:]),
1044 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1045 # overflow in bits 0..1: got shifted too (leave sticky)
1046 self.out_of.guard.eq(temp_s[2]), # guard
1047 self.out_of.round_bit.eq(temp_s[1]), # round
1048 self.out_of.sticky.eq(temp_s[0]), # sticky
1049 self.out_z.e.eq(in_z.e + ediff_n126),
1050 ]
1051
1052 return m
1053
1054
1055 class FPNorm1ModMulti:
1056
1057 def __init__(self, width, single_cycle=True):
1058 self.width = width
1059 self.in_select = Signal(reset_less=True)
1060 self.out_norm = Signal(reset_less=True)
1061 self.in_z = FPNumBase(width, False)
1062 self.in_of = Overflow()
1063 self.temp_z = FPNumBase(width, False)
1064 self.temp_of = Overflow()
1065 self.out_z = FPNumBase(width, False)
1066 self.out_of = Overflow()
1067
1068 def elaborate(self, platform):
1069 m = Module()
1070
1071 m.submodules.norm1_out_z = self.out_z
1072 m.submodules.norm1_out_overflow = self.out_of
1073 m.submodules.norm1_temp_z = self.temp_z
1074 m.submodules.norm1_temp_of = self.temp_of
1075 m.submodules.norm1_in_z = self.in_z
1076 m.submodules.norm1_in_overflow = self.in_of
1077
1078 in_z = FPNumBase(self.width, False)
1079 in_of = Overflow()
1080 m.submodules.norm1_insel_z = in_z
1081 m.submodules.norm1_insel_overflow = in_of
1082
1083 # select which of temp or in z/of to use
1084 with m.If(self.in_select):
1085 m.d.comb += in_z.eq(self.in_z)
1086 m.d.comb += in_of.eq(self.in_of)
1087 with m.Else():
1088 m.d.comb += in_z.eq(self.temp_z)
1089 m.d.comb += in_of.eq(self.temp_of)
1090 # initialise out from in (overridden below)
1091 m.d.comb += self.out_z.eq(in_z)
1092 m.d.comb += self.out_of.eq(in_of)
1093 # normalisation increase/decrease conditions
1094 decrease = Signal(reset_less=True)
1095 increase = Signal(reset_less=True)
1096 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1097 m.d.comb += increase.eq(in_z.exp_lt_n126)
1098 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1099 # decrease exponent
1100 with m.If(decrease):
1101 m.d.comb += [
1102 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1103 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1104 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1105 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1106 self.out_of.round_bit.eq(0), # reset round bit
1107 self.out_of.m0.eq(in_of.guard),
1108 ]
1109 # increase exponent
1110 with m.Elif(increase):
1111 m.d.comb += [
1112 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1113 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1114 self.out_of.guard.eq(in_z.m[0]),
1115 self.out_of.m0.eq(in_z.m[1]),
1116 self.out_of.round_bit.eq(in_of.guard),
1117 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1118 ]
1119
1120 return m
1121
1122
1123 class FPNorm1Single(FPState, FPID):
1124
1125 def __init__(self, width, id_wid, single_cycle=True):
1126 FPID.__init__(self, id_wid)
1127 FPState.__init__(self, "normalise_1")
1128 self.mod = FPNorm1ModSingle(width)
1129 self.out_norm = Signal(reset_less=True)
1130 self.out_z = FPNumBase(width)
1131 self.out_roundz = Signal(reset_less=True)
1132
1133 def setup(self, m, in_z, in_of, in_mid):
1134 """ links module to inputs and outputs
1135 """
1136 self.mod.setup(m, in_z, in_of, self.out_z)
1137
1138 if self.in_mid is not None:
1139 m.d.comb += self.in_mid.eq(in_mid)
1140
1141 def action(self, m):
1142 self.idsync(m)
1143 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1144 m.next = "round"
1145
1146
1147 class FPNorm1Multi(FPState, FPID):
1148
1149 def __init__(self, width, id_wid):
1150 FPID.__init__(self, id_wid)
1151 FPState.__init__(self, "normalise_1")
1152 self.mod = FPNorm1ModMulti(width)
1153 self.stb = Signal(reset_less=True)
1154 self.ack = Signal(reset=0, reset_less=True)
1155 self.out_norm = Signal(reset_less=True)
1156 self.in_accept = Signal(reset_less=True)
1157 self.temp_z = FPNumBase(width)
1158 self.temp_of = Overflow()
1159 self.out_z = FPNumBase(width)
1160 self.out_roundz = Signal(reset_less=True)
1161
1162 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1163 """ links module to inputs and outputs
1164 """
1165 self.mod.setup(m, in_z, in_of, norm_stb,
1166 self.in_accept, self.temp_z, self.temp_of,
1167 self.out_z, self.out_norm)
1168
1169 m.d.comb += self.stb.eq(norm_stb)
1170 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1171
1172 if self.in_mid is not None:
1173 m.d.comb += self.in_mid.eq(in_mid)
1174
1175 def action(self, m):
1176 self.idsync(m)
1177 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1178 m.d.sync += self.temp_of.eq(self.mod.out_of)
1179 m.d.sync += self.temp_z.eq(self.out_z)
1180 with m.If(self.out_norm):
1181 with m.If(self.in_accept):
1182 m.d.sync += [
1183 self.ack.eq(1),
1184 ]
1185 with m.Else():
1186 m.d.sync += self.ack.eq(0)
1187 with m.Else():
1188 # normalisation not required (or done).
1189 m.next = "round"
1190 m.d.sync += self.ack.eq(1)
1191 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1192
1193
1194 class FPNormToPack(FPState, FPID):
1195
1196 def __init__(self, width, id_wid):
1197 FPID.__init__(self, id_wid)
1198 FPState.__init__(self, "normalise_1")
1199 self.width = width
1200
1201 def setup(self, m, in_z, in_of, in_mid):
1202 """ links module to inputs and outputs
1203 """
1204
1205 # Normalisation (chained to input in_z+in_of)
1206 nmod = FPNorm1ModSingle(self.width)
1207 n_out_z = FPNumBase(self.width)
1208 n_out_roundz = Signal(reset_less=True)
1209 nmod.setup(m, in_z, in_of, n_out_z)
1210
1211 # Rounding (chained to normalisation)
1212 rmod = FPRoundMod(self.width)
1213 r_out_z = FPNumBase(self.width)
1214 rmod.setup(m, n_out_z, n_out_roundz)
1215 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1216 m.d.comb += r_out_z.eq(rmod.out_z)
1217
1218 # Corrections (chained to rounding)
1219 cmod = FPCorrectionsMod(self.width)
1220 c_out_z = FPNumBase(self.width)
1221 cmod.setup(m, r_out_z)
1222 m.d.comb += c_out_z.eq(cmod.out_z)
1223
1224 # Pack (chained to corrections)
1225 self.pmod = FPPackMod(self.width)
1226 self.out_z = FPNumBase(self.width)
1227 self.pmod.setup(m, c_out_z)
1228
1229 # Multiplex ID
1230 if self.in_mid is not None:
1231 m.d.comb += self.in_mid.eq(in_mid)
1232
1233 def action(self, m):
1234 self.idsync(m) # copies incoming ID to outgoing
1235 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1236 m.next = "pack_put_z"
1237
1238
1239 class FPRoundMod:
1240
1241 def __init__(self, width):
1242 self.in_roundz = Signal(reset_less=True)
1243 self.in_z = FPNumBase(width, False)
1244 self.out_z = FPNumBase(width, False)
1245
1246 def setup(self, m, in_z, roundz):
1247 m.submodules.roundz = self
1248
1249 m.d.comb += self.in_z.eq(in_z)
1250 m.d.comb += self.in_roundz.eq(roundz)
1251
1252 def elaborate(self, platform):
1253 m = Module()
1254 m.d.comb += self.out_z.eq(self.in_z)
1255 with m.If(self.in_roundz):
1256 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1257 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1258 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1259 return m
1260
1261
1262 class FPRound(FPState, FPID):
1263
1264 def __init__(self, width, id_wid):
1265 FPState.__init__(self, "round")
1266 FPID.__init__(self, id_wid)
1267 self.mod = FPRoundMod(width)
1268 self.out_z = FPNumBase(width)
1269
1270 def setup(self, m, in_z, roundz, in_mid):
1271 """ links module to inputs and outputs
1272 """
1273 self.mod.setup(m, in_z, roundz)
1274
1275 if self.in_mid is not None:
1276 m.d.comb += self.in_mid.eq(in_mid)
1277
1278 def action(self, m):
1279 self.idsync(m)
1280 m.d.sync += self.out_z.eq(self.mod.out_z)
1281 m.next = "corrections"
1282
1283
1284 class FPCorrectionsMod:
1285
1286 def __init__(self, width):
1287 self.in_z = FPNumOut(width, False)
1288 self.out_z = FPNumOut(width, False)
1289
1290 def setup(self, m, in_z):
1291 """ links module to inputs and outputs
1292 """
1293 m.submodules.corrections = self
1294 m.d.comb += self.in_z.eq(in_z)
1295
1296 def elaborate(self, platform):
1297 m = Module()
1298 m.submodules.corr_in_z = self.in_z
1299 m.submodules.corr_out_z = self.out_z
1300 m.d.comb += self.out_z.eq(self.in_z)
1301 with m.If(self.in_z.is_denormalised):
1302 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1303 return m
1304
1305
1306 class FPCorrections(FPState, FPID):
1307
1308 def __init__(self, width, id_wid):
1309 FPState.__init__(self, "corrections")
1310 FPID.__init__(self, id_wid)
1311 self.mod = FPCorrectionsMod(width)
1312 self.out_z = FPNumBase(width)
1313
1314 def setup(self, m, in_z, in_mid):
1315 """ links module to inputs and outputs
1316 """
1317 self.mod.setup(m, in_z)
1318 if self.in_mid is not None:
1319 m.d.comb += self.in_mid.eq(in_mid)
1320
1321 def action(self, m):
1322 self.idsync(m)
1323 m.d.sync += self.out_z.eq(self.mod.out_z)
1324 m.next = "pack"
1325
1326
1327 class FPPackMod:
1328
1329 def __init__(self, width):
1330 self.in_z = FPNumOut(width, False)
1331 self.out_z = FPNumOut(width, False)
1332
1333 def setup(self, m, in_z):
1334 """ links module to inputs and outputs
1335 """
1336 m.submodules.pack = self
1337 m.d.comb += self.in_z.eq(in_z)
1338
1339 def elaborate(self, platform):
1340 m = Module()
1341 m.submodules.pack_in_z = self.in_z
1342 with m.If(self.in_z.is_overflowed):
1343 m.d.comb += self.out_z.inf(self.in_z.s)
1344 with m.Else():
1345 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1346 return m
1347
1348
1349 class FPPack(FPState, FPID):
1350
1351 def __init__(self, width, id_wid):
1352 FPState.__init__(self, "pack")
1353 FPID.__init__(self, id_wid)
1354 self.mod = FPPackMod(width)
1355 self.out_z = FPNumOut(width, False)
1356
1357 def setup(self, m, in_z, in_mid):
1358 """ links module to inputs and outputs
1359 """
1360 self.mod.setup(m, in_z)
1361 if self.in_mid is not None:
1362 m.d.comb += self.in_mid.eq(in_mid)
1363
1364 def action(self, m):
1365 self.idsync(m)
1366 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1367 m.next = "pack_put_z"
1368
1369
1370 class FPPutZ(FPState):
1371
1372 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1373 FPState.__init__(self, state)
1374 if to_state is None:
1375 to_state = "get_ops"
1376 self.to_state = to_state
1377 self.in_z = in_z
1378 self.out_z = out_z
1379 self.in_mid = in_mid
1380 self.out_mid = out_mid
1381
1382 def action(self, m):
1383 if self.in_mid is not None:
1384 m.d.sync += self.out_mid.eq(self.in_mid)
1385 m.d.sync += [
1386 self.out_z.v.eq(self.in_z.v)
1387 ]
1388 with m.If(self.out_z.stb & self.out_z.ack):
1389 m.d.sync += self.out_z.stb.eq(0)
1390 m.next = self.to_state
1391 with m.Else():
1392 m.d.sync += self.out_z.stb.eq(1)
1393
1394
1395 class FPPutZIdx(FPState):
1396
1397 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1398 FPState.__init__(self, state)
1399 if to_state is None:
1400 to_state = "get_ops"
1401 self.to_state = to_state
1402 self.in_z = in_z
1403 self.out_zs = out_zs
1404 self.in_mid = in_mid
1405
1406 def action(self, m):
1407 outz_stb = Signal(reset_less=True)
1408 outz_ack = Signal(reset_less=True)
1409 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1410 outz_ack.eq(self.out_zs[self.in_mid].ack),
1411 ]
1412 m.d.sync += [
1413 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1414 ]
1415 with m.If(outz_stb & outz_ack):
1416 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1417 m.next = self.to_state
1418 with m.Else():
1419 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1420
1421
1422 class FPADDBaseMod(FPID):
1423
1424 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1425 """ IEEE754 FP Add
1426
1427 * width: bit-width of IEEE754. supported: 16, 32, 64
1428 * id_wid: an identifier that is sync-connected to the input
1429 * single_cycle: True indicates each stage to complete in 1 clock
1430 * compact: True indicates a reduced number of stages
1431 """
1432 FPID.__init__(self, id_wid)
1433 self.width = width
1434 self.single_cycle = single_cycle
1435 self.compact = compact
1436
1437 self.in_t = Trigger()
1438 self.in_a = Signal(width)
1439 self.in_b = Signal(width)
1440 self.out_z = FPOp(width)
1441
1442 self.states = []
1443
1444 def add_state(self, state):
1445 self.states.append(state)
1446 return state
1447
1448 def get_fragment(self, platform=None):
1449 """ creates the HDL code-fragment for FPAdd
1450 """
1451 m = Module()
1452 m.submodules.out_z = self.out_z
1453 m.submodules.in_t = self.in_t
1454 if self.compact:
1455 self.get_compact_fragment(m, platform)
1456 else:
1457 self.get_longer_fragment(m, platform)
1458
1459 with m.FSM() as fsm:
1460
1461 for state in self.states:
1462 with m.State(state.state_from):
1463 state.action(m)
1464
1465 return m
1466
1467 def get_longer_fragment(self, m, platform=None):
1468
1469 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1470 self.in_a, self.in_b, self.width))
1471 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1472 a = get.out_op1
1473 b = get.out_op2
1474
1475 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1476 sc.setup(m, a, b, self.in_mid)
1477
1478 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1479 dn.setup(m, a, b, sc.in_mid)
1480
1481 if self.single_cycle:
1482 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1483 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1484 else:
1485 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1486 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1487
1488 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1489 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1490
1491 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1492 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1493
1494 if self.single_cycle:
1495 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1496 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1497 else:
1498 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1499 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1500
1501 rn = self.add_state(FPRound(self.width, self.id_wid))
1502 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1503
1504 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1505 cor.setup(m, rn.out_z, rn.in_mid)
1506
1507 pa = self.add_state(FPPack(self.width, self.id_wid))
1508 pa.setup(m, cor.out_z, rn.in_mid)
1509
1510 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1511 pa.in_mid, self.out_mid))
1512
1513 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1514 pa.in_mid, self.out_mid))
1515
1516 def get_compact_fragment(self, m, platform=None):
1517
1518 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1519 self.in_a, self.in_b, self.width))
1520 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1521 a = get.out_op1
1522 b = get.out_op2
1523
1524 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1525 sc.setup(m, a, b, self.in_mid)
1526
1527 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1528 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1529
1530 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1531 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1532
1533 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1534 n1.in_mid, self.out_mid))
1535
1536 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1537 sc.in_mid, self.out_mid))
1538
1539
1540 class FPADDBase(FPState, FPID):
1541
1542 def __init__(self, width, id_wid=None, single_cycle=False):
1543 """ IEEE754 FP Add
1544
1545 * width: bit-width of IEEE754. supported: 16, 32, 64
1546 * id_wid: an identifier that is sync-connected to the input
1547 * single_cycle: True indicates each stage to complete in 1 clock
1548 """
1549 FPID.__init__(self, id_wid)
1550 FPState.__init__(self, "fpadd")
1551 self.width = width
1552 self.single_cycle = single_cycle
1553 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1554
1555 self.in_t = Trigger()
1556 self.in_a = Signal(width)
1557 self.in_b = Signal(width)
1558 #self.out_z = FPOp(width)
1559
1560 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1561 self.in_accept = Signal(reset_less=True)
1562 self.add_stb = Signal(reset_less=True)
1563 self.add_ack = Signal(reset=0, reset_less=True)
1564
1565 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1566 self.out_z = out_z
1567 self.out_mid = out_mid
1568 m.d.comb += [self.in_a.eq(a),
1569 self.in_b.eq(b),
1570 self.mod.in_a.eq(self.in_a),
1571 self.mod.in_b.eq(self.in_b),
1572 self.in_mid.eq(in_mid),
1573 self.mod.in_mid.eq(self.in_mid),
1574 self.z_done.eq(self.mod.out_z.trigger),
1575 #self.add_stb.eq(add_stb),
1576 self.mod.in_t.stb.eq(self.in_t.stb),
1577 self.in_t.ack.eq(self.mod.in_t.ack),
1578 self.out_mid.eq(self.mod.out_mid),
1579 self.out_z.v.eq(self.mod.out_z.v),
1580 self.out_z.stb.eq(self.mod.out_z.stb),
1581 self.mod.out_z.ack.eq(self.out_z.ack),
1582 ]
1583
1584 m.d.sync += self.add_stb.eq(add_stb)
1585 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1586 m.d.sync += self.out_z.ack.eq(0) # likewise
1587 #m.d.sync += self.in_t.stb.eq(0)
1588
1589 m.submodules.fpadd = self.mod
1590
1591 def action(self, m):
1592
1593 # in_accept is set on incoming strobe HIGH and ack LOW.
1594 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1595
1596 #with m.If(self.in_t.ack):
1597 # m.d.sync += self.in_t.stb.eq(0)
1598 with m.If(~self.z_done):
1599 # not done: test for accepting an incoming operand pair
1600 with m.If(self.in_accept):
1601 m.d.sync += [
1602 self.add_ack.eq(1), # acknowledge receipt...
1603 self.in_t.stb.eq(1), # initiate add
1604 ]
1605 with m.Else():
1606 m.d.sync += [self.add_ack.eq(0),
1607 self.in_t.stb.eq(0),
1608 self.out_z.ack.eq(1),
1609 ]
1610 with m.Else():
1611 # done: acknowledge, and write out id and value
1612 m.d.sync += [self.add_ack.eq(1),
1613 self.in_t.stb.eq(0)
1614 ]
1615 m.next = "put_z"
1616
1617 return
1618
1619 if self.in_mid is not None:
1620 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1621
1622 m.d.sync += [
1623 self.out_z.v.eq(self.mod.out_z.v)
1624 ]
1625 # move to output state on detecting z ack
1626 with m.If(self.out_z.trigger):
1627 m.d.sync += self.out_z.stb.eq(0)
1628 m.next = "put_z"
1629 with m.Else():
1630 m.d.sync += self.out_z.stb.eq(1)
1631
1632 class ResArray:
1633 def __init__(self, width, id_wid):
1634 self.width = width
1635 self.id_wid = id_wid
1636 res = []
1637 for i in range(rs_sz):
1638 out_z = FPOp(width)
1639 out_z.name = "out_z_%d" % i
1640 res.append(out_z)
1641 self.res = Array(res)
1642 self.in_z = FPOp(width)
1643 self.in_mid = Signal(self.id_wid, reset_less=True)
1644
1645 def setup(self, m, in_z, in_mid):
1646 m.d.comb += [self.in_z.eq(in_z),
1647 self.in_mid.eq(in_mid)]
1648
1649 def get_fragment(self, platform=None):
1650 """ creates the HDL code-fragment for FPAdd
1651 """
1652 m = Module()
1653 m.submodules.res_in_z = self.in_z
1654 m.submodules += self.res
1655
1656 return m
1657
1658 def ports(self):
1659 res = []
1660 for z in self.res:
1661 res += z.ports()
1662 return res
1663
1664
1665 class FPADD(FPID):
1666 """ FPADD: stages as follows:
1667
1668 FPGetOp (a)
1669 |
1670 FPGetOp (b)
1671 |
1672 FPAddBase---> FPAddBaseMod
1673 | |
1674 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1675
1676 FPAddBase is tricky: it is both a stage and *has* stages.
1677 Connection to FPAddBaseMod therefore requires an in stb/ack
1678 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1679 needs to be the thing that raises the incoming stb.
1680 """
1681
1682 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1683 """ IEEE754 FP Add
1684
1685 * width: bit-width of IEEE754. supported: 16, 32, 64
1686 * id_wid: an identifier that is sync-connected to the input
1687 * single_cycle: True indicates each stage to complete in 1 clock
1688 """
1689 self.width = width
1690 self.id_wid = id_wid
1691 self.single_cycle = single_cycle
1692
1693 #self.out_z = FPOp(width)
1694 self.ids = FPID(id_wid)
1695
1696 rs = []
1697 for i in range(rs_sz):
1698 in_a = FPOp(width)
1699 in_b = FPOp(width)
1700 in_a.name = "in_a_%d" % i
1701 in_b.name = "in_b_%d" % i
1702 rs.append((in_a, in_b))
1703 self.rs = Array(rs)
1704
1705 res = []
1706 for i in range(rs_sz):
1707 out_z = FPOp(width)
1708 out_z.name = "out_z_%d" % i
1709 res.append(out_z)
1710 self.res = Array(res)
1711
1712 self.states = []
1713
1714 def add_state(self, state):
1715 self.states.append(state)
1716 return state
1717
1718 def get_fragment(self, platform=None):
1719 """ creates the HDL code-fragment for FPAdd
1720 """
1721 m = Module()
1722 m.submodules += self.rs
1723
1724 in_a = self.rs[0][0]
1725 in_b = self.rs[0][1]
1726
1727 out_z = FPOp(self.width)
1728 out_mid = Signal(self.id_wid, reset_less=True)
1729 m.submodules.out_z = out_z
1730
1731 geta = self.add_state(FPGetOp("get_a", "get_b",
1732 in_a, self.width))
1733 geta.setup(m, in_a)
1734 a = geta.out_op
1735
1736 getb = self.add_state(FPGetOp("get_b", "fpadd",
1737 in_b, self.width))
1738 getb.setup(m, in_b)
1739 b = getb.out_op
1740
1741 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1742 ab = self.add_state(ab)
1743 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1744 out_z, out_mid)
1745
1746 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1747 out_mid, "get_a"))
1748
1749 with m.FSM() as fsm:
1750
1751 for state in self.states:
1752 with m.State(state.state_from):
1753 state.action(m)
1754
1755 return m
1756
1757
1758 if __name__ == "__main__":
1759 if True:
1760 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1761 main(alu, ports=alu.rs[0][0].ports() + \
1762 alu.rs[0][1].ports() + \
1763 alu.res[0].ports() + \
1764 [alu.ids.in_mid, alu.ids.out_mid])
1765 else:
1766 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1767 main(alu, ports=[alu.in_a, alu.in_b] + \
1768 alu.in_t.ports() + \
1769 alu.out_z.ports() + \
1770 [alu.in_mid, alu.out_mid])
1771
1772
1773 # works... but don't use, just do "python fname.py convert -t v"
1774 #print (verilog.convert(alu, ports=[
1775 # ports=alu.in_a.ports() + \
1776 # alu.in_b.ports() + \
1777 # alu.out_z.ports())