src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def setup(self, m, in_op, out_op, out_decode):
  35         """ links module to inputs and outputs
  36         """
  37         m.d.comb += self.in_op.copy(in_op)
  38         m.d.comb += out_op.v.eq(self.out_op.v)
  39         m.d.comb += out_decode.eq(self.out_decode)
  40
  41     def elaborate(self, platform):
  42         m = Module()
  43         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  44         #m.submodules.get_op_in = self.in_op
  45         m.submodules.get_op_out = self.out_op
  46         with m.If(self.out_decode):
  47             m.d.comb += [
  48                 self.out_op.decode(self.in_op.v),
  49             ]
  50         return m
  51
  52
  53 class FPGetOp(FPState):
  54     """ gets operand
  55     """
  56
  57     def __init__(self, in_state, out_state, in_op, width):
  58         FPState.__init__(self, in_state)
  59         self.out_state = out_state
  60         self.mod = FPGetOpMod(width)
  61         self.in_op = in_op
  62         self.out_op = FPNumIn(in_op, width)
  63         self.out_decode = Signal(reset_less=True)
  64
  65     def action(self, m):
  66         with m.If(self.out_decode):
  67             m.next = self.out_state
  68             m.d.sync += [
  69                 self.in_op.ack.eq(0),
  70                 self.out_op.copy(self.mod.out_op)
  71             ]
  72         with m.Else():
  73             m.d.sync += self.in_op.ack.eq(1)
  74
  75
  76 class FPGetOpB(FPState):
  77     """ gets operand b
  78     """
  79
  80     def __init__(self, in_b, width):
  81         FPState.__init__(self, "get_b")
  82         self.in_b = in_b
  83         self.b = FPNumIn(self.in_b, width)
  84
  85     def action(self, m):
  86         self.get_op(m, self.in_b, self.b, "special_cases")
  87
  88
  89 class FPAddSpecialCasesMod:
  90     """ special cases: NaNs, infs, zeros, denormalised
  91         NOTE: some of these are unique to add.  see "Special Operations"
  92         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  93     """
  94
  95     def __init__(self, width):
  96         self.in_a = FPNumBase(width)
  97         self.in_b = FPNumBase(width)
  98         self.out_z = FPNumOut(width, False)
  99         self.out_do_z = Signal(reset_less=True)
 100
 101     def setup(self, m, in_a, in_b, out_z, out_do_z):
 102         """ links module to inputs and outputs
 103         """
 104         m.d.comb += self.in_a.copy(in_a)
 105         m.d.comb += self.in_b.copy(in_b)
 106         #m.d.comb += out_z.v.eq(self.out_z.v)
 107         m.d.comb += out_do_z.eq(self.out_do_z)
 108
 109     def elaborate(self, platform):
 110         m = Module()
 111
 112         m.submodules.sc_in_a = self.in_a
 113         m.submodules.sc_in_b = self.in_b
 114         m.submodules.sc_out_z = self.out_z
 115
 116         s_nomatch = Signal()
 117         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
 118
 119         m_match = Signal()
 120         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 121
 122         # if a is NaN or b is NaN return NaN
 123         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 124             m.d.comb += self.out_do_z.eq(1)
 125             m.d.comb += self.out_z.nan(0)
 126
 127         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 128         # under review
 129
 130         ## if a is zero and b is NaN return -b
 131         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 132         #    m.d.comb += self.out_do_z.eq(1)
 133         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 134
 135         ## if b is zero and a is NaN return -a
 136         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 137         #    m.d.comb += self.out_do_z.eq(1)
 138         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 139
 140         ## if a is -zero and b is NaN return -b
 141         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 142         #    m.d.comb += self.out_do_z.eq(1)
 143         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 144
 145         ## if b is -zero and a is NaN return -a
 146         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 147         #    m.d.comb += self.out_do_z.eq(1)
 148         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 149
 150         # if a is inf return inf (or NaN)
 151         with m.Elif(self.in_a.is_inf):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.inf(self.in_a.s)
 154             # if a is inf and signs don't match return NaN
 155             with m.If(self.in_b.exp_128 & s_nomatch):
 156                 m.d.comb += self.out_z.nan(0)
 157
 158         # if b is inf return inf
 159         with m.Elif(self.in_b.is_inf):
 160             m.d.comb += self.out_do_z.eq(1)
 161             m.d.comb += self.out_z.inf(self.in_b.s)
 162
 163         # if a is zero and b zero return signed-a/b
 164         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 165             m.d.comb += self.out_do_z.eq(1)
 166             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 167                                           self.in_b.e,
 168                                           self.in_b.m[3:-1])
 169
 170         # if a is zero return b
 171         with m.Elif(self.in_a.is_zero):
 172             m.d.comb += self.out_do_z.eq(1)
 173             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 174                                       self.in_b.m[3:-1])
 175
 176         # if b is zero return a
 177         with m.Elif(self.in_b.is_zero):
 178             m.d.comb += self.out_do_z.eq(1)
 179             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 180                                       self.in_a.m[3:-1])
 181
 182         # if a equal to -b return zero (+ve zero)
 183         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 184             m.d.comb += self.out_do_z.eq(1)
 185             m.d.comb += self.out_z.zero(0)
 186
 187         # Denormalised Number checks
 188         with m.Else():
 189             m.d.comb += self.out_do_z.eq(0)
 190
 191         return m
 192
 193
 194 class FPAddSpecialCases(FPState):
 195     """ special cases: NaNs, infs, zeros, denormalised
 196         NOTE: some of these are unique to add.  see "Special Operations"
 197         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 198     """
 199
 200     def __init__(self, width):
 201         FPState.__init__(self, "special_cases")
 202         self.mod = FPAddSpecialCasesMod(width)
 203         self.out_z = FPNumOut(width, False)
 204         self.out_do_z = Signal(reset_less=True)
 205
 206     def action(self, m):
 207         with m.If(self.out_do_z):
 208             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 209             m.next = "put_z"
 210         with m.Else():
 211             m.next = "denormalise"
 212
 213
 214 class FPAddDeNormMod(FPState):
 215
 216     def __init__(self, width):
 217         self.in_a = FPNumBase(width)
 218         self.in_b = FPNumBase(width)
 219         self.out_a = FPNumBase(width)
 220         self.out_b = FPNumBase(width)
 221
 222     def setup(self, m, in_a, in_b, out_a, out_b):
 223         """ links module to inputs and outputs
 224         """
 225         m.d.comb += self.in_a.copy(in_a)
 226         m.d.comb += self.in_b.copy(in_b)
 227
 228     def elaborate(self, platform):
 229         m = Module()
 230         m.submodules.denorm_in_a = self.in_a
 231         m.submodules.denorm_in_b = self.in_b
 232         m.submodules.denorm_out_a = self.out_a
 233         m.submodules.denorm_out_b = self.out_b
 234         # hmmm, don't like repeating identical code
 235         m.d.comb += self.out_a.copy(self.in_a)
 236         with m.If(self.in_a.exp_n127):
 237             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 238         with m.Else():
 239             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 240
 241         m.d.comb += self.out_b.copy(self.in_b)
 242         with m.If(self.in_b.exp_n127):
 243             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 244         with m.Else():
 245             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 246
 247         return m
 248
 249
 250 class FPAddDeNorm(FPState):
 251
 252     def __init__(self, width):
 253         FPState.__init__(self, "denormalise")
 254         self.mod = FPAddDeNormMod(width)
 255         self.out_a = FPNumBase(width)
 256         self.out_b = FPNumBase(width)
 257
 258     def action(self, m):
 259         # Denormalised Number checks
 260         m.next = "align"
 261         m.d.sync += self.out_a.copy(self.mod.out_a)
 262         m.d.sync += self.out_b.copy(self.mod.out_b)
 263
 264
 265 class FPAddAlignMultiMod(FPState):
 266
 267     def __init__(self, width):
 268         self.in_a = FPNumBase(width)
 269         self.in_b = FPNumBase(width)
 270         self.out_a = FPNumIn(None, width)
 271         self.out_b = FPNumIn(None, width)
 272         self.exp_eq = Signal(reset_less=True)
 273
 274     def elaborate(self, platform):
 275         # This one however (single-cycle) will do the shift
 276         # in one go.
 277
 278         m = Module()
 279
 280         m.submodules.align_in_a = self.in_a
 281         m.submodules.align_in_b = self.in_b
 282         m.submodules.align_out_a = self.out_a
 283         m.submodules.align_out_b = self.out_b
 284
 285         # NOTE: this does *not* do single-cycle multi-shifting,
 286         #       it *STAYS* in the align state until exponents match
 287
 288         # exponent of a greater than b: shift b down
 289         m.d.comb += self.exp_eq.eq(0)
 290         m.d.comb += self.out_a.copy(self.in_a)
 291         m.d.comb += self.out_b.copy(self.in_b)
 292         agtb = Signal(reset_less=True)
 293         altb = Signal(reset_less=True)
 294         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 295         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 296         with m.If(agtb):
 297             m.d.comb += self.out_b.shift_down(self.in_b)
 298         # exponent of b greater than a: shift a down
 299         with m.Elif(altb):
 300             m.d.comb += self.out_a.shift_down(self.in_a)
 301         # exponents equal: move to next stage.
 302         with m.Else():
 303             m.d.comb += self.exp_eq.eq(1)
 304         return m
 305
 306
 307 class FPAddAlignMulti(FPState):
 308
 309     def __init__(self, width):
 310         FPState.__init__(self, "align")
 311         self.mod = FPAddAlignMultiMod(width)
 312         self.out_a = FPNumIn(None, width)
 313         self.out_b = FPNumIn(None, width)
 314         self.exp_eq = Signal(reset_less=True)
 315
 316     def setup(self, m, in_a, in_b):
 317         """ links module to inputs and outputs
 318         """
 319         m.submodules.align = self.mod
 320         m.d.comb += self.mod.in_a.copy(in_a)
 321         m.d.comb += self.mod.in_b.copy(in_b)
 322         #m.d.comb += self.out_a.copy(self.mod.out_a)
 323         #m.d.comb += self.out_b.copy(self.mod.out_b)
 324         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 325
 326     def action(self, m):
 327         m.d.sync += self.out_a.copy(self.mod.out_a)
 328         m.d.sync += self.out_b.copy(self.mod.out_b)
 329         with m.If(self.exp_eq):
 330             m.next = "add_0"
 331
 332
 333 class FPAddAlignSingleMod:
 334
 335     def __init__(self, width):
 336         self.width = width
 337         self.in_a = FPNumBase(width)
 338         self.in_b = FPNumBase(width)
 339         self.out_a = FPNumIn(None, width)
 340         self.out_b = FPNumIn(None, width)
 341
 342     def elaborate(self, platform):
 343         """ Aligns A against B or B against A, depending on which has the
 344             greater exponent.  This is done in a *single* cycle using
 345             variable-width bit-shift
 346
 347             the shifter used here is quite expensive in terms of gates.
 348             Mux A or B in (and out) into temporaries, as only one of them
 349             needs to be aligned against the other
 350         """
 351         m = Module()
 352
 353         m.submodules.align_in_a = self.in_a
 354         m.submodules.align_in_b = self.in_b
 355         m.submodules.align_out_a = self.out_a
 356         m.submodules.align_out_b = self.out_b
 357
 358         # temporary (muxed) input and output to be shifted
 359         t_inp = FPNumBase(self.width)
 360         t_out = FPNumIn(None, self.width)
 361         espec = (len(self.in_a.e), True)
 362         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 363         m.submodules.align_t_in = t_inp
 364         m.submodules.align_t_out = t_out
 365         m.submodules.multishift_r = msr
 366
 367         ediff = Signal(espec, reset_less=True)
 368         ediffr = Signal(espec, reset_less=True)
 369         tdiff = Signal(espec, reset_less=True)
 370         elz = Signal(reset_less=True)
 371         egz = Signal(reset_less=True)
 372
 373         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 374         m.d.comb += msr.inp.eq(t_inp.m)
 375         m.d.comb += msr.diff.eq(tdiff)
 376         m.d.comb += t_out.m.eq(msr.m)
 377         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 378         m.d.comb += t_out.s.eq(t_inp.s)
 379
 380         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 381         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 382         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 383         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 384
 385         # default: A-exp == B-exp, A and B untouched (fall through)
 386         m.d.comb += self.out_a.copy(self.in_a)
 387         m.d.comb += self.out_b.copy(self.in_b)
 388         # only one shifter (muxed)
 389         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 390         # exponent of a greater than b: shift b down
 391         with m.If(egz):
 392             m.d.comb += [t_inp.copy(self.in_b),
 393                          tdiff.eq(ediff),
 394                          self.out_b.copy(t_out),
 395                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 396                         ]
 397         # exponent of b greater than a: shift a down
 398         with m.Elif(elz):
 399             m.d.comb += [t_inp.copy(self.in_a),
 400                          tdiff.eq(ediffr),
 401                          self.out_a.copy(t_out),
 402                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 403                         ]
 404         return m
 405
 406
 407 class FPAddAlignSingle(FPState):
 408
 409     def __init__(self, width):
 410         FPState.__init__(self, "align")
 411         self.mod = FPAddAlignSingleMod(width)
 412         self.out_a = FPNumIn(None, width)
 413         self.out_b = FPNumIn(None, width)
 414
 415     def setup(self, m, in_a, in_b):
 416         """ links module to inputs and outputs
 417         """
 418         m.submodules.align = self.mod
 419         m.d.comb += self.mod.in_a.copy(in_a)
 420         m.d.comb += self.mod.in_b.copy(in_b)
 421
 422     def action(self, m):
 423         # NOTE: could be done as comb
 424         m.d.sync += self.out_a.copy(self.mod.out_a)
 425         m.d.sync += self.out_b.copy(self.mod.out_b)
 426         m.next = "add_0"
 427
 428
 429 class FPAddStage0Mod:
 430
 431     def __init__(self, width):
 432         self.in_a = FPNumBase(width)
 433         self.in_b = FPNumBase(width)
 434         self.in_z = FPNumBase(width, False)
 435         self.out_z = FPNumBase(width, False)
 436         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 437
 438     def elaborate(self, platform):
 439         m = Module()
 440         m.submodules.add0_in_a = self.in_a
 441         m.submodules.add0_in_b = self.in_b
 442         m.submodules.add0_out_z = self.out_z
 443
 444         m.d.comb += self.out_z.e.eq(self.in_a.e)
 445
 446         # store intermediate tests (and zero-extended mantissas)
 447         seq = Signal(reset_less=True)
 448         mge = Signal(reset_less=True)
 449         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 450         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 451         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 452                      mge.eq(self.in_a.m >= self.in_b.m),
 453                      am0.eq(Cat(self.in_a.m, 0)),
 454                      bm0.eq(Cat(self.in_b.m, 0))
 455                     ]
 456         # same-sign (both negative or both positive) add mantissas
 457         with m.If(seq):
 458             m.d.comb += [
 459                 self.out_tot.eq(am0 + bm0),
 460                 self.out_z.s.eq(self.in_a.s)
 461             ]
 462         # a mantissa greater than b, use a
 463         with m.Elif(mge):
 464             m.d.comb += [
 465                 self.out_tot.eq(am0 - bm0),
 466                 self.out_z.s.eq(self.in_a.s)
 467             ]
 468         # b mantissa greater than a, use b
 469         with m.Else():
 470             m.d.comb += [
 471                 self.out_tot.eq(bm0 - am0),
 472                 self.out_z.s.eq(self.in_b.s)
 473         ]
 474         return m
 475
 476
 477 class FPAddStage0(FPState):
 478     """ First stage of add.  covers same-sign (add) and subtract
 479         special-casing when mantissas are greater or equal, to
 480         give greatest accuracy.
 481     """
 482
 483     def __init__(self, width):
 484         FPState.__init__(self, "add_0")
 485         self.mod = FPAddStage0Mod(width)
 486         self.out_z = FPNumBase(width, False)
 487         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 488
 489     def setup(self, m, in_a, in_b):
 490         """ links module to inputs and outputs
 491         """
 492         m.submodules.add0 = self.mod
 493
 494         m.d.comb += self.mod.in_a.copy(in_a)
 495         m.d.comb += self.mod.in_b.copy(in_b)
 496
 497     def action(self, m):
 498         m.next = "add_1"
 499         # NOTE: these could be done as combinatorial (merge add0+add1)
 500         m.d.sync += self.out_z.copy(self.mod.out_z)
 501         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 502
 503
 504 class FPAddStage1Mod(FPState):
 505     """ Second stage of add: preparation for normalisation.
 506         detects when tot sum is too big (tot[27] is kinda a carry bit)
 507     """
 508
 509     def __init__(self, width):
 510         self.out_norm = Signal(reset_less=True)
 511         self.in_z = FPNumBase(width, False)
 512         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 513         self.out_z = FPNumBase(width, False)
 514         self.out_of = Overflow()
 515
 516     def elaborate(self, platform):
 517         m = Module()
 518         #m.submodules.norm1_in_overflow = self.in_of
 519         #m.submodules.norm1_out_overflow = self.out_of
 520         #m.submodules.norm1_in_z = self.in_z
 521         #m.submodules.norm1_out_z = self.out_z
 522         m.d.comb += self.out_z.copy(self.in_z)
 523         # tot[27] gets set when the sum overflows. shift result down
 524         with m.If(self.in_tot[-1]):
 525             m.d.comb += [
 526                 self.out_z.m.eq(self.in_tot[4:]),
 527                 self.out_of.m0.eq(self.in_tot[4]),
 528                 self.out_of.guard.eq(self.in_tot[3]),
 529                 self.out_of.round_bit.eq(self.in_tot[2]),
 530                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 531                 self.out_z.e.eq(self.in_z.e + 1)
 532         ]
 533         # tot[27] zero case
 534         with m.Else():
 535             m.d.comb += [
 536                 self.out_z.m.eq(self.in_tot[3:]),
 537                 self.out_of.m0.eq(self.in_tot[3]),
 538                 self.out_of.guard.eq(self.in_tot[2]),
 539                 self.out_of.round_bit.eq(self.in_tot[1]),
 540                 self.out_of.sticky.eq(self.in_tot[0])
 541         ]
 542         return m
 543
 544
 545 class FPAddStage1(FPState):
 546
 547     def __init__(self, width):
 548         FPState.__init__(self, "add_1")
 549         self.mod = FPAddStage1Mod(width)
 550         self.out_z = FPNumBase(width, False)
 551         self.out_of = Overflow()
 552         self.norm_stb = Signal()
 553
 554     def setup(self, m, in_tot, in_z):
 555         """ links module to inputs and outputs
 556         """
 557         m.submodules.add1 = self.mod
 558
 559         m.d.comb += self.mod.in_z.copy(in_z)
 560         m.d.comb += self.mod.in_tot.eq(in_tot)
 561
 562         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 563
 564     def action(self, m):
 565         m.submodules.add1_out_overflow = self.out_of
 566         m.d.sync += self.out_of.copy(self.mod.out_of)
 567         m.d.sync += self.out_z.copy(self.mod.out_z)
 568         m.d.sync += self.norm_stb.eq(1)
 569         m.next = "normalise_1"
 570
 571
 572 class FPNorm1ModSingle:
 573
 574     def __init__(self, width):
 575         self.width = width
 576         self.in_select = Signal(reset_less=True)
 577         self.out_norm = Signal(reset_less=True)
 578         self.in_z = FPNumBase(width, False)
 579         self.in_of = Overflow()
 580         self.temp_z = FPNumBase(width, False)
 581         self.temp_of = Overflow()
 582         self.out_z = FPNumBase(width, False)
 583         self.out_of = Overflow()
 584
 585     def elaborate(self, platform):
 586         m = Module()
 587
 588         mwid = self.out_z.m_width+2
 589         pe = PriorityEncoder(mwid)
 590         m.submodules.norm_pe = pe
 591
 592         m.submodules.norm1_out_z = self.out_z
 593         m.submodules.norm1_out_overflow = self.out_of
 594         m.submodules.norm1_temp_z = self.temp_z
 595         m.submodules.norm1_temp_of = self.temp_of
 596         m.submodules.norm1_in_z = self.in_z
 597         m.submodules.norm1_in_overflow = self.in_of
 598
 599         in_z = FPNumBase(self.width, False)
 600         in_of = Overflow()
 601         m.submodules.norm1_insel_z = in_z
 602         m.submodules.norm1_insel_overflow = in_of
 603
 604         espec = (len(in_z.e), True)
 605         ediff_n126 = Signal(espec, reset_less=True)
 606         msr = MultiShiftRMerge(mwid, espec)
 607         m.submodules.multishift_r = msr
 608
 609         # select which of temp or in z/of to use
 610         with m.If(self.in_select):
 611             m.d.comb += in_z.copy(self.in_z)
 612             m.d.comb += in_of.copy(self.in_of)
 613         with m.Else():
 614             m.d.comb += in_z.copy(self.temp_z)
 615             m.d.comb += in_of.copy(self.temp_of)
 616         # initialise out from in (overridden below)
 617         m.d.comb += self.out_z.copy(in_z)
 618         m.d.comb += self.out_of.copy(in_of)
 619         # normalisation increase/decrease conditions
 620         decrease = Signal(reset_less=True)
 621         increase = Signal(reset_less=True)
 622         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 623         m.d.comb += increase.eq(in_z.exp_lt_n126)
 624         m.d.comb += self.out_norm.eq(0) # loop-end condition
 625         # decrease exponent
 626         with m.If(decrease):
 627             # *sigh* not entirely obvious: count leading zeros (clz)
 628             # with a PriorityEncoder: to find from the MSB
 629             # we reverse the order of the bits.
 630             temp_m = Signal(mwid, reset_less=True)
 631             temp_s = Signal(mwid+1, reset_less=True)
 632             clz = Signal((len(in_z.e), True), reset_less=True)
 633             # make sure that the amount to decrease by does NOT
 634             # go below the minimum non-INF/NaN exponent
 635             limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 636                          in_z.exp_sub_n126)
 637             m.d.comb += [
 638                 # cat round and guard bits back into the mantissa
 639                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 640                 pe.i.eq(temp_m[::-1]),          # inverted
 641                 clz.eq(limclz),                 # count zeros from MSB down
 642                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 643                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 644                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 645                 self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 646                 # overflow in bits 0..1: got shifted too (leave sticky)
 647                 self.out_of.guard.eq(temp_s[1]),     # guard
 648                 self.out_of.round_bit.eq(temp_s[0]), # round
 649             ]
 650         # increase exponent
 651         with m.Elif(increase):
 652             temp_m = Signal(mwid+1, reset_less=True)
 653             m.d.comb += [
 654                 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
 655                               in_z.m)),
 656                 ediff_n126.eq(in_z.N126 - in_z.e),
 657                 # connect multi-shifter to inp/out mantissa (and ediff)
 658                 msr.inp.eq(temp_m),
 659                 msr.diff.eq(ediff_n126),
 660                 self.out_z.m.eq(msr.m[3:]),
 661                 self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
 662                 # overflow in bits 0..1: got shifted too (leave sticky)
 663                 self.out_of.guard.eq(temp_s[2]),     # guard
 664                 self.out_of.round_bit.eq(temp_s[1]), # round
 665                 self.out_of.sticky.eq(temp_s[0]), # sticky
 666                 self.out_z.e.eq(in_z.e + ediff_n126),
 667             ]
 668
 669         return m
 670
 671
 672 class FPNorm1ModMulti:
 673
 674     def __init__(self, width, single_cycle=True):
 675         self.width = width
 676         self.in_select = Signal(reset_less=True)
 677         self.out_norm = Signal(reset_less=True)
 678         self.in_z = FPNumBase(width, False)
 679         self.in_of = Overflow()
 680         self.temp_z = FPNumBase(width, False)
 681         self.temp_of = Overflow()
 682         self.out_z = FPNumBase(width, False)
 683         self.out_of = Overflow()
 684
 685     def elaborate(self, platform):
 686         m = Module()
 687
 688         m.submodules.norm1_out_z = self.out_z
 689         m.submodules.norm1_out_overflow = self.out_of
 690         m.submodules.norm1_temp_z = self.temp_z
 691         m.submodules.norm1_temp_of = self.temp_of
 692         m.submodules.norm1_in_z = self.in_z
 693         m.submodules.norm1_in_overflow = self.in_of
 694
 695         in_z = FPNumBase(self.width, False)
 696         in_of = Overflow()
 697         m.submodules.norm1_insel_z = in_z
 698         m.submodules.norm1_insel_overflow = in_of
 699
 700         # select which of temp or in z/of to use
 701         with m.If(self.in_select):
 702             m.d.comb += in_z.copy(self.in_z)
 703             m.d.comb += in_of.copy(self.in_of)
 704         with m.Else():
 705             m.d.comb += in_z.copy(self.temp_z)
 706             m.d.comb += in_of.copy(self.temp_of)
 707         # initialise out from in (overridden below)
 708         m.d.comb += self.out_z.copy(in_z)
 709         m.d.comb += self.out_of.copy(in_of)
 710         # normalisation increase/decrease conditions
 711         decrease = Signal(reset_less=True)
 712         increase = Signal(reset_less=True)
 713         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 714         m.d.comb += increase.eq(in_z.exp_lt_n126)
 715         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 716         # decrease exponent
 717         with m.If(decrease):
 718             m.d.comb += [
 719                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 720                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 721                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 722                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 723                 self.out_of.round_bit.eq(0),        # reset round bit
 724                 self.out_of.m0.eq(in_of.guard),
 725             ]
 726         # increase exponent
 727         with m.Elif(increase):
 728             m.d.comb += [
 729                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 730                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 731                 self.out_of.guard.eq(in_z.m[0]),
 732                 self.out_of.m0.eq(in_z.m[1]),
 733                 self.out_of.round_bit.eq(in_of.guard),
 734                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 735             ]
 736
 737         return m
 738
 739
 740 class FPNorm1(FPState):
 741
 742     def __init__(self, width, single_cycle=True):
 743         FPState.__init__(self, "normalise_1")
 744         if single_cycle:
 745             self.mod = FPNorm1ModSingle(width)
 746         else:
 747             self.mod = FPNorm1ModMulti(width)
 748         self.stb = Signal(reset_less=True)
 749         self.ack = Signal(reset=0, reset_less=True)
 750         self.out_norm = Signal(reset_less=True)
 751         self.in_accept = Signal(reset_less=True)
 752         self.temp_z = FPNumBase(width)
 753         self.temp_of = Overflow()
 754         self.out_z = FPNumBase(width)
 755         self.out_roundz = Signal(reset_less=True)
 756
 757     def setup(self, m, in_z, in_of, norm_stb):
 758         """ links module to inputs and outputs
 759         """
 760         m.submodules.normalise_1 = self.mod
 761
 762         m.d.comb += self.mod.in_z.copy(in_z)
 763         m.d.comb += self.mod.in_of.copy(in_of)
 764
 765         m.d.comb += self.mod.in_select.eq(self.in_accept)
 766         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 767         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 768
 769         m.d.comb += self.out_z.copy(self.mod.out_z)
 770         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 771
 772         m.d.comb += self.stb.eq(norm_stb)
 773         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 774
 775     def action(self, m):
 776
 777         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 778         m.d.sync += self.temp_of.copy(self.mod.out_of)
 779         m.d.sync += self.temp_z.copy(self.out_z)
 780         with m.If(self.out_norm):
 781             with m.If(self.in_accept):
 782                 m.d.sync += [
 783                     self.ack.eq(1),
 784                 ]
 785             with m.Else():
 786                 m.d.sync += self.ack.eq(0)
 787         with m.Else():
 788             # normalisation not required (or done).
 789             m.next = "round"
 790             m.d.sync += self.ack.eq(1)
 791             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 792
 793
 794 class FPRoundMod:
 795
 796     def __init__(self, width):
 797         self.in_roundz = Signal(reset_less=True)
 798         self.in_z = FPNumBase(width, False)
 799         self.out_z = FPNumBase(width, False)
 800
 801     def elaborate(self, platform):
 802         m = Module()
 803         m.d.comb += self.out_z.copy(self.in_z)
 804         with m.If(self.in_roundz):
 805             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 806             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 807                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 808         return m
 809
 810
 811 class FPRound(FPState):
 812
 813     def __init__(self, width):
 814         FPState.__init__(self, "round")
 815         self.mod = FPRoundMod(width)
 816         self.out_z = FPNumBase(width)
 817
 818     def setup(self, m, in_z, roundz):
 819         """ links module to inputs and outputs
 820         """
 821         m.submodules.roundz = self.mod
 822
 823         m.d.comb += self.mod.in_z.copy(in_z)
 824         m.d.comb += self.mod.in_roundz.eq(roundz)
 825
 826     def action(self, m):
 827         m.d.sync += self.out_z.copy(self.mod.out_z)
 828         m.next = "corrections"
 829
 830
 831 class FPCorrectionsMod:
 832
 833     def __init__(self, width):
 834         self.in_z = FPNumOut(width, False)
 835         self.out_z = FPNumOut(width, False)
 836
 837     def elaborate(self, platform):
 838         m = Module()
 839         m.submodules.corr_in_z = self.in_z
 840         m.submodules.corr_out_z = self.out_z
 841         m.d.comb += self.out_z.copy(self.in_z)
 842         with m.If(self.in_z.is_denormalised):
 843             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 844
 845         #        with m.If(self.in_z.is_overflowed):
 846         #            m.d.comb += self.out_z.inf(self.in_z.s)
 847         #        with m.Else():
 848         #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 849         return m
 850
 851
 852 class FPCorrections(FPState):
 853
 854     def __init__(self, width):
 855         FPState.__init__(self, "corrections")
 856         self.mod = FPCorrectionsMod(width)
 857         self.out_z = FPNumBase(width)
 858
 859     def setup(self, m, in_z):
 860         """ links module to inputs and outputs
 861         """
 862         m.submodules.corrections = self.mod
 863         m.d.comb += self.mod.in_z.copy(in_z)
 864
 865     def action(self, m):
 866         m.d.sync += self.out_z.copy(self.mod.out_z)
 867         m.next = "pack"
 868
 869
 870 class FPPackMod:
 871
 872     def __init__(self, width):
 873         self.in_z = FPNumOut(width, False)
 874         self.out_z = FPNumOut(width, False)
 875
 876     def elaborate(self, platform):
 877         m = Module()
 878         m.submodules.pack_in_z = self.in_z
 879         with m.If(self.in_z.is_overflowed):
 880             m.d.comb += self.out_z.inf(self.in_z.s)
 881         with m.Else():
 882             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 883         return m
 884
 885
 886 class FPPack(FPState):
 887
 888     def __init__(self, width):
 889         FPState.__init__(self, "pack")
 890         self.mod = FPPackMod(width)
 891         self.out_z = FPNumOut(width, False)
 892
 893     def setup(self, m, in_z):
 894         """ links module to inputs and outputs
 895         """
 896         m.submodules.pack = self.mod
 897         m.d.comb += self.mod.in_z.copy(in_z)
 898
 899     def action(self, m):
 900         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 901         m.next = "pack_put_z"
 902
 903
 904 class FPPutZ(FPState):
 905
 906     def __init__(self, state, in_z, out_z):
 907         FPState.__init__(self, state)
 908         self.in_z = in_z
 909         self.out_z = out_z
 910
 911     def action(self, m):
 912         m.d.sync += [
 913           self.out_z.v.eq(self.in_z.v)
 914         ]
 915         with m.If(self.out_z.stb & self.out_z.ack):
 916             m.d.sync += self.out_z.stb.eq(0)
 917             m.next = "get_a"
 918         with m.Else():
 919             m.d.sync += self.out_z.stb.eq(1)
 920
 921
 922 class FPADD:
 923
 924     def __init__(self, width, single_cycle=False):
 925         self.width = width
 926         self.single_cycle = single_cycle
 927
 928         self.in_a  = FPOp(width)
 929         self.in_b  = FPOp(width)
 930         self.out_z = FPOp(width)
 931
 932         self.states = []
 933
 934     def add_state(self, state):
 935         self.states.append(state)
 936         return state
 937
 938     def get_fragment(self, platform=None):
 939         """ creates the HDL code-fragment for FPAdd
 940         """
 941         m = Module()
 942         m.submodules.in_a = self.in_a
 943         m.submodules.in_b = self.in_b
 944         m.submodules.out_z = self.out_z
 945
 946         geta = self.add_state(FPGetOp("get_a", "get_b",
 947                                       self.in_a, self.width))
 948         a = geta.out_op
 949         geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
 950         m.submodules.get_a = geta.mod
 951
 952         getb = self.add_state(FPGetOp("get_b", "special_cases",
 953                                       self.in_b, self.width))
 954         b = getb.out_op
 955         getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
 956         m.submodules.get_b = getb.mod
 957
 958         sc = self.add_state(FPAddSpecialCases(self.width))
 959         sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
 960         m.submodules.specialcases = sc.mod
 961
 962         dn = self.add_state(FPAddDeNorm(self.width))
 963         dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
 964         m.submodules.denormalise = dn.mod
 965
 966         if self.single_cycle:
 967             alm = self.add_state(FPAddAlignSingle(self.width))
 968             alm.setup(m, dn.out_a, dn.out_b)
 969         else:
 970             alm = self.add_state(FPAddAlignMulti(self.width))
 971             #alm.set_inputs({"a": a, "b": b})
 972             alm.setup(m, dn.out_a, dn.out_b)
 973
 974         add0 = self.add_state(FPAddStage0(self.width))
 975         add0.setup(m, alm.out_a, alm.out_b)
 976
 977         add1 = self.add_state(FPAddStage1(self.width))
 978         add1.setup(m, add0.out_tot, add0.out_z)
 979
 980         n1 = self.add_state(FPNorm1(self.width))
 981         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 982
 983         rn = self.add_state(FPRound(self.width))
 984         rn.setup(m, n1.out_z, n1.out_roundz)
 985
 986         cor = self.add_state(FPCorrections(self.width))
 987         cor.setup(m, rn.out_z)
 988
 989         pa = self.add_state(FPPack(self.width))
 990         pa.setup(m, cor.out_z)
 991
 992         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
 993
 994         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
 995
 996         with m.FSM() as fsm:
 997
 998             for state in self.states:
 999                 with m.State(state.state_from):
1000                     state.action(m)
1001
1002         return m
1003
1004
1005 if __name__ == "__main__":
1006     alu = FPADD(width=32, single_cycle=True)
1007     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
1008
1009
1010     # works... but don't use, just do "python fname.py convert -t v"
1011     #print (verilog.convert(alu, ports=[
1012     #                        ports=alu.in_a.ports() + \
1013     #                              alu.in_b.ports() + \
1014     #                              alu.out_z.ports())