src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 #from fpbase import FPNumShiftMultiRight
  13
  14
  15 class FPState(FPBase):
  16     def __init__(self, state_from):
  17         self.state_from = state_from
  18
  19     def set_inputs(self, inputs):
  20         self.inputs = inputs
  21         for k,v in inputs.items():
  22             setattr(self, k, v)
  23
  24     def set_outputs(self, outputs):
  25         self.outputs = outputs
  26         for k,v in outputs.items():
  27             setattr(self, k, v)
  28
  29
  30 class FPGetSyncOpsMod:
  31     def __init__(self, width, num_ops=2):
  32         self.width = width
  33         self.num_ops = num_ops
  34         inops = []
  35         outops = []
  36         for i in range(num_ops):
  37             inops.append(Signal(width, reset_less=True))
  38             outops.append(Signal(width, reset_less=True))
  39         self.in_op = inops
  40         self.out_op = outops
  41         self.stb = Signal(num_ops)
  42         self.ack = Signal()
  43         self.ready = Signal(reset_less=True)
  44         self.out_decode = Signal(reset_less=True)
  45
  46     def elaborate(self, platform):
  47         m = Module()
  48         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  49         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  50         with m.If(self.out_decode):
  51             for i in range(self.num_ops):
  52                 m.d.comb += [
  53                         self.out_op[i].eq(self.in_op[i]),
  54                 ]
  55         return m
  56
  57     def ports(self):
  58         return self.in_op + self.out_op + [self.stb, self.ack]
  59
  60
  61 class FPOps(Trigger):
  62     def __init__(self, width, num_ops):
  63         Trigger.__init__(self)
  64         self.width = width
  65         self.num_ops = num_ops
  66
  67         res = []
  68         for i in range(num_ops):
  69             res.append(Signal(width))
  70         self.v  = Array(res)
  71
  72     def ports(self):
  73         res = []
  74         for i in range(self.num_ops):
  75             res.append(self.v[i])
  76         res.append(self.ack)
  77         res.append(self.stb)
  78         return res
  79
  80
  81 class InputGroup:
  82     def __init__(self, width, num_ops=2, num_rows=4):
  83         self.width = width
  84         self.num_ops = num_ops
  85         self.num_rows = num_rows
  86         self.mmax = int(log(self.num_rows) / log(2))
  87         self.rs = []
  88         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  89         for i in range(num_rows):
  90             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  91         self.rs = Array(self.rs)
  92
  93         self.out_op = FPOps(width, num_ops)
  94
  95     def elaborate(self, platform):
  96         m = Module()
  97
  98         pe = PriorityEncoder(self.num_rows)
  99         m.submodules.selector = pe
 100         m.submodules.out_op = self.out_op
 101         m.submodules += self.rs
 102
 103         # connect priority encoder
 104         in_ready = []
 105         for i in range(self.num_rows):
 106             in_ready.append(self.rs[i].ready)
 107         m.d.comb += pe.i.eq(Cat(*in_ready))
 108
 109         active = Signal(reset_less=True)
 110         out_en = Signal(reset_less=True)
 111         m.d.comb += active.eq(~pe.n) # encoder active
 112         m.d.comb += out_en.eq(active & self.out_op.trigger)
 113
 114         # encoder active: ack relevant input, record MID, pass output
 115         with m.If(out_en):
 116             rs = self.rs[pe.o]
 117             m.d.sync += self.mid.eq(pe.o)
 118             m.d.sync += rs.ack.eq(0)
 119             m.d.sync += self.out_op.stb.eq(0)
 120             for j in range(self.num_ops):
 121                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 122         with m.Else():
 123             m.d.sync += self.out_op.stb.eq(1)
 124             # acks all default to zero
 125             for i in range(self.num_rows):
 126                 m.d.sync += self.rs[i].ack.eq(1)
 127
 128         return m
 129
 130     def ports(self):
 131         res = []
 132         for i in range(self.num_rows):
 133             inop = self.rs[i]
 134             res += inop.in_op + [inop.stb]
 135         return self.out_op.ports() + res + [self.mid]
 136
 137
 138 class FPGetOpMod:
 139     def __init__(self, width):
 140         self.in_op = FPOp(width)
 141         self.out_op = Signal(width)
 142         self.out_decode = Signal(reset_less=True)
 143
 144     def elaborate(self, platform):
 145         m = Module()
 146         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 147         m.submodules.get_op_in = self.in_op
 148         #m.submodules.get_op_out = self.out_op
 149         with m.If(self.out_decode):
 150             m.d.comb += [
 151                 self.out_op.eq(self.in_op.v),
 152             ]
 153         return m
 154
 155
 156 class FPGetOp(FPState):
 157     """ gets operand
 158     """
 159
 160     def __init__(self, in_state, out_state, in_op, width):
 161         FPState.__init__(self, in_state)
 162         self.out_state = out_state
 163         self.mod = FPGetOpMod(width)
 164         self.in_op = in_op
 165         self.out_op = Signal(width)
 166         self.out_decode = Signal(reset_less=True)
 167
 168     def setup(self, m, in_op):
 169         """ links module to inputs and outputs
 170         """
 171         setattr(m.submodules, self.state_from, self.mod)
 172         m.d.comb += self.mod.in_op.eq(in_op)
 173         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 174
 175     def action(self, m):
 176         with m.If(self.out_decode):
 177             m.next = self.out_state
 178             m.d.sync += [
 179                 self.in_op.ack.eq(0),
 180                 self.out_op.eq(self.mod.out_op)
 181             ]
 182         with m.Else():
 183             m.d.sync += self.in_op.ack.eq(1)
 184
 185
 186 class FPGet2OpMod(Trigger):
 187     def __init__(self, width, id_wid):
 188         Trigger.__init__(self)
 189         self.width = width
 190         self.id_wid = id_wid
 191         self.i = self.ispec()
 192         self.o = self.ospec()
 193
 194     def ispec(self):
 195         return FPADDBaseData(self.width, self.id_wid)
 196
 197     def ospec(self):
 198         return FPNumBase2Ops(self.width, self.id_wid)
 199
 200     def elaborate(self, platform):
 201         m = Trigger.elaborate(self, platform)
 202         m.submodules.get_op1_out = self.o.a
 203         m.submodules.get_op2_out = self.o.b
 204         out_op1 = FPNumIn(None, self.width)
 205         out_op2 = FPNumIn(None, self.width)
 206         with m.If(self.trigger):
 207             m.d.comb += [
 208                 out_op1.decode(self.i.a),
 209                 out_op2.decode(self.i.b),
 210                 self.o.a.eq(out_op1),
 211                 self.o.b.eq(out_op2),
 212             ]
 213         return m
 214
 215
 216 class FPGet2Op(FPState):
 217     """ gets operands
 218     """
 219
 220     def __init__(self, in_state, out_state, width, id_wid):
 221         FPState.__init__(self, in_state)
 222         self.out_state = out_state
 223         self.mod = FPGet2OpMod(width, id_wid)
 224         self.o = self.mod.ospec()
 225         self.in_stb = Signal(reset_less=True)
 226         self.out_ack = Signal(reset_less=True)
 227         self.out_decode = Signal(reset_less=True)
 228
 229     def setup(self, m, i, in_stb, in_ack):
 230         """ links module to inputs and outputs
 231         """
 232         m.submodules.get_ops = self.mod
 233         m.d.comb += self.mod.i.eq(i)
 234         m.d.comb += self.mod.stb.eq(in_stb)
 235         m.d.comb += self.out_ack.eq(self.mod.ack)
 236         m.d.comb += self.out_decode.eq(self.mod.trigger)
 237         m.d.comb += in_ack.eq(self.mod.ack)
 238
 239     def action(self, m):
 240         with m.If(self.out_decode):
 241             m.next = self.out_state
 242             m.d.sync += [
 243                 self.mod.ack.eq(0),
 244                 self.o.eq(self.mod.o),
 245             ]
 246         with m.Else():
 247             m.d.sync += self.mod.ack.eq(1)
 248
 249
 250 class FPNumBase2Ops:
 251
 252     def __init__(self, width, id_wid, m_extra=True):
 253         self.a = FPNumBase(width, m_extra)
 254         self.b = FPNumBase(width, m_extra)
 255         self.mid = Signal(id_wid, reset_less=True)
 256
 257     def eq(self, i):
 258         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 259
 260
 261 class FPAddSpecialCasesMod:
 262     """ special cases: NaNs, infs, zeros, denormalised
 263         NOTE: some of these are unique to add.  see "Special Operations"
 264         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 265     """
 266
 267     def __init__(self, width, id_wid):
 268         self.width = width
 269         self.id_wid = id_wid
 270         self.i = self.ispec()
 271         self.o = self.ospec()
 272         self.out_do_z = Signal(reset_less=True)
 273
 274     def ispec(self):
 275         return FPNumBase2Ops(self.width, self.id_wid)
 276
 277     def ospec(self):
 278         return FPPackData(self.width, self.id_wid)
 279
 280     def setup(self, m, i, out_do_z):
 281         """ links module to inputs and outputs
 282         """
 283         m.submodules.specialcases = self
 284         m.d.comb += self.i.eq(i)
 285         m.d.comb += out_do_z.eq(self.out_do_z)
 286
 287     def elaborate(self, platform):
 288         m = Module()
 289
 290         m.submodules.sc_in_a = self.i.a
 291         m.submodules.sc_in_b = self.i.b
 292         m.submodules.sc_out_z = self.o.z
 293
 294         s_nomatch = Signal()
 295         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 296
 297         m_match = Signal()
 298         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 299
 300         # if a is NaN or b is NaN return NaN
 301         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 302             m.d.comb += self.out_do_z.eq(1)
 303             m.d.comb += self.o.z.nan(0)
 304
 305         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 306         # under review
 307
 308         ## if a is zero and b is NaN return -b
 309         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 310         #    m.d.comb += self.out_do_z.eq(1)
 311         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 312
 313         ## if b is zero and a is NaN return -a
 314         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 315         #    m.d.comb += self.out_do_z.eq(1)
 316         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 317
 318         ## if a is -zero and b is NaN return -b
 319         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 320         #    m.d.comb += self.out_do_z.eq(1)
 321         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 322
 323         ## if b is -zero and a is NaN return -a
 324         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 325         #    m.d.comb += self.out_do_z.eq(1)
 326         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 327
 328         # if a is inf return inf (or NaN)
 329         with m.Elif(self.i.a.is_inf):
 330             m.d.comb += self.out_do_z.eq(1)
 331             m.d.comb += self.o.z.inf(self.i.a.s)
 332             # if a is inf and signs don't match return NaN
 333             with m.If(self.i.b.exp_128 & s_nomatch):
 334                 m.d.comb += self.o.z.nan(0)
 335
 336         # if b is inf return inf
 337         with m.Elif(self.i.b.is_inf):
 338             m.d.comb += self.out_do_z.eq(1)
 339             m.d.comb += self.o.z.inf(self.i.b.s)
 340
 341         # if a is zero and b zero return signed-a/b
 342         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 343             m.d.comb += self.out_do_z.eq(1)
 344             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 345                                           self.i.b.e,
 346                                           self.i.b.m[3:-1])
 347
 348         # if a is zero return b
 349         with m.Elif(self.i.a.is_zero):
 350             m.d.comb += self.out_do_z.eq(1)
 351             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 352                                       self.i.b.m[3:-1])
 353
 354         # if b is zero return a
 355         with m.Elif(self.i.b.is_zero):
 356             m.d.comb += self.out_do_z.eq(1)
 357             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 358                                       self.i.a.m[3:-1])
 359
 360         # if a equal to -b return zero (+ve zero)
 361         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 362             m.d.comb += self.out_do_z.eq(1)
 363             m.d.comb += self.o.z.zero(0)
 364
 365         # Denormalised Number checks
 366         with m.Else():
 367             m.d.comb += self.out_do_z.eq(0)
 368
 369         return m
 370
 371
 372 class FPID:
 373     def __init__(self, id_wid):
 374         self.id_wid = id_wid
 375         if self.id_wid:
 376             self.in_mid = Signal(id_wid, reset_less=True)
 377             self.out_mid = Signal(id_wid, reset_less=True)
 378         else:
 379             self.in_mid = None
 380             self.out_mid = None
 381
 382     def idsync(self, m):
 383         if self.id_wid is not None:
 384             m.d.sync += self.out_mid.eq(self.in_mid)
 385
 386
 387 class FPAddSpecialCases(FPState):
 388     """ special cases: NaNs, infs, zeros, denormalised
 389         NOTE: some of these are unique to add.  see "Special Operations"
 390         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 391     """
 392
 393     def __init__(self, width, id_wid):
 394         FPState.__init__(self, "special_cases")
 395         self.mod = FPAddSpecialCasesMod(width)
 396         self.out_z = self.mod.ospec()
 397         self.out_do_z = Signal(reset_less=True)
 398
 399     def setup(self, m, i):
 400         """ links module to inputs and outputs
 401         """
 402         self.mod.setup(m, i, self.out_do_z)
 403         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 404         m.d.sync += self.out_z.mid.eq(self.pmod.o.mid)  # (and mid)
 405
 406     def action(self, m):
 407         self.idsync(m)
 408         with m.If(self.out_do_z):
 409             m.next = "put_z"
 410         with m.Else():
 411             m.next = "denormalise"
 412
 413
 414 class FPAddSpecialCasesDeNorm(FPState):
 415     """ special cases: NaNs, infs, zeros, denormalised
 416         NOTE: some of these are unique to add.  see "Special Operations"
 417         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 418     """
 419
 420     def __init__(self, width, id_wid):
 421         FPState.__init__(self, "special_cases")
 422         self.smod = FPAddSpecialCasesMod(width, id_wid)
 423         self.out_z = self.smod.ospec()
 424         self.out_do_z = Signal(reset_less=True)
 425
 426         self.dmod = FPAddDeNormMod(width, id_wid)
 427         self.o = self.dmod.ospec()
 428
 429     def setup(self, m, i):
 430         """ links module to inputs and outputs
 431         """
 432         self.smod.setup(m, i, self.out_do_z)
 433         self.dmod.setup(m, i)
 434
 435         # out_do_z=True
 436         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 437         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 438         # out_do_z=False
 439         m.d.sync += self.o.eq(self.dmod.o)
 440
 441     def action(self, m):
 442         with m.If(self.out_do_z):
 443             m.next = "put_z"
 444         with m.Else():
 445             m.next = "align"
 446
 447
 448 class FPAddDeNormMod(FPState):
 449
 450     def __init__(self, width, id_wid):
 451         self.width = width
 452         self.id_wid = id_wid
 453         self.i = self.ispec()
 454         self.o = self.ospec()
 455
 456     def ispec(self):
 457         return FPNumBase2Ops(self.width, self.id_wid)
 458
 459     def ospec(self):
 460         return FPNumBase2Ops(self.width, self.id_wid)
 461
 462     def setup(self, m, i):
 463         """ links module to inputs and outputs
 464         """
 465         m.submodules.denormalise = self
 466         m.d.comb += self.i.eq(i)
 467
 468     def elaborate(self, platform):
 469         m = Module()
 470         m.submodules.denorm_in_a = self.i.a
 471         m.submodules.denorm_in_b = self.i.b
 472         m.submodules.denorm_out_a = self.o.a
 473         m.submodules.denorm_out_b = self.o.b
 474         # hmmm, don't like repeating identical code
 475         m.d.comb += self.o.a.eq(self.i.a)
 476         with m.If(self.i.a.exp_n127):
 477             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 478         with m.Else():
 479             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 480
 481         m.d.comb += self.o.b.eq(self.i.b)
 482         with m.If(self.i.b.exp_n127):
 483             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 484         with m.Else():
 485             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 486
 487         return m
 488
 489
 490 class FPAddDeNorm(FPState):
 491
 492     def __init__(self, width, id_wid):
 493         FPState.__init__(self, "denormalise")
 494         self.mod = FPAddDeNormMod(width)
 495         self.out_a = FPNumBase(width)
 496         self.out_b = FPNumBase(width)
 497
 498     def setup(self, m, i):
 499         """ links module to inputs and outputs
 500         """
 501         self.mod.setup(m, i)
 502
 503         m.d.sync += self.out_a.eq(self.mod.out_a)
 504         m.d.sync += self.out_b.eq(self.mod.out_b)
 505
 506     def action(self, m):
 507         # Denormalised Number checks
 508         m.next = "align"
 509
 510
 511 class FPAddAlignMultiMod(FPState):
 512
 513     def __init__(self, width):
 514         self.in_a = FPNumBase(width)
 515         self.in_b = FPNumBase(width)
 516         self.out_a = FPNumIn(None, width)
 517         self.out_b = FPNumIn(None, width)
 518         self.exp_eq = Signal(reset_less=True)
 519
 520     def elaborate(self, platform):
 521         # This one however (single-cycle) will do the shift
 522         # in one go.
 523
 524         m = Module()
 525
 526         m.submodules.align_in_a = self.in_a
 527         m.submodules.align_in_b = self.in_b
 528         m.submodules.align_out_a = self.out_a
 529         m.submodules.align_out_b = self.out_b
 530
 531         # NOTE: this does *not* do single-cycle multi-shifting,
 532         #       it *STAYS* in the align state until exponents match
 533
 534         # exponent of a greater than b: shift b down
 535         m.d.comb += self.exp_eq.eq(0)
 536         m.d.comb += self.out_a.eq(self.in_a)
 537         m.d.comb += self.out_b.eq(self.in_b)
 538         agtb = Signal(reset_less=True)
 539         altb = Signal(reset_less=True)
 540         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 541         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 542         with m.If(agtb):
 543             m.d.comb += self.out_b.shift_down(self.in_b)
 544         # exponent of b greater than a: shift a down
 545         with m.Elif(altb):
 546             m.d.comb += self.out_a.shift_down(self.in_a)
 547         # exponents equal: move to next stage.
 548         with m.Else():
 549             m.d.comb += self.exp_eq.eq(1)
 550         return m
 551
 552
 553 class FPAddAlignMulti(FPState):
 554
 555     def __init__(self, width, id_wid):
 556         FPState.__init__(self, "align")
 557         self.mod = FPAddAlignMultiMod(width)
 558         self.out_a = FPNumIn(None, width)
 559         self.out_b = FPNumIn(None, width)
 560         self.exp_eq = Signal(reset_less=True)
 561
 562     def setup(self, m, in_a, in_b):
 563         """ links module to inputs and outputs
 564         """
 565         m.submodules.align = self.mod
 566         m.d.comb += self.mod.in_a.eq(in_a)
 567         m.d.comb += self.mod.in_b.eq(in_b)
 568         #m.d.comb += self.out_a.eq(self.mod.out_a)
 569         #m.d.comb += self.out_b.eq(self.mod.out_b)
 570         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 571         m.d.sync += self.out_a.eq(self.mod.out_a)
 572         m.d.sync += self.out_b.eq(self.mod.out_b)
 573
 574     def action(self, m):
 575         with m.If(self.exp_eq):
 576             m.next = "add_0"
 577
 578
 579 class FPNumIn2Ops:
 580
 581     def __init__(self, width, id_wid):
 582         self.a = FPNumIn(None, width)
 583         self.b = FPNumIn(None, width)
 584         self.mid = Signal(id_wid, reset_less=True)
 585
 586     def eq(self, i):
 587         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 588
 589
 590 class FPAddAlignSingleMod:
 591
 592     def __init__(self, width, id_wid):
 593         self.width = width
 594         self.id_wid = id_wid
 595         self.i = self.ispec()
 596         self.o = self.ospec()
 597
 598     def ispec(self):
 599         return FPNumBase2Ops(self.width, self.id_wid)
 600
 601     def ospec(self):
 602         return FPNumIn2Ops(self.width, self.id_wid)
 603
 604     def setup(self, m, i):
 605         """ links module to inputs and outputs
 606         """
 607         m.submodules.align = self
 608         m.d.comb += self.i.eq(i)
 609
 610     def elaborate(self, platform):
 611         """ Aligns A against B or B against A, depending on which has the
 612             greater exponent.  This is done in a *single* cycle using
 613             variable-width bit-shift
 614
 615             the shifter used here is quite expensive in terms of gates.
 616             Mux A or B in (and out) into temporaries, as only one of them
 617             needs to be aligned against the other
 618         """
 619         m = Module()
 620
 621         m.submodules.align_in_a = self.i.a
 622         m.submodules.align_in_b = self.i.b
 623         m.submodules.align_out_a = self.o.a
 624         m.submodules.align_out_b = self.o.b
 625
 626         # temporary (muxed) input and output to be shifted
 627         t_inp = FPNumBase(self.width)
 628         t_out = FPNumIn(None, self.width)
 629         espec = (len(self.i.a.e), True)
 630         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 631         m.submodules.align_t_in = t_inp
 632         m.submodules.align_t_out = t_out
 633         m.submodules.multishift_r = msr
 634
 635         ediff = Signal(espec, reset_less=True)
 636         ediffr = Signal(espec, reset_less=True)
 637         tdiff = Signal(espec, reset_less=True)
 638         elz = Signal(reset_less=True)
 639         egz = Signal(reset_less=True)
 640
 641         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 642         m.d.comb += msr.inp.eq(t_inp.m)
 643         m.d.comb += msr.diff.eq(tdiff)
 644         m.d.comb += t_out.m.eq(msr.m)
 645         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 646         m.d.comb += t_out.s.eq(t_inp.s)
 647
 648         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 649         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 650         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 651         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 652
 653         # default: A-exp == B-exp, A and B untouched (fall through)
 654         m.d.comb += self.o.a.eq(self.i.a)
 655         m.d.comb += self.o.b.eq(self.i.b)
 656         # only one shifter (muxed)
 657         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 658         # exponent of a greater than b: shift b down
 659         with m.If(egz):
 660             m.d.comb += [t_inp.eq(self.i.b),
 661                          tdiff.eq(ediff),
 662                          self.o.b.eq(t_out),
 663                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 664                         ]
 665         # exponent of b greater than a: shift a down
 666         with m.Elif(elz):
 667             m.d.comb += [t_inp.eq(self.i.a),
 668                          tdiff.eq(ediffr),
 669                          self.o.a.eq(t_out),
 670                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 671                         ]
 672         return m
 673
 674
 675 class FPAddAlignSingle(FPState):
 676
 677     def __init__(self, width, id_wid):
 678         FPState.__init__(self, "align")
 679         self.mod = FPAddAlignSingleMod(width, id_wid)
 680         self.out_a = FPNumIn(None, width)
 681         self.out_b = FPNumIn(None, width)
 682
 683     def setup(self, m, i):
 684         """ links module to inputs and outputs
 685         """
 686         self.mod.setup(m, i)
 687
 688         # NOTE: could be done as comb
 689         m.d.sync += self.out_a.eq(self.mod.out_a)
 690         m.d.sync += self.out_b.eq(self.mod.out_b)
 691
 692     def action(self, m):
 693         m.next = "add_0"
 694
 695
 696 class FPAddAlignSingleAdd(FPState):
 697
 698     def __init__(self, width, id_wid):
 699         FPState.__init__(self, "align")
 700         self.width = width
 701         self.id_wid = id_wid
 702         self.a1o = self.ospec()
 703
 704     def ispec(self):
 705         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 706
 707     def ospec(self):
 708         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 709
 710     def setup(self, m, i):
 711         """ links module to inputs and outputs
 712         """
 713         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 714         mod.setup(m, i)
 715         o = mod.ospec()
 716         m.d.comb += o.eq(mod.o)
 717
 718         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 719         a0mod.setup(m, o)
 720         a0o = a0mod.ospec()
 721         m.d.comb += a0o.eq(a0mod.o)
 722
 723         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 724         a1mod.setup(m, a0o)
 725         self.a1modo = a1mod.o
 726
 727         m.d.sync += self.a1o.eq(self.a1modo)
 728
 729     def action(self, m):
 730         m.next = "normalise_1"
 731
 732
 733 class FPAddStage0Data:
 734
 735     def __init__(self, width, id_wid):
 736         self.z = FPNumBase(width, False)
 737         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 738         self.mid = Signal(id_wid, reset_less=True)
 739
 740     def eq(self, i):
 741         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 742
 743
 744 class FPAddStage0Mod:
 745
 746     def __init__(self, width, id_wid):
 747         self.width = width
 748         self.id_wid = id_wid
 749         self.i = self.ispec()
 750         self.o = self.ospec()
 751
 752     def ispec(self):
 753         return FPNumBase2Ops(self.width, self.id_wid)
 754
 755     def ospec(self):
 756         return FPAddStage0Data(self.width, self.id_wid)
 757
 758     def setup(self, m, i):
 759         """ links module to inputs and outputs
 760         """
 761         m.submodules.add0 = self
 762         m.d.comb += self.i.eq(i)
 763
 764     def elaborate(self, platform):
 765         m = Module()
 766         m.submodules.add0_in_a = self.i.a
 767         m.submodules.add0_in_b = self.i.b
 768         m.submodules.add0_out_z = self.o.z
 769
 770         m.d.comb += self.o.z.e.eq(self.i.a.e)
 771
 772         # store intermediate tests (and zero-extended mantissas)
 773         seq = Signal(reset_less=True)
 774         mge = Signal(reset_less=True)
 775         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 776         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 777         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 778                      mge.eq(self.i.a.m >= self.i.b.m),
 779                      am0.eq(Cat(self.i.a.m, 0)),
 780                      bm0.eq(Cat(self.i.b.m, 0))
 781                     ]
 782         # same-sign (both negative or both positive) add mantissas
 783         with m.If(seq):
 784             m.d.comb += [
 785                 self.o.tot.eq(am0 + bm0),
 786                 self.o.z.s.eq(self.i.a.s)
 787             ]
 788         # a mantissa greater than b, use a
 789         with m.Elif(mge):
 790             m.d.comb += [
 791                 self.o.tot.eq(am0 - bm0),
 792                 self.o.z.s.eq(self.i.a.s)
 793             ]
 794         # b mantissa greater than a, use b
 795         with m.Else():
 796             m.d.comb += [
 797                 self.o.tot.eq(bm0 - am0),
 798                 self.o.z.s.eq(self.i.b.s)
 799         ]
 800         return m
 801
 802
 803 class FPAddStage0(FPState):
 804     """ First stage of add.  covers same-sign (add) and subtract
 805         special-casing when mantissas are greater or equal, to
 806         give greatest accuracy.
 807     """
 808
 809     def __init__(self, width, id_wid):
 810         FPState.__init__(self, "add_0")
 811         self.mod = FPAddStage0Mod(width)
 812         self.o = self.mod.ospec()
 813
 814     def setup(self, m, i):
 815         """ links module to inputs and outputs
 816         """
 817         self.mod.setup(m, i)
 818
 819         # NOTE: these could be done as combinatorial (merge add0+add1)
 820         m.d.sync += self.o.eq(self.mod.o)
 821
 822     def action(self, m):
 823         m.next = "add_1"
 824
 825
 826 class FPAddStage1Data:
 827
 828     def __init__(self, width, id_wid):
 829         self.z = FPNumBase(width, False)
 830         self.of = Overflow()
 831         self.mid = Signal(id_wid, reset_less=True)
 832
 833     def eq(self, i):
 834         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 835
 836
 837
 838 class FPAddStage1Mod(FPState):
 839     """ Second stage of add: preparation for normalisation.
 840         detects when tot sum is too big (tot[27] is kinda a carry bit)
 841     """
 842
 843     def __init__(self, width, id_wid):
 844         self.width = width
 845         self.id_wid = id_wid
 846         self.i = self.ispec()
 847         self.o = self.ospec()
 848
 849     def ispec(self):
 850         return FPAddStage0Data(self.width, self.id_wid)
 851
 852     def ospec(self):
 853         return FPAddStage1Data(self.width, self.id_wid)
 854
 855     def setup(self, m, i):
 856         """ links module to inputs and outputs
 857         """
 858         m.submodules.add1 = self
 859         m.submodules.add1_out_overflow = self.o.of
 860
 861         m.d.comb += self.i.eq(i)
 862
 863     def elaborate(self, platform):
 864         m = Module()
 865         #m.submodules.norm1_in_overflow = self.in_of
 866         #m.submodules.norm1_out_overflow = self.out_of
 867         #m.submodules.norm1_in_z = self.in_z
 868         #m.submodules.norm1_out_z = self.out_z
 869         m.d.comb += self.o.z.eq(self.i.z)
 870         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 871         with m.If(self.i.tot[-1]):
 872             m.d.comb += [
 873                 self.o.z.m.eq(self.i.tot[4:]),
 874                 self.o.of.m0.eq(self.i.tot[4]),
 875                 self.o.of.guard.eq(self.i.tot[3]),
 876                 self.o.of.round_bit.eq(self.i.tot[2]),
 877                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 878                 self.o.z.e.eq(self.i.z.e + 1)
 879         ]
 880         # tot[-1] (MSB) zero case
 881         with m.Else():
 882             m.d.comb += [
 883                 self.o.z.m.eq(self.i.tot[3:]),
 884                 self.o.of.m0.eq(self.i.tot[3]),
 885                 self.o.of.guard.eq(self.i.tot[2]),
 886                 self.o.of.round_bit.eq(self.i.tot[1]),
 887                 self.o.of.sticky.eq(self.i.tot[0])
 888         ]
 889         return m
 890
 891
 892 class FPAddStage1(FPState):
 893
 894     def __init__(self, width, id_wid):
 895         FPState.__init__(self, "add_1")
 896         self.mod = FPAddStage1Mod(width)
 897         self.out_z = FPNumBase(width, False)
 898         self.out_of = Overflow()
 899         self.norm_stb = Signal()
 900
 901     def setup(self, m, i):
 902         """ links module to inputs and outputs
 903         """
 904         self.mod.setup(m, i)
 905
 906         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 907
 908         m.d.sync += self.out_of.eq(self.mod.out_of)
 909         m.d.sync += self.out_z.eq(self.mod.out_z)
 910         m.d.sync += self.norm_stb.eq(1)
 911
 912     def action(self, m):
 913         m.next = "normalise_1"
 914
 915
 916 class FPNormaliseModSingle:
 917
 918     def __init__(self, width):
 919         self.width = width
 920         self.in_z = self.ispec()
 921         self.out_z = self.ospec()
 922
 923     def ispec(self):
 924         return FPNumBase(self.width, False)
 925
 926     def ospec(self):
 927         return FPNumBase(self.width, False)
 928
 929     def setup(self, m, i):
 930         """ links module to inputs and outputs
 931         """
 932         m.submodules.normalise = self
 933         m.d.comb += self.i.eq(i)
 934
 935     def elaborate(self, platform):
 936         m = Module()
 937
 938         mwid = self.out_z.m_width+2
 939         pe = PriorityEncoder(mwid)
 940         m.submodules.norm_pe = pe
 941
 942         m.submodules.norm1_out_z = self.out_z
 943         m.submodules.norm1_in_z = self.in_z
 944
 945         in_z = FPNumBase(self.width, False)
 946         in_of = Overflow()
 947         m.submodules.norm1_insel_z = in_z
 948         m.submodules.norm1_insel_overflow = in_of
 949
 950         espec = (len(in_z.e), True)
 951         ediff_n126 = Signal(espec, reset_less=True)
 952         msr = MultiShiftRMerge(mwid, espec)
 953         m.submodules.multishift_r = msr
 954
 955         m.d.comb += in_z.eq(self.in_z)
 956         m.d.comb += in_of.eq(self.in_of)
 957         # initialise out from in (overridden below)
 958         m.d.comb += self.out_z.eq(in_z)
 959         m.d.comb += self.out_of.eq(in_of)
 960         # normalisation decrease condition
 961         decrease = Signal(reset_less=True)
 962         m.d.comb += decrease.eq(in_z.m_msbzero)
 963         # decrease exponent
 964         with m.If(decrease):
 965             # *sigh* not entirely obvious: count leading zeros (clz)
 966             # with a PriorityEncoder: to find from the MSB
 967             # we reverse the order of the bits.
 968             temp_m = Signal(mwid, reset_less=True)
 969             temp_s = Signal(mwid+1, reset_less=True)
 970             clz = Signal((len(in_z.e), True), reset_less=True)
 971             m.d.comb += [
 972                 # cat round and guard bits back into the mantissa
 973                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 974                 pe.i.eq(temp_m[::-1]),          # inverted
 975                 clz.eq(pe.o),                   # count zeros from MSB down
 976                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 977                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 978                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 979             ]
 980
 981         return m
 982
 983 class FPNorm1Data:
 984
 985     def __init__(self, width, id_wid):
 986         self.roundz = Signal(reset_less=True)
 987         self.z = FPNumBase(width, False)
 988         self.mid = Signal(id_wid, reset_less=True)
 989
 990     def eq(self, i):
 991         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
 992
 993
 994 class FPNorm1ModSingle:
 995
 996     def __init__(self, width, id_wid):
 997         self.width = width
 998         self.id_wid = id_wid
 999         self.i = self.ispec()
1000         self.o = self.ospec()
1001
1002     def ispec(self):
1003         return FPAddStage1Data(self.width, self.id_wid)
1004
1005     def ospec(self):
1006         return FPNorm1Data(self.width, self.id_wid)
1007
1008     def setup(self, m, i):
1009         """ links module to inputs and outputs
1010         """
1011         m.submodules.normalise_1 = self
1012         m.d.comb += self.i.eq(i)
1013
1014     def elaborate(self, platform):
1015         m = Module()
1016
1017         mwid = self.o.z.m_width+2
1018         pe = PriorityEncoder(mwid)
1019         m.submodules.norm_pe = pe
1020
1021         of = Overflow()
1022         m.d.comb += self.o.roundz.eq(of.roundz)
1023
1024         m.submodules.norm1_out_z = self.o.z
1025         m.submodules.norm1_out_overflow = of
1026         m.submodules.norm1_in_z = self.i.z
1027         m.submodules.norm1_in_overflow = self.i.of
1028
1029         i = self.ispec()
1030         m.submodules.norm1_insel_z = i.z
1031         m.submodules.norm1_insel_overflow = i.of
1032
1033         espec = (len(i.z.e), True)
1034         ediff_n126 = Signal(espec, reset_less=True)
1035         msr = MultiShiftRMerge(mwid, espec)
1036         m.submodules.multishift_r = msr
1037
1038         m.d.comb += i.eq(self.i)
1039         # initialise out from in (overridden below)
1040         m.d.comb += self.o.z.eq(i.z)
1041         m.d.comb += self.o.mid.eq(self.i.mid)
1042         m.d.comb += of.eq(i.of)
1043         # normalisation increase/decrease conditions
1044         decrease = Signal(reset_less=True)
1045         increase = Signal(reset_less=True)
1046         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1047         m.d.comb += increase.eq(i.z.exp_lt_n126)
1048         # decrease exponent
1049         with m.If(decrease):
1050             # *sigh* not entirely obvious: count leading zeros (clz)
1051             # with a PriorityEncoder: to find from the MSB
1052             # we reverse the order of the bits.
1053             temp_m = Signal(mwid, reset_less=True)
1054             temp_s = Signal(mwid+1, reset_less=True)
1055             clz = Signal((len(i.z.e), True), reset_less=True)
1056             # make sure that the amount to decrease by does NOT
1057             # go below the minimum non-INF/NaN exponent
1058             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1059                          i.z.exp_sub_n126)
1060             m.d.comb += [
1061                 # cat round and guard bits back into the mantissa
1062                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1063                 pe.i.eq(temp_m[::-1]),          # inverted
1064                 clz.eq(limclz),                 # count zeros from MSB down
1065                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1066                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1067                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1068                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1069                 # overflow in bits 0..1: got shifted too (leave sticky)
1070                 of.guard.eq(temp_s[1]),       # guard
1071                 of.round_bit.eq(temp_s[0]),   # round
1072             ]
1073         # increase exponent
1074         with m.Elif(increase):
1075             temp_m = Signal(mwid+1, reset_less=True)
1076             m.d.comb += [
1077                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1078                               i.z.m)),
1079                 ediff_n126.eq(i.z.N126 - i.z.e),
1080                 # connect multi-shifter to inp/out mantissa (and ediff)
1081                 msr.inp.eq(temp_m),
1082                 msr.diff.eq(ediff_n126),
1083                 self.o.z.m.eq(msr.m[3:]),
1084                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1085                 # overflow in bits 0..1: got shifted too (leave sticky)
1086                 of.guard.eq(temp_s[2]),     # guard
1087                 of.round_bit.eq(temp_s[1]), # round
1088                 of.sticky.eq(temp_s[0]),    # sticky
1089                 self.o.z.e.eq(i.z.e + ediff_n126),
1090             ]
1091
1092         return m
1093
1094
1095 class FPNorm1ModMulti:
1096
1097     def __init__(self, width, single_cycle=True):
1098         self.width = width
1099         self.in_select = Signal(reset_less=True)
1100         self.in_z = FPNumBase(width, False)
1101         self.in_of = Overflow()
1102         self.temp_z = FPNumBase(width, False)
1103         self.temp_of = Overflow()
1104         self.out_z = FPNumBase(width, False)
1105         self.out_of = Overflow()
1106
1107     def elaborate(self, platform):
1108         m = Module()
1109
1110         m.submodules.norm1_out_z = self.out_z
1111         m.submodules.norm1_out_overflow = self.out_of
1112         m.submodules.norm1_temp_z = self.temp_z
1113         m.submodules.norm1_temp_of = self.temp_of
1114         m.submodules.norm1_in_z = self.in_z
1115         m.submodules.norm1_in_overflow = self.in_of
1116
1117         in_z = FPNumBase(self.width, False)
1118         in_of = Overflow()
1119         m.submodules.norm1_insel_z = in_z
1120         m.submodules.norm1_insel_overflow = in_of
1121
1122         # select which of temp or in z/of to use
1123         with m.If(self.in_select):
1124             m.d.comb += in_z.eq(self.in_z)
1125             m.d.comb += in_of.eq(self.in_of)
1126         with m.Else():
1127             m.d.comb += in_z.eq(self.temp_z)
1128             m.d.comb += in_of.eq(self.temp_of)
1129         # initialise out from in (overridden below)
1130         m.d.comb += self.out_z.eq(in_z)
1131         m.d.comb += self.out_of.eq(in_of)
1132         # normalisation increase/decrease conditions
1133         decrease = Signal(reset_less=True)
1134         increase = Signal(reset_less=True)
1135         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1136         m.d.comb += increase.eq(in_z.exp_lt_n126)
1137         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1138         # decrease exponent
1139         with m.If(decrease):
1140             m.d.comb += [
1141                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1142                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1143                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1144                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1145                 self.out_of.round_bit.eq(0),        # reset round bit
1146                 self.out_of.m0.eq(in_of.guard),
1147             ]
1148         # increase exponent
1149         with m.Elif(increase):
1150             m.d.comb += [
1151                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1152                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1153                 self.out_of.guard.eq(in_z.m[0]),
1154                 self.out_of.m0.eq(in_z.m[1]),
1155                 self.out_of.round_bit.eq(in_of.guard),
1156                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1157             ]
1158
1159         return m
1160
1161
1162 class FPNorm1Single(FPState):
1163
1164     def __init__(self, width, id_wid, single_cycle=True):
1165         FPState.__init__(self, "normalise_1")
1166         self.mod = FPNorm1ModSingle(width)
1167         self.out_z = FPNumBase(width, False)
1168         self.out_roundz = Signal(reset_less=True)
1169
1170     def setup(self, m, i):
1171         """ links module to inputs and outputs
1172         """
1173         self.mod.setup(m, i, self.out_z)
1174
1175         m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1176
1177     def action(self, m):
1178         m.next = "round"
1179
1180
1181 class FPNorm1Multi(FPState):
1182
1183     def __init__(self, width, id_wid):
1184         FPState.__init__(self, "normalise_1")
1185         self.mod = FPNorm1ModMulti(width)
1186         self.stb = Signal(reset_less=True)
1187         self.ack = Signal(reset=0, reset_less=True)
1188         self.out_norm = Signal(reset_less=True)
1189         self.in_accept = Signal(reset_less=True)
1190         self.temp_z = FPNumBase(width)
1191         self.temp_of = Overflow()
1192         self.out_z = FPNumBase(width)
1193         self.out_roundz = Signal(reset_less=True)
1194
1195     def setup(self, m, in_z, in_of, norm_stb):
1196         """ links module to inputs and outputs
1197         """
1198         self.mod.setup(m, in_z, in_of, norm_stb,
1199                        self.in_accept, self.temp_z, self.temp_of,
1200                        self.out_z, self.out_norm)
1201
1202         m.d.comb += self.stb.eq(norm_stb)
1203         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1204
1205     def action(self, m):
1206         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1207         m.d.sync += self.temp_of.eq(self.mod.out_of)
1208         m.d.sync += self.temp_z.eq(self.out_z)
1209         with m.If(self.out_norm):
1210             with m.If(self.in_accept):
1211                 m.d.sync += [
1212                     self.ack.eq(1),
1213                 ]
1214             with m.Else():
1215                 m.d.sync += self.ack.eq(0)
1216         with m.Else():
1217             # normalisation not required (or done).
1218             m.next = "round"
1219             m.d.sync += self.ack.eq(1)
1220             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1221
1222
1223 class FPNormToPack(FPState):
1224
1225     def __init__(self, width, id_wid):
1226         FPState.__init__(self, "normalise_1")
1227         self.id_wid = id_wid
1228         self.width = width
1229
1230     def ispec(self):
1231         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1232
1233     def ospec(self):
1234         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1235
1236     def setup(self, m, i):
1237         """ links module to inputs and outputs
1238         """
1239
1240         # Normalisation (chained to input in_z+in_of)
1241         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1242         nmod.setup(m, i)
1243         n_out = nmod.ospec()
1244         m.d.comb += n_out.eq(nmod.o)
1245
1246         # Rounding (chained to normalisation)
1247         rmod = FPRoundMod(self.width, self.id_wid)
1248         rmod.setup(m, n_out)
1249         r_out_z = rmod.ospec()
1250         m.d.comb += r_out_z.eq(rmod.out_z)
1251
1252         # Corrections (chained to rounding)
1253         cmod = FPCorrectionsMod(self.width, self.id_wid)
1254         cmod.setup(m, r_out_z)
1255         c_out_z = cmod.ospec()
1256         m.d.comb += c_out_z.eq(cmod.out_z)
1257
1258         # Pack (chained to corrections)
1259         self.pmod = FPPackMod(self.width, self.id_wid)
1260         self.pmod.setup(m, c_out_z)
1261         self.out_z = self.pmod.ospec()
1262
1263         m.d.sync += self.out_z.mid.eq(self.pmod.o.mid)
1264         m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1265
1266     def action(self, m):
1267         m.next = "pack_put_z"
1268
1269
1270 class FPRoundData:
1271
1272     def __init__(self, width, id_wid):
1273         self.z = FPNumBase(width, False)
1274         self.mid = Signal(id_wid, reset_less=True)
1275
1276     def eq(self, i):
1277         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1278
1279
1280 class FPRoundMod:
1281
1282     def __init__(self, width, id_wid):
1283         self.width = width
1284         self.id_wid = id_wid
1285         self.i = self.ispec()
1286         self.out_z = self.ospec()
1287
1288     def ispec(self):
1289         return FPNorm1Data(self.width, self.id_wid)
1290
1291     def ospec(self):
1292         return FPRoundData(self.width, self.id_wid)
1293
1294     def setup(self, m, i):
1295         m.submodules.roundz = self
1296         m.d.comb += self.i.eq(i)
1297
1298     def elaborate(self, platform):
1299         m = Module()
1300         m.d.comb += self.out_z.eq(self.i)
1301         with m.If(self.i.roundz):
1302             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1303             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1304                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1305         return m
1306
1307
1308 class FPRound(FPState):
1309
1310     def __init__(self, width, id_wid):
1311         FPState.__init__(self, "round")
1312         self.mod = FPRoundMod(width)
1313         self.out_z = self.ospec()
1314
1315     def ispec(self):
1316         return self.mod.ispec()
1317
1318     def ospec(self):
1319         return self.mod.ospec()
1320
1321     def setup(self, m, i):
1322         """ links module to inputs and outputs
1323         """
1324         self.mod.setup(m, i)
1325
1326         self.idsync(m)
1327         m.d.sync += self.out_z.eq(self.mod.out_z)
1328         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1329
1330     def action(self, m):
1331         m.next = "corrections"
1332
1333
1334 class FPCorrectionsMod:
1335
1336     def __init__(self, width, id_wid):
1337         self.width = width
1338         self.id_wid = id_wid
1339         self.i = self.ispec()
1340         self.out_z = self.ospec()
1341
1342     def ispec(self):
1343         return FPRoundData(self.width, self.id_wid)
1344
1345     def ospec(self):
1346         return FPRoundData(self.width, self.id_wid)
1347
1348     def setup(self, m, i):
1349         """ links module to inputs and outputs
1350         """
1351         m.submodules.corrections = self
1352         m.d.comb += self.i.eq(i)
1353
1354     def elaborate(self, platform):
1355         m = Module()
1356         m.submodules.corr_in_z = self.i.z
1357         m.submodules.corr_out_z = self.out_z.z
1358         m.d.comb += self.out_z.eq(self.i)
1359         with m.If(self.i.z.is_denormalised):
1360             m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1361         return m
1362
1363
1364 class FPCorrections(FPState):
1365
1366     def __init__(self, width, id_wid):
1367         FPState.__init__(self, "corrections")
1368         self.mod = FPCorrectionsMod(width)
1369         self.out_z = self.ospec()
1370
1371     def ispec(self):
1372         return self.mod.ispec()
1373
1374     def ospec(self):
1375         return self.mod.ospec()
1376
1377     def setup(self, m, in_z):
1378         """ links module to inputs and outputs
1379         """
1380         self.mod.setup(m, in_z)
1381
1382         m.d.sync += self.out_z.eq(self.mod.out_z)
1383         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1384
1385     def action(self, m):
1386         m.next = "pack"
1387
1388
1389 class FPPackData:
1390
1391     def __init__(self, width, id_wid):
1392         self.z = FPNumOut(width, False)
1393         self.mid = Signal(id_wid, reset_less=True)
1394
1395     def eq(self, i):
1396         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1397
1398
1399 class FPPackMod:
1400
1401     def __init__(self, width, id_wid):
1402         self.width = width
1403         self.id_wid = id_wid
1404         self.i = self.ispec()
1405         self.o = self.ospec()
1406
1407     def ispec(self):
1408         return FPRoundData(self.width, self.id_wid)
1409
1410     def ospec(self):
1411         return FPPackData(self.width, self.id_wid)
1412
1413     def setup(self, m, in_z):
1414         """ links module to inputs and outputs
1415         """
1416         m.submodules.pack = self
1417         m.d.comb += self.i.eq(in_z)
1418
1419     def elaborate(self, platform):
1420         m = Module()
1421         m.submodules.pack_in_z = self.i.z
1422         m.d.comb += self.o.mid.eq(self.i.mid)
1423         with m.If(self.i.z.is_overflowed):
1424             m.d.comb += self.o.z.inf(self.i.z.s)
1425         with m.Else():
1426             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1427         return m
1428
1429
1430 class FPPackData:
1431     def __init__(self, width, id_wid):
1432         self.z = FPNumOut(width, False)
1433         self.mid = Signal(id_wid, reset_less=True)
1434
1435     def eq(self, i):
1436         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1437
1438
1439 class FPPack(FPState):
1440
1441     def __init__(self, width, id_wid):
1442         FPState.__init__(self, "pack")
1443         self.mod = FPPackMod(width)
1444         self.out_z = self.ospec()
1445
1446     def ispec(self):
1447         return self.mod.ispec()
1448
1449     def ospec(self):
1450         return self.mod.ospec()
1451
1452     def setup(self, m, in_z):
1453         """ links module to inputs and outputs
1454         """
1455         self.mod.setup(m, in_z)
1456
1457         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1458         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1459
1460     def action(self, m):
1461         m.next = "pack_put_z"
1462
1463
1464 class FPPutZ(FPState):
1465
1466     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1467         FPState.__init__(self, state)
1468         if to_state is None:
1469             to_state = "get_ops"
1470         self.to_state = to_state
1471         self.in_z = in_z
1472         self.out_z = out_z
1473         self.in_mid = in_mid
1474         self.out_mid = out_mid
1475
1476     def action(self, m):
1477         if self.in_mid is not None:
1478             m.d.sync += self.out_mid.eq(self.in_mid)
1479         m.d.sync += [
1480           self.out_z.z.v.eq(self.in_z.v)
1481         ]
1482         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1483             m.d.sync += self.out_z.z.stb.eq(0)
1484             m.next = self.to_state
1485         with m.Else():
1486             m.d.sync += self.out_z.z.stb.eq(1)
1487
1488
1489 class FPPutZIdx(FPState):
1490
1491     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1492         FPState.__init__(self, state)
1493         if to_state is None:
1494             to_state = "get_ops"
1495         self.to_state = to_state
1496         self.in_z = in_z
1497         self.out_zs = out_zs
1498         self.in_mid = in_mid
1499
1500     def action(self, m):
1501         outz_stb = Signal(reset_less=True)
1502         outz_ack = Signal(reset_less=True)
1503         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1504                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1505                     ]
1506         m.d.sync += [
1507           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1508         ]
1509         with m.If(outz_stb & outz_ack):
1510             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1511             m.next = self.to_state
1512         with m.Else():
1513             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1514
1515 class FPADDBaseData:
1516
1517     def __init__(self, width, id_wid):
1518         self.width = width
1519         self.id_wid = id_wid
1520         self.a  = Signal(width)
1521         self.b  = Signal(width)
1522         self.mid = Signal(id_wid, reset_less=True)
1523
1524     def eq(self, i):
1525         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1526
1527
1528 class FPOpData:
1529     def __init__(self, width, id_wid):
1530         self.z = FPOp(width)
1531         self.mid = Signal(id_wid, reset_less=True)
1532
1533     def eq(self, i):
1534         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1535
1536
1537 class FPADDBaseMod:
1538
1539     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1540         """ IEEE754 FP Add
1541
1542             * width: bit-width of IEEE754.  supported: 16, 32, 64
1543             * id_wid: an identifier that is sync-connected to the input
1544             * single_cycle: True indicates each stage to complete in 1 clock
1545             * compact: True indicates a reduced number of stages
1546         """
1547         self.width = width
1548         self.id_wid = id_wid
1549         self.single_cycle = single_cycle
1550         self.compact = compact
1551
1552         self.in_t = Trigger()
1553         self.i = self.ispec()
1554         self.o = self.ospec()
1555
1556         self.states = []
1557
1558     def ispec(self):
1559         return FPADDBaseData(self.width, self.id_wid)
1560
1561     def ospec(self):
1562         return FPOpData(self.width, self.id_wid)
1563
1564     def add_state(self, state):
1565         self.states.append(state)
1566         return state
1567
1568     def get_fragment(self, platform=None):
1569         """ creates the HDL code-fragment for FPAdd
1570         """
1571         m = Module()
1572         m.submodules.out_z = self.o.z
1573         m.submodules.in_t = self.in_t
1574         if self.compact:
1575             self.get_compact_fragment(m, platform)
1576         else:
1577             self.get_longer_fragment(m, platform)
1578
1579         with m.FSM() as fsm:
1580
1581             for state in self.states:
1582                 with m.State(state.state_from):
1583                     state.action(m)
1584
1585         return m
1586
1587     def get_longer_fragment(self, m, platform=None):
1588
1589         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1590                                       self.width))
1591         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1592         a = get.out_op1
1593         b = get.out_op2
1594
1595         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1596         sc.setup(m, a, b, self.in_mid)
1597
1598         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1599         dn.setup(m, a, b, sc.in_mid)
1600
1601         if self.single_cycle:
1602             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1603             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1604         else:
1605             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1606             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1607
1608         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1609         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1610
1611         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1612         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1613
1614         if self.single_cycle:
1615             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1616             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1617         else:
1618             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1619             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1620
1621         rn = self.add_state(FPRound(self.width, self.id_wid))
1622         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1623
1624         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1625         cor.setup(m, rn.out_z, rn.in_mid)
1626
1627         pa = self.add_state(FPPack(self.width, self.id_wid))
1628         pa.setup(m, cor.out_z, rn.in_mid)
1629
1630         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1631                                     pa.in_mid, self.out_mid))
1632
1633         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1634                                     pa.in_mid, self.out_mid))
1635
1636     def get_compact_fragment(self, m, platform=None):
1637
1638         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1639                                       self.width, self.id_wid))
1640         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1641
1642         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1643         sc.setup(m, get.o)
1644
1645         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1646         alm.setup(m, sc.o)
1647
1648         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1649         n1.setup(m, alm.a1o)
1650
1651         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1652                                     n1.out_z.mid, self.o.mid))
1653
1654         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1655                                     sc.o.mid, self.o.mid))
1656
1657
1658 class FPADDBase(FPState):
1659
1660     def __init__(self, width, id_wid=None, single_cycle=False):
1661         """ IEEE754 FP Add
1662
1663             * width: bit-width of IEEE754.  supported: 16, 32, 64
1664             * id_wid: an identifier that is sync-connected to the input
1665             * single_cycle: True indicates each stage to complete in 1 clock
1666         """
1667         FPState.__init__(self, "fpadd")
1668         self.width = width
1669         self.single_cycle = single_cycle
1670         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1671         self.o = self.ospec()
1672
1673         self.in_t = Trigger()
1674         self.i = self.ispec()
1675
1676         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1677         self.in_accept = Signal(reset_less=True)
1678         self.add_stb = Signal(reset_less=True)
1679         self.add_ack = Signal(reset=0, reset_less=True)
1680
1681     def ispec(self):
1682         return self.mod.ispec()
1683
1684     def ospec(self):
1685         return self.mod.ospec()
1686
1687     def setup(self, m, i, add_stb, in_mid):
1688         m.d.comb += [self.i.eq(i),
1689                      self.mod.i.eq(self.i),
1690                      self.z_done.eq(self.mod.o.z.trigger),
1691                      #self.add_stb.eq(add_stb),
1692                      self.mod.in_t.stb.eq(self.in_t.stb),
1693                      self.in_t.ack.eq(self.mod.in_t.ack),
1694                      self.o.mid.eq(self.mod.o.mid),
1695                      self.o.z.v.eq(self.mod.o.z.v),
1696                      self.o.z.stb.eq(self.mod.o.z.stb),
1697                      self.mod.o.z.ack.eq(self.o.z.ack),
1698                     ]
1699
1700         m.d.sync += self.add_stb.eq(add_stb)
1701         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1702         m.d.sync += self.o.z.ack.eq(0) # likewise
1703         #m.d.sync += self.in_t.stb.eq(0)
1704
1705         m.submodules.fpadd = self.mod
1706
1707     def action(self, m):
1708
1709         # in_accept is set on incoming strobe HIGH and ack LOW.
1710         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1711
1712         #with m.If(self.in_t.ack):
1713         #    m.d.sync += self.in_t.stb.eq(0)
1714         with m.If(~self.z_done):
1715             # not done: test for accepting an incoming operand pair
1716             with m.If(self.in_accept):
1717                 m.d.sync += [
1718                     self.add_ack.eq(1), # acknowledge receipt...
1719                     self.in_t.stb.eq(1), # initiate add
1720                 ]
1721             with m.Else():
1722                 m.d.sync += [self.add_ack.eq(0),
1723                              self.in_t.stb.eq(0),
1724                              self.o.z.ack.eq(1),
1725                             ]
1726         with m.Else():
1727             # done: acknowledge, and write out id and value
1728             m.d.sync += [self.add_ack.eq(1),
1729                          self.in_t.stb.eq(0)
1730                         ]
1731             m.next = "put_z"
1732
1733             return
1734
1735             if self.in_mid is not None:
1736                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1737
1738             m.d.sync += [
1739               self.out_z.v.eq(self.mod.out_z.v)
1740             ]
1741             # move to output state on detecting z ack
1742             with m.If(self.out_z.trigger):
1743                 m.d.sync += self.out_z.stb.eq(0)
1744                 m.next = "put_z"
1745             with m.Else():
1746                 m.d.sync += self.out_z.stb.eq(1)
1747
1748
1749 class ResArray:
1750     def __init__(self, width, id_wid):
1751         self.width = width
1752         self.id_wid = id_wid
1753         res = []
1754         for i in range(rs_sz):
1755             out_z = FPOp(width)
1756             out_z.name = "out_z_%d" % i
1757             res.append(out_z)
1758         self.res = Array(res)
1759         self.in_z = FPOp(width)
1760         self.in_mid = Signal(self.id_wid, reset_less=True)
1761
1762     def setup(self, m, in_z, in_mid):
1763         m.d.comb += [self.in_z.eq(in_z),
1764                      self.in_mid.eq(in_mid)]
1765
1766     def get_fragment(self, platform=None):
1767         """ creates the HDL code-fragment for FPAdd
1768         """
1769         m = Module()
1770         m.submodules.res_in_z = self.in_z
1771         m.submodules += self.res
1772
1773         return m
1774
1775     def ports(self):
1776         res = []
1777         for z in self.res:
1778             res += z.ports()
1779         return res
1780
1781
1782 class FPADD(FPID):
1783     """ FPADD: stages as follows:
1784
1785         FPGetOp (a)
1786            |
1787         FPGetOp (b)
1788            |
1789         FPAddBase---> FPAddBaseMod
1790            |            |
1791         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1792
1793         FPAddBase is tricky: it is both a stage and *has* stages.
1794         Connection to FPAddBaseMod therefore requires an in stb/ack
1795         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1796         needs to be the thing that raises the incoming stb.
1797     """
1798
1799     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1800         """ IEEE754 FP Add
1801
1802             * width: bit-width of IEEE754.  supported: 16, 32, 64
1803             * id_wid: an identifier that is sync-connected to the input
1804             * single_cycle: True indicates each stage to complete in 1 clock
1805         """
1806         self.width = width
1807         self.id_wid = id_wid
1808         self.single_cycle = single_cycle
1809
1810         #self.out_z = FPOp(width)
1811         self.ids = FPID(id_wid)
1812
1813         rs = []
1814         for i in range(rs_sz):
1815             in_a  = FPOp(width)
1816             in_b  = FPOp(width)
1817             in_a.name = "in_a_%d" % i
1818             in_b.name = "in_b_%d" % i
1819             rs.append((in_a, in_b))
1820         self.rs = Array(rs)
1821
1822         res = []
1823         for i in range(rs_sz):
1824             out_z = FPOp(width)
1825             out_z.name = "out_z_%d" % i
1826             res.append(out_z)
1827         self.res = Array(res)
1828
1829         self.states = []
1830
1831     def add_state(self, state):
1832         self.states.append(state)
1833         return state
1834
1835     def get_fragment(self, platform=None):
1836         """ creates the HDL code-fragment for FPAdd
1837         """
1838         m = Module()
1839         m.submodules += self.rs
1840
1841         in_a = self.rs[0][0]
1842         in_b = self.rs[0][1]
1843
1844         geta = self.add_state(FPGetOp("get_a", "get_b",
1845                                       in_a, self.width))
1846         geta.setup(m, in_a)
1847         a = geta.out_op
1848
1849         getb = self.add_state(FPGetOp("get_b", "fpadd",
1850                                       in_b, self.width))
1851         getb.setup(m, in_b)
1852         b = getb.out_op
1853
1854         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1855         ab = self.add_state(ab)
1856         abd = ab.ispec() # create an input spec object for FPADDBase
1857         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1858         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1859         o = ab.o
1860
1861         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1862                                     o.mid, "get_a"))
1863
1864         with m.FSM() as fsm:
1865
1866             for state in self.states:
1867                 with m.State(state.state_from):
1868                     state.action(m)
1869
1870         return m
1871
1872
1873 if __name__ == "__main__":
1874     if True:
1875         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1876         main(alu, ports=alu.rs[0][0].ports() + \
1877                         alu.rs[0][1].ports() + \
1878                         alu.res[0].ports() + \
1879                         [alu.ids.in_mid, alu.ids.out_mid])
1880     else:
1881         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1882         main(alu, ports=[alu.in_a, alu.in_b] + \
1883                         alu.in_t.ports() + \
1884                         alu.out_z.ports() + \
1885                         [alu.in_mid, alu.out_mid])
1886
1887
1888     # works... but don't use, just do "python fname.py convert -t v"
1889     #print (verilog.convert(alu, ports=[
1890     #                        ports=alu.in_a.ports() + \
1891     #                              alu.in_b.ports() + \
1892     #                              alu.out_z.ports())