src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPSCData:
 264
 265     def __init__(self, width, id_wid):
 266         self.a = FPNumBase(width, True)
 267         self.b = FPNumBase(width, True)
 268         self.z = FPNumOut(width, False)
 269         self.out_do_z = Signal(reset_less=True)
 270         self.mid = Signal(id_wid, reset_less=True)
 271
 272     def eq(self, i):
 273         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z),
 274                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 275
 276
 277 class FPAddSpecialCasesMod:
 278     """ special cases: NaNs, infs, zeros, denormalised
 279         NOTE: some of these are unique to add.  see "Special Operations"
 280         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 281     """
 282
 283     def __init__(self, width, id_wid):
 284         self.width = width
 285         self.id_wid = id_wid
 286         self.i = self.ispec()
 287         self.o = self.ospec()
 288
 289     def ispec(self):
 290         return FPNumBase2Ops(self.width, self.id_wid)
 291
 292     def ospec(self):
 293         return FPSCData(self.width, self.id_wid)
 294
 295     def setup(self, m, i):
 296         """ links module to inputs and outputs
 297         """
 298         m.submodules.specialcases = self
 299         m.d.comb += self.i.eq(i)
 300
 301     def elaborate(self, platform):
 302         m = Module()
 303
 304         m.submodules.sc_in_a = self.i.a
 305         m.submodules.sc_in_b = self.i.b
 306         m.submodules.sc_out_z = self.o.z
 307
 308         s_nomatch = Signal()
 309         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 310
 311         m_match = Signal()
 312         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 313
 314         # if a is NaN or b is NaN return NaN
 315         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 316             m.d.comb += self.o.out_do_z.eq(1)
 317             m.d.comb += self.o.z.nan(0)
 318
 319         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 320         # under review
 321
 322         ## if a is zero and b is NaN return -b
 323         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 324         #    m.d.comb += self.o.out_do_z.eq(1)
 325         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 326
 327         ## if b is zero and a is NaN return -a
 328         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 329         #    m.d.comb += self.o.out_do_z.eq(1)
 330         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 331
 332         ## if a is -zero and b is NaN return -b
 333         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 334         #    m.d.comb += self.o.out_do_z.eq(1)
 335         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 336
 337         ## if b is -zero and a is NaN return -a
 338         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 339         #    m.d.comb += self.o.out_do_z.eq(1)
 340         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 341
 342         # if a is inf return inf (or NaN)
 343         with m.Elif(self.i.a.is_inf):
 344             m.d.comb += self.o.out_do_z.eq(1)
 345             m.d.comb += self.o.z.inf(self.i.a.s)
 346             # if a is inf and signs don't match return NaN
 347             with m.If(self.i.b.exp_128 & s_nomatch):
 348                 m.d.comb += self.o.z.nan(0)
 349
 350         # if b is inf return inf
 351         with m.Elif(self.i.b.is_inf):
 352             m.d.comb += self.o.out_do_z.eq(1)
 353             m.d.comb += self.o.z.inf(self.i.b.s)
 354
 355         # if a is zero and b zero return signed-a/b
 356         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 357             m.d.comb += self.o.out_do_z.eq(1)
 358             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 359                                           self.i.b.e,
 360                                           self.i.b.m[3:-1])
 361
 362         # if a is zero return b
 363         with m.Elif(self.i.a.is_zero):
 364             m.d.comb += self.o.out_do_z.eq(1)
 365             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 366                                       self.i.b.m[3:-1])
 367
 368         # if b is zero return a
 369         with m.Elif(self.i.b.is_zero):
 370             m.d.comb += self.o.out_do_z.eq(1)
 371             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 372                                       self.i.a.m[3:-1])
 373
 374         # if a equal to -b return zero (+ve zero)
 375         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 376             m.d.comb += self.o.out_do_z.eq(1)
 377             m.d.comb += self.o.z.zero(0)
 378
 379         # Denormalised Number checks next, so pass a/b data through
 380         with m.Else():
 381             m.d.comb += self.o.out_do_z.eq(0)
 382             m.d.comb += self.o.a.eq(self.i.a)
 383             m.d.comb += self.o.b.eq(self.i.b)
 384
 385         m.d.comb += self.o.mid.eq(self.i.mid)
 386
 387         return m
 388
 389
 390 class FPID:
 391     def __init__(self, id_wid):
 392         self.id_wid = id_wid
 393         if self.id_wid:
 394             self.in_mid = Signal(id_wid, reset_less=True)
 395             self.out_mid = Signal(id_wid, reset_less=True)
 396         else:
 397             self.in_mid = None
 398             self.out_mid = None
 399
 400     def idsync(self, m):
 401         if self.id_wid is not None:
 402             m.d.sync += self.out_mid.eq(self.in_mid)
 403
 404
 405 class FPAddSpecialCases(FPState):
 406     """ special cases: NaNs, infs, zeros, denormalised
 407         NOTE: some of these are unique to add.  see "Special Operations"
 408         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 409     """
 410
 411     def __init__(self, width, id_wid):
 412         FPState.__init__(self, "special_cases")
 413         self.mod = FPAddSpecialCasesMod(width)
 414         self.out_z = self.mod.ospec()
 415         self.out_do_z = Signal(reset_less=True)
 416
 417     def setup(self, m, i):
 418         """ links module to inputs and outputs
 419         """
 420         self.mod.setup(m, i, self.out_do_z)
 421         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 422         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 423
 424     def action(self, m):
 425         self.idsync(m)
 426         with m.If(self.out_do_z):
 427             m.next = "put_z"
 428         with m.Else():
 429             m.next = "denormalise"
 430
 431
 432 class FPAddSpecialCasesDeNorm(FPState):
 433     """ special cases: NaNs, infs, zeros, denormalised
 434         NOTE: some of these are unique to add.  see "Special Operations"
 435         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 436     """
 437
 438     def __init__(self, width, id_wid):
 439         FPState.__init__(self, "special_cases")
 440         self.smod = FPAddSpecialCasesMod(width, id_wid)
 441         self.out_z = self.smod.ospec()
 442         self.out_do_z = Signal(reset_less=True)
 443
 444         self.dmod = FPAddDeNormMod(width, id_wid)
 445         self.o = self.dmod.ospec()
 446
 447     def setup(self, m, i):
 448         """ links module to inputs and outputs
 449         """
 450         self.smod.setup(m, i)
 451         self.dmod.setup(m, self.smod.o)
 452         m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
 453
 454         # out_do_z=True
 455         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 456         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 457         # out_do_z=False
 458         m.d.sync += self.o.eq(self.dmod.o)
 459
 460     def action(self, m):
 461         with m.If(self.out_do_z):
 462             m.next = "put_z"
 463         with m.Else():
 464             m.next = "align"
 465
 466
 467 class FPAddDeNormMod(FPState):
 468
 469     def __init__(self, width, id_wid):
 470         self.width = width
 471         self.id_wid = id_wid
 472         self.i = self.ispec()
 473         self.o = self.ospec()
 474
 475     def ispec(self):
 476         return FPSCData(self.width, self.id_wid)
 477
 478     def ospec(self):
 479         return FPSCData(self.width, self.id_wid)
 480
 481     def setup(self, m, i):
 482         """ links module to inputs and outputs
 483         """
 484         m.submodules.denormalise = self
 485         m.d.comb += self.i.eq(i)
 486
 487     def elaborate(self, platform):
 488         m = Module()
 489         m.submodules.denorm_in_a = self.i.a
 490         m.submodules.denorm_in_b = self.i.b
 491         m.submodules.denorm_out_a = self.o.a
 492         m.submodules.denorm_out_b = self.o.b
 493
 494         with m.If(~self.i.out_do_z):
 495             # XXX hmmm, don't like repeating identical code
 496             m.d.comb += self.o.a.eq(self.i.a)
 497             with m.If(self.i.a.exp_n127):
 498                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 499             with m.Else():
 500                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 501
 502             m.d.comb += self.o.b.eq(self.i.b)
 503             with m.If(self.i.b.exp_n127):
 504                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 505             with m.Else():
 506                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 507
 508         m.d.comb += self.o.mid.eq(self.i.mid)
 509         m.d.comb += self.o.z.eq(self.i.z)
 510         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 511
 512         return m
 513
 514
 515 class FPAddDeNorm(FPState):
 516
 517     def __init__(self, width, id_wid):
 518         FPState.__init__(self, "denormalise")
 519         self.mod = FPAddDeNormMod(width)
 520         self.out_a = FPNumBase(width)
 521         self.out_b = FPNumBase(width)
 522
 523     def setup(self, m, i):
 524         """ links module to inputs and outputs
 525         """
 526         self.mod.setup(m, i)
 527
 528         m.d.sync += self.out_a.eq(self.mod.out_a)
 529         m.d.sync += self.out_b.eq(self.mod.out_b)
 530
 531     def action(self, m):
 532         # Denormalised Number checks
 533         m.next = "align"
 534
 535
 536 class FPAddAlignMultiMod(FPState):
 537
 538     def __init__(self, width):
 539         self.in_a = FPNumBase(width)
 540         self.in_b = FPNumBase(width)
 541         self.out_a = FPNumIn(None, width)
 542         self.out_b = FPNumIn(None, width)
 543         self.exp_eq = Signal(reset_less=True)
 544
 545     def elaborate(self, platform):
 546         # This one however (single-cycle) will do the shift
 547         # in one go.
 548
 549         m = Module()
 550
 551         m.submodules.align_in_a = self.in_a
 552         m.submodules.align_in_b = self.in_b
 553         m.submodules.align_out_a = self.out_a
 554         m.submodules.align_out_b = self.out_b
 555
 556         # NOTE: this does *not* do single-cycle multi-shifting,
 557         #       it *STAYS* in the align state until exponents match
 558
 559         # exponent of a greater than b: shift b down
 560         m.d.comb += self.exp_eq.eq(0)
 561         m.d.comb += self.out_a.eq(self.in_a)
 562         m.d.comb += self.out_b.eq(self.in_b)
 563         agtb = Signal(reset_less=True)
 564         altb = Signal(reset_less=True)
 565         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 566         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 567         with m.If(agtb):
 568             m.d.comb += self.out_b.shift_down(self.in_b)
 569         # exponent of b greater than a: shift a down
 570         with m.Elif(altb):
 571             m.d.comb += self.out_a.shift_down(self.in_a)
 572         # exponents equal: move to next stage.
 573         with m.Else():
 574             m.d.comb += self.exp_eq.eq(1)
 575         return m
 576
 577
 578 class FPAddAlignMulti(FPState):
 579
 580     def __init__(self, width, id_wid):
 581         FPState.__init__(self, "align")
 582         self.mod = FPAddAlignMultiMod(width)
 583         self.out_a = FPNumIn(None, width)
 584         self.out_b = FPNumIn(None, width)
 585         self.exp_eq = Signal(reset_less=True)
 586
 587     def setup(self, m, in_a, in_b):
 588         """ links module to inputs and outputs
 589         """
 590         m.submodules.align = self.mod
 591         m.d.comb += self.mod.in_a.eq(in_a)
 592         m.d.comb += self.mod.in_b.eq(in_b)
 593         #m.d.comb += self.out_a.eq(self.mod.out_a)
 594         #m.d.comb += self.out_b.eq(self.mod.out_b)
 595         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 596         m.d.sync += self.out_a.eq(self.mod.out_a)
 597         m.d.sync += self.out_b.eq(self.mod.out_b)
 598
 599     def action(self, m):
 600         with m.If(self.exp_eq):
 601             m.next = "add_0"
 602
 603
 604 class FPNumIn2Ops:
 605
 606     def __init__(self, width, id_wid):
 607         self.a = FPNumIn(None, width)
 608         self.b = FPNumIn(None, width)
 609         self.z = FPNumOut(width, False)
 610         self.out_do_z = Signal(reset_less=True)
 611         self.oz = Signal(width, reset_less=True)
 612         self.mid = Signal(id_wid, reset_less=True)
 613
 614     def eq(self, i):
 615         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 616                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 617
 618
 619 class FPAddAlignSingleMod:
 620
 621     def __init__(self, width, id_wid):
 622         self.width = width
 623         self.id_wid = id_wid
 624         self.i = self.ispec()
 625         self.o = self.ospec()
 626
 627     def ispec(self):
 628         return FPSCData(self.width, self.id_wid)
 629
 630     def ospec(self):
 631         return FPNumIn2Ops(self.width, self.id_wid)
 632
 633     def process(self, i):
 634         return self.o
 635
 636     def setup(self, m, i):
 637         """ links module to inputs and outputs
 638         """
 639         m.submodules.align = self
 640         m.d.comb += self.i.eq(i)
 641
 642     def elaborate(self, platform):
 643         """ Aligns A against B or B against A, depending on which has the
 644             greater exponent.  This is done in a *single* cycle using
 645             variable-width bit-shift
 646
 647             the shifter used here is quite expensive in terms of gates.
 648             Mux A or B in (and out) into temporaries, as only one of them
 649             needs to be aligned against the other
 650         """
 651         m = Module()
 652
 653         m.submodules.align_in_a = self.i.a
 654         m.submodules.align_in_b = self.i.b
 655         m.submodules.align_out_a = self.o.a
 656         m.submodules.align_out_b = self.o.b
 657
 658         # temporary (muxed) input and output to be shifted
 659         t_inp = FPNumBase(self.width)
 660         t_out = FPNumIn(None, self.width)
 661         espec = (len(self.i.a.e), True)
 662         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 663         m.submodules.align_t_in = t_inp
 664         m.submodules.align_t_out = t_out
 665         m.submodules.multishift_r = msr
 666
 667         ediff = Signal(espec, reset_less=True)
 668         ediffr = Signal(espec, reset_less=True)
 669         tdiff = Signal(espec, reset_less=True)
 670         elz = Signal(reset_less=True)
 671         egz = Signal(reset_less=True)
 672
 673         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 674         m.d.comb += msr.inp.eq(t_inp.m)
 675         m.d.comb += msr.diff.eq(tdiff)
 676         m.d.comb += t_out.m.eq(msr.m)
 677         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 678         m.d.comb += t_out.s.eq(t_inp.s)
 679
 680         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 681         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 682         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 683         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 684
 685         # default: A-exp == B-exp, A and B untouched (fall through)
 686         m.d.comb += self.o.a.eq(self.i.a)
 687         m.d.comb += self.o.b.eq(self.i.b)
 688         # only one shifter (muxed)
 689         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 690         # exponent of a greater than b: shift b down
 691         with m.If(~self.i.out_do_z):
 692             with m.If(egz):
 693                 m.d.comb += [t_inp.eq(self.i.b),
 694                              tdiff.eq(ediff),
 695                              self.o.b.eq(t_out),
 696                              self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 697                             ]
 698             # exponent of b greater than a: shift a down
 699             with m.Elif(elz):
 700                 m.d.comb += [t_inp.eq(self.i.a),
 701                              tdiff.eq(ediffr),
 702                              self.o.a.eq(t_out),
 703                              self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 704                             ]
 705
 706         m.d.comb += self.o.mid.eq(self.i.mid)
 707         m.d.comb += self.o.z.eq(self.i.z)
 708         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 709         m.d.comb += self.o.oz.eq(self.i.z.v)
 710
 711         return m
 712
 713
 714 class FPAddAlignSingle(FPState):
 715
 716     def __init__(self, width, id_wid):
 717         FPState.__init__(self, "align")
 718         self.mod = FPAddAlignSingleMod(width, id_wid)
 719         self.out_a = FPNumIn(None, width)
 720         self.out_b = FPNumIn(None, width)
 721
 722     def setup(self, m, i):
 723         """ links module to inputs and outputs
 724         """
 725         self.mod.setup(m, i)
 726
 727         # NOTE: could be done as comb
 728         m.d.sync += self.out_a.eq(self.mod.out_a)
 729         m.d.sync += self.out_b.eq(self.mod.out_b)
 730
 731     def action(self, m):
 732         m.next = "add_0"
 733
 734
 735 class FPAddAlignSingleAdd(FPState):
 736
 737     def __init__(self, width, id_wid):
 738         FPState.__init__(self, "align")
 739         self.width = width
 740         self.id_wid = id_wid
 741         self.a1o = self.ospec()
 742
 743     def ispec(self):
 744         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 745
 746     def ospec(self):
 747         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 748
 749     def setup(self, m, i):
 750         """ links module to inputs and outputs
 751         """
 752
 753         # chain AddAlignSingle, AddStage0 and AddStage1
 754         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 755         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 756         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 757
 758         chain = StageChain([mod, a0mod, a1mod])
 759         chain.setup(m, i)
 760
 761         m.d.sync += self.a1o.eq(a1mod.o)
 762
 763     def action(self, m):
 764         m.next = "normalise_1"
 765
 766
 767 class FPAddStage0Data:
 768
 769     def __init__(self, width, id_wid):
 770         self.z = FPNumBase(width, False)
 771         self.out_do_z = Signal(reset_less=True)
 772         self.oz = Signal(width, reset_less=True)
 773         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 774         self.mid = Signal(id_wid, reset_less=True)
 775
 776     def eq(self, i):
 777         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 778                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 779
 780
 781 class FPAddStage0Mod:
 782
 783     def __init__(self, width, id_wid):
 784         self.width = width
 785         self.id_wid = id_wid
 786         self.i = self.ispec()
 787         self.o = self.ospec()
 788
 789     def ispec(self):
 790         return FPSCData(self.width, self.id_wid)
 791
 792     def ospec(self):
 793         return FPAddStage0Data(self.width, self.id_wid)
 794
 795     def process(self, i):
 796         return self.o
 797
 798     def setup(self, m, i):
 799         """ links module to inputs and outputs
 800         """
 801         m.submodules.add0 = self
 802         m.d.comb += self.i.eq(i)
 803
 804     def elaborate(self, platform):
 805         m = Module()
 806         m.submodules.add0_in_a = self.i.a
 807         m.submodules.add0_in_b = self.i.b
 808         m.submodules.add0_out_z = self.o.z
 809
 810         # store intermediate tests (and zero-extended mantissas)
 811         seq = Signal(reset_less=True)
 812         mge = Signal(reset_less=True)
 813         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 814         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 815         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 816                      mge.eq(self.i.a.m >= self.i.b.m),
 817                      am0.eq(Cat(self.i.a.m, 0)),
 818                      bm0.eq(Cat(self.i.b.m, 0))
 819                     ]
 820         # same-sign (both negative or both positive) add mantissas
 821         with m.If(~self.i.out_do_z):
 822             m.d.comb += self.o.z.e.eq(self.i.a.e)
 823             with m.If(seq):
 824                 m.d.comb += [
 825                     self.o.tot.eq(am0 + bm0),
 826                     self.o.z.s.eq(self.i.a.s)
 827                 ]
 828             # a mantissa greater than b, use a
 829             with m.Elif(mge):
 830                 m.d.comb += [
 831                     self.o.tot.eq(am0 - bm0),
 832                     self.o.z.s.eq(self.i.a.s)
 833                 ]
 834             # b mantissa greater than a, use b
 835             with m.Else():
 836                 m.d.comb += [
 837                     self.o.tot.eq(bm0 - am0),
 838                     self.o.z.s.eq(self.i.b.s)
 839             ]
 840         with m.Else():
 841             m.d.comb += self.o.oz.eq(self.i.z.v)
 842
 843         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 844         m.d.comb += self.o.mid.eq(self.i.mid)
 845         return m
 846
 847
 848 class FPAddStage0(FPState):
 849     """ First stage of add.  covers same-sign (add) and subtract
 850         special-casing when mantissas are greater or equal, to
 851         give greatest accuracy.
 852     """
 853
 854     def __init__(self, width, id_wid):
 855         FPState.__init__(self, "add_0")
 856         self.mod = FPAddStage0Mod(width)
 857         self.o = self.mod.ospec()
 858
 859     def setup(self, m, i):
 860         """ links module to inputs and outputs
 861         """
 862         self.mod.setup(m, i)
 863
 864         # NOTE: these could be done as combinatorial (merge add0+add1)
 865         m.d.sync += self.o.eq(self.mod.o)
 866
 867     def action(self, m):
 868         m.next = "add_1"
 869
 870
 871 class FPAddStage1Data:
 872
 873     def __init__(self, width, id_wid):
 874         self.z = FPNumBase(width, False)
 875         self.out_do_z = Signal(reset_less=True)
 876         self.oz = Signal(width, reset_less=True)
 877         self.of = Overflow()
 878         self.mid = Signal(id_wid, reset_less=True)
 879
 880     def eq(self, i):
 881         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 882                 self.of.eq(i.of), self.mid.eq(i.mid)]
 883
 884
 885
 886 class FPAddStage1Mod(FPState):
 887     """ Second stage of add: preparation for normalisation.
 888         detects when tot sum is too big (tot[27] is kinda a carry bit)
 889     """
 890
 891     def __init__(self, width, id_wid):
 892         self.width = width
 893         self.id_wid = id_wid
 894         self.i = self.ispec()
 895         self.o = self.ospec()
 896
 897     def ispec(self):
 898         return FPAddStage0Data(self.width, self.id_wid)
 899
 900     def ospec(self):
 901         return FPAddStage1Data(self.width, self.id_wid)
 902
 903     def process(self, i):
 904         return self.o
 905
 906     def setup(self, m, i):
 907         """ links module to inputs and outputs
 908         """
 909         m.submodules.add1 = self
 910         m.submodules.add1_out_overflow = self.o.of
 911
 912         m.d.comb += self.i.eq(i)
 913
 914     def elaborate(self, platform):
 915         m = Module()
 916         #m.submodules.norm1_in_overflow = self.in_of
 917         #m.submodules.norm1_out_overflow = self.out_of
 918         #m.submodules.norm1_in_z = self.in_z
 919         #m.submodules.norm1_out_z = self.out_z
 920         m.d.comb += self.o.z.eq(self.i.z)
 921         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 922         with m.If(~self.i.out_do_z):
 923             with m.If(self.i.tot[-1]):
 924                 m.d.comb += [
 925                     self.o.z.m.eq(self.i.tot[4:]),
 926                     self.o.of.m0.eq(self.i.tot[4]),
 927                     self.o.of.guard.eq(self.i.tot[3]),
 928                     self.o.of.round_bit.eq(self.i.tot[2]),
 929                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 930                     self.o.z.e.eq(self.i.z.e + 1)
 931             ]
 932             # tot[-1] (MSB) zero case
 933             with m.Else():
 934                 m.d.comb += [
 935                     self.o.z.m.eq(self.i.tot[3:]),
 936                     self.o.of.m0.eq(self.i.tot[3]),
 937                     self.o.of.guard.eq(self.i.tot[2]),
 938                     self.o.of.round_bit.eq(self.i.tot[1]),
 939                     self.o.of.sticky.eq(self.i.tot[0])
 940             ]
 941
 942         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 943         m.d.comb += self.o.oz.eq(self.i.oz)
 944         m.d.comb += self.o.mid.eq(self.i.mid)
 945
 946         return m
 947
 948
 949 class FPAddStage1(FPState):
 950
 951     def __init__(self, width, id_wid):
 952         FPState.__init__(self, "add_1")
 953         self.mod = FPAddStage1Mod(width)
 954         self.out_z = FPNumBase(width, False)
 955         self.out_of = Overflow()
 956         self.norm_stb = Signal()
 957
 958     def setup(self, m, i):
 959         """ links module to inputs and outputs
 960         """
 961         self.mod.setup(m, i)
 962
 963         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 964
 965         m.d.sync += self.out_of.eq(self.mod.out_of)
 966         m.d.sync += self.out_z.eq(self.mod.out_z)
 967         m.d.sync += self.norm_stb.eq(1)
 968
 969     def action(self, m):
 970         m.next = "normalise_1"
 971
 972
 973 class FPNormaliseModSingle:
 974
 975     def __init__(self, width):
 976         self.width = width
 977         self.in_z = self.ispec()
 978         self.out_z = self.ospec()
 979
 980     def ispec(self):
 981         return FPNumBase(self.width, False)
 982
 983     def ospec(self):
 984         return FPNumBase(self.width, False)
 985
 986     def setup(self, m, i):
 987         """ links module to inputs and outputs
 988         """
 989         m.submodules.normalise = self
 990         m.d.comb += self.i.eq(i)
 991
 992     def elaborate(self, platform):
 993         m = Module()
 994
 995         mwid = self.out_z.m_width+2
 996         pe = PriorityEncoder(mwid)
 997         m.submodules.norm_pe = pe
 998
 999         m.submodules.norm1_out_z = self.out_z
1000         m.submodules.norm1_in_z = self.in_z
1001
1002         in_z = FPNumBase(self.width, False)
1003         in_of = Overflow()
1004         m.submodules.norm1_insel_z = in_z
1005         m.submodules.norm1_insel_overflow = in_of
1006
1007         espec = (len(in_z.e), True)
1008         ediff_n126 = Signal(espec, reset_less=True)
1009         msr = MultiShiftRMerge(mwid, espec)
1010         m.submodules.multishift_r = msr
1011
1012         m.d.comb += in_z.eq(self.in_z)
1013         m.d.comb += in_of.eq(self.in_of)
1014         # initialise out from in (overridden below)
1015         m.d.comb += self.out_z.eq(in_z)
1016         m.d.comb += self.out_of.eq(in_of)
1017         # normalisation decrease condition
1018         decrease = Signal(reset_less=True)
1019         m.d.comb += decrease.eq(in_z.m_msbzero)
1020         # decrease exponent
1021         with m.If(decrease):
1022             # *sigh* not entirely obvious: count leading zeros (clz)
1023             # with a PriorityEncoder: to find from the MSB
1024             # we reverse the order of the bits.
1025             temp_m = Signal(mwid, reset_less=True)
1026             temp_s = Signal(mwid+1, reset_less=True)
1027             clz = Signal((len(in_z.e), True), reset_less=True)
1028             m.d.comb += [
1029                 # cat round and guard bits back into the mantissa
1030                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1031                 pe.i.eq(temp_m[::-1]),          # inverted
1032                 clz.eq(pe.o),                   # count zeros from MSB down
1033                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1034                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1035                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1036             ]
1037
1038         return m
1039
1040 class FPNorm1Data:
1041
1042     def __init__(self, width, id_wid):
1043         self.roundz = Signal(reset_less=True)
1044         self.z = FPNumBase(width, False)
1045         self.out_do_z = Signal(reset_less=True)
1046         self.oz = Signal(width, reset_less=True)
1047         self.mid = Signal(id_wid, reset_less=True)
1048
1049     def eq(self, i):
1050         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1051                 self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1052
1053
1054 class FPNorm1ModSingle:
1055
1056     def __init__(self, width, id_wid):
1057         self.width = width
1058         self.id_wid = id_wid
1059         self.i = self.ispec()
1060         self.o = self.ospec()
1061
1062     def ispec(self):
1063         return FPAddStage1Data(self.width, self.id_wid)
1064
1065     def ospec(self):
1066         return FPNorm1Data(self.width, self.id_wid)
1067
1068     def setup(self, m, i):
1069         """ links module to inputs and outputs
1070         """
1071         m.submodules.normalise_1 = self
1072         m.d.comb += self.i.eq(i)
1073
1074     def process(self, i):
1075         return self.o
1076
1077     def elaborate(self, platform):
1078         m = Module()
1079
1080         mwid = self.o.z.m_width+2
1081         pe = PriorityEncoder(mwid)
1082         m.submodules.norm_pe = pe
1083
1084         of = Overflow()
1085         m.d.comb += self.o.roundz.eq(of.roundz)
1086
1087         m.submodules.norm1_out_z = self.o.z
1088         m.submodules.norm1_out_overflow = of
1089         m.submodules.norm1_in_z = self.i.z
1090         m.submodules.norm1_in_overflow = self.i.of
1091
1092         i = self.ispec()
1093         m.submodules.norm1_insel_z = i.z
1094         m.submodules.norm1_insel_overflow = i.of
1095
1096         espec = (len(i.z.e), True)
1097         ediff_n126 = Signal(espec, reset_less=True)
1098         msr = MultiShiftRMerge(mwid, espec)
1099         m.submodules.multishift_r = msr
1100
1101         m.d.comb += i.eq(self.i)
1102         # initialise out from in (overridden below)
1103         m.d.comb += self.o.z.eq(i.z)
1104         m.d.comb += of.eq(i.of)
1105         # normalisation increase/decrease conditions
1106         decrease = Signal(reset_less=True)
1107         increase = Signal(reset_less=True)
1108         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1109         m.d.comb += increase.eq(i.z.exp_lt_n126)
1110         # decrease exponent
1111         with m.If(~self.i.out_do_z):
1112             with m.If(decrease):
1113                 # *sigh* not entirely obvious: count leading zeros (clz)
1114                 # with a PriorityEncoder: to find from the MSB
1115                 # we reverse the order of the bits.
1116                 temp_m = Signal(mwid, reset_less=True)
1117                 temp_s = Signal(mwid+1, reset_less=True)
1118                 clz = Signal((len(i.z.e), True), reset_less=True)
1119                 # make sure that the amount to decrease by does NOT
1120                 # go below the minimum non-INF/NaN exponent
1121                 limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1122                              i.z.exp_sub_n126)
1123                 m.d.comb += [
1124                     # cat round and guard bits back into the mantissa
1125                     temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1126                     pe.i.eq(temp_m[::-1]),          # inverted
1127                     clz.eq(limclz),                 # count zeros from MSB down
1128                     temp_s.eq(temp_m << clz),       # shift mantissa UP
1129                     self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1130                     self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1131                     of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1132                     # overflow in bits 0..1: got shifted too (leave sticky)
1133                     of.guard.eq(temp_s[1]),       # guard
1134                     of.round_bit.eq(temp_s[0]),   # round
1135                 ]
1136             # increase exponent
1137             with m.Elif(increase):
1138                 temp_m = Signal(mwid+1, reset_less=True)
1139                 m.d.comb += [
1140                     temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1141                                   i.z.m)),
1142                     ediff_n126.eq(i.z.N126 - i.z.e),
1143                     # connect multi-shifter to inp/out mantissa (and ediff)
1144                     msr.inp.eq(temp_m),
1145                     msr.diff.eq(ediff_n126),
1146                     self.o.z.m.eq(msr.m[3:]),
1147                     of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1148                     # overflow in bits 0..1: got shifted too (leave sticky)
1149                     of.guard.eq(temp_s[2]),     # guard
1150                     of.round_bit.eq(temp_s[1]), # round
1151                     of.sticky.eq(temp_s[0]),    # sticky
1152                     self.o.z.e.eq(i.z.e + ediff_n126),
1153                 ]
1154
1155         m.d.comb += self.o.mid.eq(self.i.mid)
1156         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
1157         m.d.comb += self.o.oz.eq(self.i.oz)
1158
1159         return m
1160
1161
1162 class FPNorm1ModMulti:
1163
1164     def __init__(self, width, single_cycle=True):
1165         self.width = width
1166         self.in_select = Signal(reset_less=True)
1167         self.in_z = FPNumBase(width, False)
1168         self.in_of = Overflow()
1169         self.temp_z = FPNumBase(width, False)
1170         self.temp_of = Overflow()
1171         self.out_z = FPNumBase(width, False)
1172         self.out_of = Overflow()
1173
1174     def elaborate(self, platform):
1175         m = Module()
1176
1177         m.submodules.norm1_out_z = self.out_z
1178         m.submodules.norm1_out_overflow = self.out_of
1179         m.submodules.norm1_temp_z = self.temp_z
1180         m.submodules.norm1_temp_of = self.temp_of
1181         m.submodules.norm1_in_z = self.in_z
1182         m.submodules.norm1_in_overflow = self.in_of
1183
1184         in_z = FPNumBase(self.width, False)
1185         in_of = Overflow()
1186         m.submodules.norm1_insel_z = in_z
1187         m.submodules.norm1_insel_overflow = in_of
1188
1189         # select which of temp or in z/of to use
1190         with m.If(self.in_select):
1191             m.d.comb += in_z.eq(self.in_z)
1192             m.d.comb += in_of.eq(self.in_of)
1193         with m.Else():
1194             m.d.comb += in_z.eq(self.temp_z)
1195             m.d.comb += in_of.eq(self.temp_of)
1196         # initialise out from in (overridden below)
1197         m.d.comb += self.out_z.eq(in_z)
1198         m.d.comb += self.out_of.eq(in_of)
1199         # normalisation increase/decrease conditions
1200         decrease = Signal(reset_less=True)
1201         increase = Signal(reset_less=True)
1202         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1203         m.d.comb += increase.eq(in_z.exp_lt_n126)
1204         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1205         # decrease exponent
1206         with m.If(decrease):
1207             m.d.comb += [
1208                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1209                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1210                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1211                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1212                 self.out_of.round_bit.eq(0),        # reset round bit
1213                 self.out_of.m0.eq(in_of.guard),
1214             ]
1215         # increase exponent
1216         with m.Elif(increase):
1217             m.d.comb += [
1218                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1219                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1220                 self.out_of.guard.eq(in_z.m[0]),
1221                 self.out_of.m0.eq(in_z.m[1]),
1222                 self.out_of.round_bit.eq(in_of.guard),
1223                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1224             ]
1225
1226         return m
1227
1228
1229 class FPNorm1Single(FPState):
1230
1231     def __init__(self, width, id_wid, single_cycle=True):
1232         FPState.__init__(self, "normalise_1")
1233         self.mod = FPNorm1ModSingle(width)
1234         self.o = self.ospec()
1235         self.out_z = FPNumBase(width, False)
1236         self.out_roundz = Signal(reset_less=True)
1237
1238     def ispec(self):
1239         return self.mod.ispec()
1240
1241     def ospec(self):
1242         return self.mod.ospec()
1243
1244     def setup(self, m, i):
1245         """ links module to inputs and outputs
1246         """
1247         self.mod.setup(m, i)
1248
1249     def action(self, m):
1250         m.next = "round"
1251
1252
1253 class FPNorm1Multi(FPState):
1254
1255     def __init__(self, width, id_wid):
1256         FPState.__init__(self, "normalise_1")
1257         self.mod = FPNorm1ModMulti(width)
1258         self.stb = Signal(reset_less=True)
1259         self.ack = Signal(reset=0, reset_less=True)
1260         self.out_norm = Signal(reset_less=True)
1261         self.in_accept = Signal(reset_less=True)
1262         self.temp_z = FPNumBase(width)
1263         self.temp_of = Overflow()
1264         self.out_z = FPNumBase(width)
1265         self.out_roundz = Signal(reset_less=True)
1266
1267     def setup(self, m, in_z, in_of, norm_stb):
1268         """ links module to inputs and outputs
1269         """
1270         self.mod.setup(m, in_z, in_of, norm_stb,
1271                        self.in_accept, self.temp_z, self.temp_of,
1272                        self.out_z, self.out_norm)
1273
1274         m.d.comb += self.stb.eq(norm_stb)
1275         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1276
1277     def action(self, m):
1278         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1279         m.d.sync += self.temp_of.eq(self.mod.out_of)
1280         m.d.sync += self.temp_z.eq(self.out_z)
1281         with m.If(self.out_norm):
1282             with m.If(self.in_accept):
1283                 m.d.sync += [
1284                     self.ack.eq(1),
1285                 ]
1286             with m.Else():
1287                 m.d.sync += self.ack.eq(0)
1288         with m.Else():
1289             # normalisation not required (or done).
1290             m.next = "round"
1291             m.d.sync += self.ack.eq(1)
1292             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1293
1294
1295 class FPNormToPack(FPState):
1296
1297     def __init__(self, width, id_wid):
1298         FPState.__init__(self, "normalise_1")
1299         self.id_wid = id_wid
1300         self.width = width
1301
1302     def ispec(self):
1303         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1304
1305     def ospec(self):
1306         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1307
1308     def setup(self, m, i):
1309         """ links module to inputs and outputs
1310         """
1311
1312         # Normalisation, Rounding Corrections, Pack - in a chain
1313         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1314         rmod = FPRoundMod(self.width, self.id_wid)
1315         cmod = FPCorrectionsMod(self.width, self.id_wid)
1316         pmod = FPPackMod(self.width, self.id_wid)
1317         chain = StageChain([nmod, rmod, cmod, pmod])
1318         chain.setup(m, i)
1319         self.out_z = pmod.ospec()
1320
1321         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1322         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1323
1324     def action(self, m):
1325         m.next = "pack_put_z"
1326
1327
1328 class FPRoundData:
1329
1330     def __init__(self, width, id_wid):
1331         self.z = FPNumBase(width, False)
1332         self.out_do_z = Signal(reset_less=True)
1333         self.mid = Signal(id_wid, reset_less=True)
1334
1335     def eq(self, i):
1336         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z),
1337                 self.mid.eq(i.mid)]
1338
1339
1340 class FPRoundMod:
1341
1342     def __init__(self, width, id_wid):
1343         self.width = width
1344         self.id_wid = id_wid
1345         self.i = self.ispec()
1346         self.out_z = self.ospec()
1347
1348     def ispec(self):
1349         return FPNorm1Data(self.width, self.id_wid)
1350
1351     def ospec(self):
1352         return FPRoundData(self.width, self.id_wid)
1353
1354     def process(self, i):
1355         return self.out_z
1356
1357     def setup(self, m, i):
1358         m.submodules.roundz = self
1359         m.d.comb += self.i.eq(i)
1360
1361     def elaborate(self, platform):
1362         m = Module()
1363         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1364         with m.If(~self.i.out_do_z):
1365             with m.If(self.i.roundz):
1366                 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
1367                 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1368                     m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1369
1370         return m
1371
1372
1373 class FPRound(FPState):
1374
1375     def __init__(self, width, id_wid):
1376         FPState.__init__(self, "round")
1377         self.mod = FPRoundMod(width)
1378         self.out_z = self.ospec()
1379
1380     def ispec(self):
1381         return self.mod.ispec()
1382
1383     def ospec(self):
1384         return self.mod.ospec()
1385
1386     def setup(self, m, i):
1387         """ links module to inputs and outputs
1388         """
1389         self.mod.setup(m, i)
1390
1391         self.idsync(m)
1392         m.d.sync += self.out_z.eq(self.mod.out_z)
1393         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1394
1395     def action(self, m):
1396         m.next = "corrections"
1397
1398
1399 class FPCorrectionsMod:
1400
1401     def __init__(self, width, id_wid):
1402         self.width = width
1403         self.id_wid = id_wid
1404         self.i = self.ispec()
1405         self.out_z = self.ospec()
1406
1407     def ispec(self):
1408         return FPRoundData(self.width, self.id_wid)
1409
1410     def ospec(self):
1411         return FPRoundData(self.width, self.id_wid)
1412
1413     def process(self, i):
1414         return self.out_z
1415
1416     def setup(self, m, i):
1417         """ links module to inputs and outputs
1418         """
1419         m.submodules.corrections = self
1420         m.d.comb += self.i.eq(i)
1421
1422     def elaborate(self, platform):
1423         m = Module()
1424         m.submodules.corr_in_z = self.i.z
1425         m.submodules.corr_out_z = self.out_z.z
1426         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1427         with m.If(~self.i.out_do_z):
1428             with m.If(self.i.z.is_denormalised):
1429                 m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1430         return m
1431
1432
1433 class FPCorrections(FPState):
1434
1435     def __init__(self, width, id_wid):
1436         FPState.__init__(self, "corrections")
1437         self.mod = FPCorrectionsMod(width)
1438         self.out_z = self.ospec()
1439
1440     def ispec(self):
1441         return self.mod.ispec()
1442
1443     def ospec(self):
1444         return self.mod.ospec()
1445
1446     def setup(self, m, in_z):
1447         """ links module to inputs and outputs
1448         """
1449         self.mod.setup(m, in_z)
1450
1451         m.d.sync += self.out_z.eq(self.mod.out_z)
1452         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1453
1454     def action(self, m):
1455         m.next = "pack"
1456
1457
1458 class FPPackData:
1459
1460     def __init__(self, width, id_wid):
1461         self.z = FPNumOut(width, False)
1462         self.mid = Signal(id_wid, reset_less=True)
1463
1464     def eq(self, i):
1465         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1466
1467
1468 class FPPackMod:
1469
1470     def __init__(self, width, id_wid):
1471         self.width = width
1472         self.id_wid = id_wid
1473         self.i = self.ispec()
1474         self.o = self.ospec()
1475
1476     def ispec(self):
1477         return FPRoundData(self.width, self.id_wid)
1478
1479     def ospec(self):
1480         return FPPackData(self.width, self.id_wid)
1481
1482     def process(self, i):
1483         return self.o
1484
1485     def setup(self, m, in_z):
1486         """ links module to inputs and outputs
1487         """
1488         m.submodules.pack = self
1489         m.d.comb += self.i.eq(in_z)
1490
1491     def elaborate(self, platform):
1492         m = Module()
1493         m.submodules.pack_in_z = self.i.z
1494         m.d.comb += self.o.mid.eq(self.i.mid)
1495         with m.If(~self.i.out_do_z):
1496             with m.If(self.i.z.is_overflowed):
1497                 m.d.comb += self.o.z.inf(self.i.z.s)
1498             with m.Else():
1499                 m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1500         with m.Else():
1501             m.d.comb += self.o.z.eq(self.i.z)
1502         return m
1503
1504
1505 class FPPack(FPState):
1506
1507     def __init__(self, width, id_wid):
1508         FPState.__init__(self, "pack")
1509         self.mod = FPPackMod(width)
1510         self.out_z = self.ospec()
1511
1512     def ispec(self):
1513         return self.mod.ispec()
1514
1515     def ospec(self):
1516         return self.mod.ospec()
1517
1518     def setup(self, m, in_z):
1519         """ links module to inputs and outputs
1520         """
1521         self.mod.setup(m, in_z)
1522
1523         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1524         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1525
1526     def action(self, m):
1527         m.next = "pack_put_z"
1528
1529
1530 class FPPutZ(FPState):
1531
1532     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1533         FPState.__init__(self, state)
1534         if to_state is None:
1535             to_state = "get_ops"
1536         self.to_state = to_state
1537         self.in_z = in_z
1538         self.out_z = out_z
1539         self.in_mid = in_mid
1540         self.out_mid = out_mid
1541
1542     def action(self, m):
1543         if self.in_mid is not None:
1544             m.d.sync += self.out_mid.eq(self.in_mid)
1545         m.d.sync += [
1546           self.out_z.z.v.eq(self.in_z.v)
1547         ]
1548         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1549             m.d.sync += self.out_z.z.stb.eq(0)
1550             m.next = self.to_state
1551         with m.Else():
1552             m.d.sync += self.out_z.z.stb.eq(1)
1553
1554
1555 class FPPutZIdx(FPState):
1556
1557     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1558         FPState.__init__(self, state)
1559         if to_state is None:
1560             to_state = "get_ops"
1561         self.to_state = to_state
1562         self.in_z = in_z
1563         self.out_zs = out_zs
1564         self.in_mid = in_mid
1565
1566     def action(self, m):
1567         outz_stb = Signal(reset_less=True)
1568         outz_ack = Signal(reset_less=True)
1569         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1570                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1571                     ]
1572         m.d.sync += [
1573           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1574         ]
1575         with m.If(outz_stb & outz_ack):
1576             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1577             m.next = self.to_state
1578         with m.Else():
1579             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1580
1581 class FPADDBaseData:
1582
1583     def __init__(self, width, id_wid):
1584         self.width = width
1585         self.id_wid = id_wid
1586         self.a  = Signal(width)
1587         self.b  = Signal(width)
1588         self.mid = Signal(id_wid, reset_less=True)
1589
1590     def eq(self, i):
1591         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1592
1593
1594 class FPOpData:
1595     def __init__(self, width, id_wid):
1596         self.z = FPOp(width)
1597         self.mid = Signal(id_wid, reset_less=True)
1598
1599     def eq(self, i):
1600         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1601
1602
1603 class FPADDBaseMod:
1604
1605     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1606         """ IEEE754 FP Add
1607
1608             * width: bit-width of IEEE754.  supported: 16, 32, 64
1609             * id_wid: an identifier that is sync-connected to the input
1610             * single_cycle: True indicates each stage to complete in 1 clock
1611             * compact: True indicates a reduced number of stages
1612         """
1613         self.width = width
1614         self.id_wid = id_wid
1615         self.single_cycle = single_cycle
1616         self.compact = compact
1617
1618         self.in_t = Trigger()
1619         self.i = self.ispec()
1620         self.o = self.ospec()
1621
1622         self.states = []
1623
1624     def ispec(self):
1625         return FPADDBaseData(self.width, self.id_wid)
1626
1627     def ospec(self):
1628         return FPOpData(self.width, self.id_wid)
1629
1630     def add_state(self, state):
1631         self.states.append(state)
1632         return state
1633
1634     def get_fragment(self, platform=None):
1635         """ creates the HDL code-fragment for FPAdd
1636         """
1637         m = Module()
1638         m.submodules.out_z = self.o.z
1639         m.submodules.in_t = self.in_t
1640         if self.compact:
1641             self.get_compact_fragment(m, platform)
1642         else:
1643             self.get_longer_fragment(m, platform)
1644
1645         with m.FSM() as fsm:
1646
1647             for state in self.states:
1648                 with m.State(state.state_from):
1649                     state.action(m)
1650
1651         return m
1652
1653     def get_longer_fragment(self, m, platform=None):
1654
1655         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1656                                       self.width))
1657         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1658         a = get.out_op1
1659         b = get.out_op2
1660
1661         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1662         sc.setup(m, a, b, self.in_mid)
1663
1664         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1665         dn.setup(m, a, b, sc.in_mid)
1666
1667         if self.single_cycle:
1668             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1669             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1670         else:
1671             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1672             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1673
1674         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1675         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1676
1677         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1678         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1679
1680         if self.single_cycle:
1681             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1682             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1683         else:
1684             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1685             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1686
1687         rn = self.add_state(FPRound(self.width, self.id_wid))
1688         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1689
1690         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1691         cor.setup(m, rn.out_z, rn.in_mid)
1692
1693         pa = self.add_state(FPPack(self.width, self.id_wid))
1694         pa.setup(m, cor.out_z, rn.in_mid)
1695
1696         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1697                                     pa.in_mid, self.out_mid))
1698
1699         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1700                                     pa.in_mid, self.out_mid))
1701
1702     def get_compact_fragment(self, m, platform=None):
1703
1704         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1705                                       self.width, self.id_wid))
1706         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1707
1708         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1709         sc.setup(m, get.o)
1710
1711         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1712         alm.setup(m, sc.o)
1713
1714         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1715         n1.setup(m, alm.a1o)
1716
1717         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1718                                     n1.out_z.mid, self.o.mid))
1719
1720         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1721                                     sc.o.mid, self.o.mid))
1722
1723
1724 class FPADDBase(FPState):
1725
1726     def __init__(self, width, id_wid=None, single_cycle=False):
1727         """ IEEE754 FP Add
1728
1729             * width: bit-width of IEEE754.  supported: 16, 32, 64
1730             * id_wid: an identifier that is sync-connected to the input
1731             * single_cycle: True indicates each stage to complete in 1 clock
1732         """
1733         FPState.__init__(self, "fpadd")
1734         self.width = width
1735         self.single_cycle = single_cycle
1736         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1737         self.o = self.ospec()
1738
1739         self.in_t = Trigger()
1740         self.i = self.ispec()
1741
1742         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1743         self.in_accept = Signal(reset_less=True)
1744         self.add_stb = Signal(reset_less=True)
1745         self.add_ack = Signal(reset=0, reset_less=True)
1746
1747     def ispec(self):
1748         return self.mod.ispec()
1749
1750     def ospec(self):
1751         return self.mod.ospec()
1752
1753     def setup(self, m, i, add_stb, in_mid):
1754         m.d.comb += [self.i.eq(i),
1755                      self.mod.i.eq(self.i),
1756                      self.z_done.eq(self.mod.o.z.trigger),
1757                      #self.add_stb.eq(add_stb),
1758                      self.mod.in_t.stb.eq(self.in_t.stb),
1759                      self.in_t.ack.eq(self.mod.in_t.ack),
1760                      self.o.mid.eq(self.mod.o.mid),
1761                      self.o.z.v.eq(self.mod.o.z.v),
1762                      self.o.z.stb.eq(self.mod.o.z.stb),
1763                      self.mod.o.z.ack.eq(self.o.z.ack),
1764                     ]
1765
1766         m.d.sync += self.add_stb.eq(add_stb)
1767         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1768         m.d.sync += self.o.z.ack.eq(0) # likewise
1769         #m.d.sync += self.in_t.stb.eq(0)
1770
1771         m.submodules.fpadd = self.mod
1772
1773     def action(self, m):
1774
1775         # in_accept is set on incoming strobe HIGH and ack LOW.
1776         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1777
1778         #with m.If(self.in_t.ack):
1779         #    m.d.sync += self.in_t.stb.eq(0)
1780         with m.If(~self.z_done):
1781             # not done: test for accepting an incoming operand pair
1782             with m.If(self.in_accept):
1783                 m.d.sync += [
1784                     self.add_ack.eq(1), # acknowledge receipt...
1785                     self.in_t.stb.eq(1), # initiate add
1786                 ]
1787             with m.Else():
1788                 m.d.sync += [self.add_ack.eq(0),
1789                              self.in_t.stb.eq(0),
1790                              self.o.z.ack.eq(1),
1791                             ]
1792         with m.Else():
1793             # done: acknowledge, and write out id and value
1794             m.d.sync += [self.add_ack.eq(1),
1795                          self.in_t.stb.eq(0)
1796                         ]
1797             m.next = "put_z"
1798
1799             return
1800
1801             if self.in_mid is not None:
1802                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1803
1804             m.d.sync += [
1805               self.out_z.v.eq(self.mod.out_z.v)
1806             ]
1807             # move to output state on detecting z ack
1808             with m.If(self.out_z.trigger):
1809                 m.d.sync += self.out_z.stb.eq(0)
1810                 m.next = "put_z"
1811             with m.Else():
1812                 m.d.sync += self.out_z.stb.eq(1)
1813
1814
1815 class ResArray:
1816     def __init__(self, width, id_wid):
1817         self.width = width
1818         self.id_wid = id_wid
1819         res = []
1820         for i in range(rs_sz):
1821             out_z = FPOp(width)
1822             out_z.name = "out_z_%d" % i
1823             res.append(out_z)
1824         self.res = Array(res)
1825         self.in_z = FPOp(width)
1826         self.in_mid = Signal(self.id_wid, reset_less=True)
1827
1828     def setup(self, m, in_z, in_mid):
1829         m.d.comb += [self.in_z.eq(in_z),
1830                      self.in_mid.eq(in_mid)]
1831
1832     def get_fragment(self, platform=None):
1833         """ creates the HDL code-fragment for FPAdd
1834         """
1835         m = Module()
1836         m.submodules.res_in_z = self.in_z
1837         m.submodules += self.res
1838
1839         return m
1840
1841     def ports(self):
1842         res = []
1843         for z in self.res:
1844             res += z.ports()
1845         return res
1846
1847
1848 class FPADD(FPID):
1849     """ FPADD: stages as follows:
1850
1851         FPGetOp (a)
1852            |
1853         FPGetOp (b)
1854            |
1855         FPAddBase---> FPAddBaseMod
1856            |            |
1857         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1858
1859         FPAddBase is tricky: it is both a stage and *has* stages.
1860         Connection to FPAddBaseMod therefore requires an in stb/ack
1861         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1862         needs to be the thing that raises the incoming stb.
1863     """
1864
1865     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1866         """ IEEE754 FP Add
1867
1868             * width: bit-width of IEEE754.  supported: 16, 32, 64
1869             * id_wid: an identifier that is sync-connected to the input
1870             * single_cycle: True indicates each stage to complete in 1 clock
1871         """
1872         self.width = width
1873         self.id_wid = id_wid
1874         self.single_cycle = single_cycle
1875
1876         #self.out_z = FPOp(width)
1877         self.ids = FPID(id_wid)
1878
1879         rs = []
1880         for i in range(rs_sz):
1881             in_a  = FPOp(width)
1882             in_b  = FPOp(width)
1883             in_a.name = "in_a_%d" % i
1884             in_b.name = "in_b_%d" % i
1885             rs.append((in_a, in_b))
1886         self.rs = Array(rs)
1887
1888         res = []
1889         for i in range(rs_sz):
1890             out_z = FPOp(width)
1891             out_z.name = "out_z_%d" % i
1892             res.append(out_z)
1893         self.res = Array(res)
1894
1895         self.states = []
1896
1897     def add_state(self, state):
1898         self.states.append(state)
1899         return state
1900
1901     def get_fragment(self, platform=None):
1902         """ creates the HDL code-fragment for FPAdd
1903         """
1904         m = Module()
1905         m.submodules += self.rs
1906
1907         in_a = self.rs[0][0]
1908         in_b = self.rs[0][1]
1909
1910         geta = self.add_state(FPGetOp("get_a", "get_b",
1911                                       in_a, self.width))
1912         geta.setup(m, in_a)
1913         a = geta.out_op
1914
1915         getb = self.add_state(FPGetOp("get_b", "fpadd",
1916                                       in_b, self.width))
1917         getb.setup(m, in_b)
1918         b = getb.out_op
1919
1920         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1921         ab = self.add_state(ab)
1922         abd = ab.ispec() # create an input spec object for FPADDBase
1923         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1924         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1925         o = ab.o
1926
1927         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1928                                     o.mid, "get_a"))
1929
1930         with m.FSM() as fsm:
1931
1932             for state in self.states:
1933                 with m.State(state.state_from):
1934                     state.action(m)
1935
1936         return m
1937
1938
1939 if __name__ == "__main__":
1940     if True:
1941         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1942         main(alu, ports=alu.rs[0][0].ports() + \
1943                         alu.rs[0][1].ports() + \
1944                         alu.res[0].ports() + \
1945                         [alu.ids.in_mid, alu.ids.out_mid])
1946     else:
1947         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1948         main(alu, ports=[alu.in_a, alu.in_b] + \
1949                         alu.in_t.ports() + \
1950                         alu.out_z.ports() + \
1951                         [alu.in_mid, alu.out_mid])
1952
1953
1954     # works... but don't use, just do "python fname.py convert -t v"
1955     #print (verilog.convert(alu, ports=[
1956     #                        ports=alu.in_a.ports() + \
1957     #                              alu.in_b.ports() + \
1958     #                              alu.out_z.ports())