src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  37         #m.submodules.get_op_in = self.in_op
  38         m.submodules.get_op_out = self.out_op
  39         with m.If(self.out_decode):
  40             m.d.comb += [
  41                 self.out_op.decode(self.in_op.v),
  42             ]
  43         return m
  44
  45
  46 class FPGetOp(FPState):
  47     """ gets operand
  48     """
  49
  50     def __init__(self, in_state, out_state, in_op, width):
  51         FPState.__init__(self, in_state)
  52         self.out_state = out_state
  53         self.mod = FPGetOpMod(width)
  54         self.in_op = in_op
  55         self.out_op = FPNumIn(in_op, width)
  56         self.out_decode = Signal(reset_less=True)
  57
  58     def setup(self, m, in_op):
  59         """ links module to inputs and outputs
  60         """
  61         setattr(m.submodules, self.state_from, self.mod)
  62         m.d.comb += self.mod.in_op.copy(in_op)
  63         m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
  64         m.d.comb += self.out_decode.eq(self.mod.out_decode)
  65
  66     def action(self, m):
  67         with m.If(self.out_decode):
  68             m.next = self.out_state
  69             m.d.sync += [
  70                 self.in_op.ack.eq(0),
  71                 self.out_op.copy(self.mod.out_op)
  72             ]
  73         with m.Else():
  74             m.d.sync += self.in_op.ack.eq(1)
  75
  76
  77 class FPAddSpecialCasesMod:
  78     """ special cases: NaNs, infs, zeros, denormalised
  79         NOTE: some of these are unique to add.  see "Special Operations"
  80         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  81     """
  82
  83     def __init__(self, width):
  84         self.in_a = FPNumBase(width)
  85         self.in_b = FPNumBase(width)
  86         self.out_z = FPNumOut(width, False)
  87         self.out_do_z = Signal(reset_less=True)
  88
  89     def elaborate(self, platform):
  90         m = Module()
  91
  92         m.submodules.sc_in_a = self.in_a
  93         m.submodules.sc_in_b = self.in_b
  94         m.submodules.sc_out_z = self.out_z
  95
  96         s_nomatch = Signal()
  97         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
  98
  99         m_match = Signal()
 100         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 101
 102         # if a is NaN or b is NaN return NaN
 103         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 104             m.d.comb += self.out_do_z.eq(1)
 105             m.d.comb += self.out_z.nan(0)
 106
 107         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 108         # under review
 109
 110         ## if a is zero and b is NaN return -b
 111         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 112         #    m.d.comb += self.out_do_z.eq(1)
 113         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 114
 115         ## if b is zero and a is NaN return -a
 116         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 117         #    m.d.comb += self.out_do_z.eq(1)
 118         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 119
 120         ## if a is -zero and b is NaN return -b
 121         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 122         #    m.d.comb += self.out_do_z.eq(1)
 123         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 124
 125         ## if b is -zero and a is NaN return -a
 126         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 127         #    m.d.comb += self.out_do_z.eq(1)
 128         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 129
 130         # if a is inf return inf (or NaN)
 131         with m.Elif(self.in_a.is_inf):
 132             m.d.comb += self.out_do_z.eq(1)
 133             m.d.comb += self.out_z.inf(self.in_a.s)
 134             # if a is inf and signs don't match return NaN
 135             with m.If(self.in_b.exp_128 & s_nomatch):
 136                 m.d.comb += self.out_z.nan(0)
 137
 138         # if b is inf return inf
 139         with m.Elif(self.in_b.is_inf):
 140             m.d.comb += self.out_do_z.eq(1)
 141             m.d.comb += self.out_z.inf(self.in_b.s)
 142
 143         # if a is zero and b zero return signed-a/b
 144         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 145             m.d.comb += self.out_do_z.eq(1)
 146             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 147                                           self.in_b.e,
 148                                           self.in_b.m[3:-1])
 149
 150         # if a is zero return b
 151         with m.Elif(self.in_a.is_zero):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 154                                       self.in_b.m[3:-1])
 155
 156         # if b is zero return a
 157         with m.Elif(self.in_b.is_zero):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 160                                       self.in_a.m[3:-1])
 161
 162         # if a equal to -b return zero (+ve zero)
 163         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 164             m.d.comb += self.out_do_z.eq(1)
 165             m.d.comb += self.out_z.zero(0)
 166
 167         # Denormalised Number checks
 168         with m.Else():
 169             m.d.comb += self.out_do_z.eq(0)
 170
 171         return m
 172
 173
 174 class FPAddSpecialCases(FPState):
 175     """ special cases: NaNs, infs, zeros, denormalised
 176         NOTE: some of these are unique to add.  see "Special Operations"
 177         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 178     """
 179
 180     def __init__(self, width):
 181         FPState.__init__(self, "special_cases")
 182         self.mod = FPAddSpecialCasesMod(width)
 183         self.out_z = FPNumOut(width, False)
 184         self.out_do_z = Signal(reset_less=True)
 185
 186     def setup(self, m, in_a, in_b):
 187         """ links module to inputs and outputs
 188         """
 189         m.submodules.specialcases = self.mod
 190         m.d.comb += self.mod.in_a.copy(in_a)
 191         m.d.comb += self.mod.in_b.copy(in_b)
 192         #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
 193         m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
 194
 195     def action(self, m):
 196         with m.If(self.out_do_z):
 197             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 198             m.next = "put_z"
 199         with m.Else():
 200             m.next = "denormalise"
 201
 202
 203 class FPAddDeNormMod(FPState):
 204
 205     def __init__(self, width):
 206         self.in_a = FPNumBase(width)
 207         self.in_b = FPNumBase(width)
 208         self.out_a = FPNumBase(width)
 209         self.out_b = FPNumBase(width)
 210
 211     def elaborate(self, platform):
 212         m = Module()
 213         m.submodules.denorm_in_a = self.in_a
 214         m.submodules.denorm_in_b = self.in_b
 215         m.submodules.denorm_out_a = self.out_a
 216         m.submodules.denorm_out_b = self.out_b
 217         # hmmm, don't like repeating identical code
 218         m.d.comb += self.out_a.copy(self.in_a)
 219         with m.If(self.in_a.exp_n127):
 220             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 221         with m.Else():
 222             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 223
 224         m.d.comb += self.out_b.copy(self.in_b)
 225         with m.If(self.in_b.exp_n127):
 226             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 227         with m.Else():
 228             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 229
 230         return m
 231
 232
 233 class FPAddDeNorm(FPState):
 234
 235     def __init__(self, width):
 236         FPState.__init__(self, "denormalise")
 237         self.mod = FPAddDeNormMod(width)
 238         self.out_a = FPNumBase(width)
 239         self.out_b = FPNumBase(width)
 240
 241     def setup(self, m, in_a, in_b):
 242         """ links module to inputs and outputs
 243         """
 244         m.submodules.denormalise = self.mod
 245         m.d.comb += self.mod.in_a.copy(in_a)
 246         m.d.comb += self.mod.in_b.copy(in_b)
 247
 248     def action(self, m):
 249         # Denormalised Number checks
 250         m.next = "align"
 251         m.d.sync += self.out_a.copy(self.mod.out_a)
 252         m.d.sync += self.out_b.copy(self.mod.out_b)
 253
 254
 255 class FPAddAlignMultiMod(FPState):
 256
 257     def __init__(self, width):
 258         self.in_a = FPNumBase(width)
 259         self.in_b = FPNumBase(width)
 260         self.out_a = FPNumIn(None, width)
 261         self.out_b = FPNumIn(None, width)
 262         self.exp_eq = Signal(reset_less=True)
 263
 264     def elaborate(self, platform):
 265         # This one however (single-cycle) will do the shift
 266         # in one go.
 267
 268         m = Module()
 269
 270         m.submodules.align_in_a = self.in_a
 271         m.submodules.align_in_b = self.in_b
 272         m.submodules.align_out_a = self.out_a
 273         m.submodules.align_out_b = self.out_b
 274
 275         # NOTE: this does *not* do single-cycle multi-shifting,
 276         #       it *STAYS* in the align state until exponents match
 277
 278         # exponent of a greater than b: shift b down
 279         m.d.comb += self.exp_eq.eq(0)
 280         m.d.comb += self.out_a.copy(self.in_a)
 281         m.d.comb += self.out_b.copy(self.in_b)
 282         agtb = Signal(reset_less=True)
 283         altb = Signal(reset_less=True)
 284         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 285         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 286         with m.If(agtb):
 287             m.d.comb += self.out_b.shift_down(self.in_b)
 288         # exponent of b greater than a: shift a down
 289         with m.Elif(altb):
 290             m.d.comb += self.out_a.shift_down(self.in_a)
 291         # exponents equal: move to next stage.
 292         with m.Else():
 293             m.d.comb += self.exp_eq.eq(1)
 294         return m
 295
 296
 297 class FPAddAlignMulti(FPState):
 298
 299     def __init__(self, width):
 300         FPState.__init__(self, "align")
 301         self.mod = FPAddAlignMultiMod(width)
 302         self.out_a = FPNumIn(None, width)
 303         self.out_b = FPNumIn(None, width)
 304         self.exp_eq = Signal(reset_less=True)
 305
 306     def setup(self, m, in_a, in_b):
 307         """ links module to inputs and outputs
 308         """
 309         m.submodules.align = self.mod
 310         m.d.comb += self.mod.in_a.copy(in_a)
 311         m.d.comb += self.mod.in_b.copy(in_b)
 312         #m.d.comb += self.out_a.copy(self.mod.out_a)
 313         #m.d.comb += self.out_b.copy(self.mod.out_b)
 314         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 315
 316     def action(self, m):
 317         m.d.sync += self.out_a.copy(self.mod.out_a)
 318         m.d.sync += self.out_b.copy(self.mod.out_b)
 319         with m.If(self.exp_eq):
 320             m.next = "add_0"
 321
 322
 323 class FPAddAlignSingleMod:
 324
 325     def __init__(self, width):
 326         self.width = width
 327         self.in_a = FPNumBase(width)
 328         self.in_b = FPNumBase(width)
 329         self.out_a = FPNumIn(None, width)
 330         self.out_b = FPNumIn(None, width)
 331
 332     def elaborate(self, platform):
 333         """ Aligns A against B or B against A, depending on which has the
 334             greater exponent.  This is done in a *single* cycle using
 335             variable-width bit-shift
 336
 337             the shifter used here is quite expensive in terms of gates.
 338             Mux A or B in (and out) into temporaries, as only one of them
 339             needs to be aligned against the other
 340         """
 341         m = Module()
 342
 343         m.submodules.align_in_a = self.in_a
 344         m.submodules.align_in_b = self.in_b
 345         m.submodules.align_out_a = self.out_a
 346         m.submodules.align_out_b = self.out_b
 347
 348         # temporary (muxed) input and output to be shifted
 349         t_inp = FPNumBase(self.width)
 350         t_out = FPNumIn(None, self.width)
 351         espec = (len(self.in_a.e), True)
 352         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 353         m.submodules.align_t_in = t_inp
 354         m.submodules.align_t_out = t_out
 355         m.submodules.multishift_r = msr
 356
 357         ediff = Signal(espec, reset_less=True)
 358         ediffr = Signal(espec, reset_less=True)
 359         tdiff = Signal(espec, reset_less=True)
 360         elz = Signal(reset_less=True)
 361         egz = Signal(reset_less=True)
 362
 363         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 364         m.d.comb += msr.inp.eq(t_inp.m)
 365         m.d.comb += msr.diff.eq(tdiff)
 366         m.d.comb += t_out.m.eq(msr.m)
 367         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 368         m.d.comb += t_out.s.eq(t_inp.s)
 369
 370         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 371         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 372         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 373         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 374
 375         # default: A-exp == B-exp, A and B untouched (fall through)
 376         m.d.comb += self.out_a.copy(self.in_a)
 377         m.d.comb += self.out_b.copy(self.in_b)
 378         # only one shifter (muxed)
 379         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 380         # exponent of a greater than b: shift b down
 381         with m.If(egz):
 382             m.d.comb += [t_inp.copy(self.in_b),
 383                          tdiff.eq(ediff),
 384                          self.out_b.copy(t_out),
 385                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 386                         ]
 387         # exponent of b greater than a: shift a down
 388         with m.Elif(elz):
 389             m.d.comb += [t_inp.copy(self.in_a),
 390                          tdiff.eq(ediffr),
 391                          self.out_a.copy(t_out),
 392                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 393                         ]
 394         return m
 395
 396
 397 class FPAddAlignSingle(FPState):
 398
 399     def __init__(self, width):
 400         FPState.__init__(self, "align")
 401         self.mod = FPAddAlignSingleMod(width)
 402         self.out_a = FPNumIn(None, width)
 403         self.out_b = FPNumIn(None, width)
 404
 405     def setup(self, m, in_a, in_b):
 406         """ links module to inputs and outputs
 407         """
 408         m.submodules.align = self.mod
 409         m.d.comb += self.mod.in_a.copy(in_a)
 410         m.d.comb += self.mod.in_b.copy(in_b)
 411
 412     def action(self, m):
 413         # NOTE: could be done as comb
 414         m.d.sync += self.out_a.copy(self.mod.out_a)
 415         m.d.sync += self.out_b.copy(self.mod.out_b)
 416         m.next = "add_0"
 417
 418
 419 class FPAddStage0Mod:
 420
 421     def __init__(self, width):
 422         self.in_a = FPNumBase(width)
 423         self.in_b = FPNumBase(width)
 424         self.in_z = FPNumBase(width, False)
 425         self.out_z = FPNumBase(width, False)
 426         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 427
 428     def elaborate(self, platform):
 429         m = Module()
 430         m.submodules.add0_in_a = self.in_a
 431         m.submodules.add0_in_b = self.in_b
 432         m.submodules.add0_out_z = self.out_z
 433
 434         m.d.comb += self.out_z.e.eq(self.in_a.e)
 435
 436         # store intermediate tests (and zero-extended mantissas)
 437         seq = Signal(reset_less=True)
 438         mge = Signal(reset_less=True)
 439         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 440         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 441         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 442                      mge.eq(self.in_a.m >= self.in_b.m),
 443                      am0.eq(Cat(self.in_a.m, 0)),
 444                      bm0.eq(Cat(self.in_b.m, 0))
 445                     ]
 446         # same-sign (both negative or both positive) add mantissas
 447         with m.If(seq):
 448             m.d.comb += [
 449                 self.out_tot.eq(am0 + bm0),
 450                 self.out_z.s.eq(self.in_a.s)
 451             ]
 452         # a mantissa greater than b, use a
 453         with m.Elif(mge):
 454             m.d.comb += [
 455                 self.out_tot.eq(am0 - bm0),
 456                 self.out_z.s.eq(self.in_a.s)
 457             ]
 458         # b mantissa greater than a, use b
 459         with m.Else():
 460             m.d.comb += [
 461                 self.out_tot.eq(bm0 - am0),
 462                 self.out_z.s.eq(self.in_b.s)
 463         ]
 464         return m
 465
 466
 467 class FPAddStage0(FPState):
 468     """ First stage of add.  covers same-sign (add) and subtract
 469         special-casing when mantissas are greater or equal, to
 470         give greatest accuracy.
 471     """
 472
 473     def __init__(self, width):
 474         FPState.__init__(self, "add_0")
 475         self.mod = FPAddStage0Mod(width)
 476         self.out_z = FPNumBase(width, False)
 477         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 478
 479     def setup(self, m, in_a, in_b):
 480         """ links module to inputs and outputs
 481         """
 482         m.submodules.add0 = self.mod
 483
 484         m.d.comb += self.mod.in_a.copy(in_a)
 485         m.d.comb += self.mod.in_b.copy(in_b)
 486
 487     def action(self, m):
 488         m.next = "add_1"
 489         # NOTE: these could be done as combinatorial (merge add0+add1)
 490         m.d.sync += self.out_z.copy(self.mod.out_z)
 491         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 492
 493
 494 class FPAddStage1Mod(FPState):
 495     """ Second stage of add: preparation for normalisation.
 496         detects when tot sum is too big (tot[27] is kinda a carry bit)
 497     """
 498
 499     def __init__(self, width):
 500         self.out_norm = Signal(reset_less=True)
 501         self.in_z = FPNumBase(width, False)
 502         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 503         self.out_z = FPNumBase(width, False)
 504         self.out_of = Overflow()
 505
 506     def elaborate(self, platform):
 507         m = Module()
 508         #m.submodules.norm1_in_overflow = self.in_of
 509         #m.submodules.norm1_out_overflow = self.out_of
 510         #m.submodules.norm1_in_z = self.in_z
 511         #m.submodules.norm1_out_z = self.out_z
 512         m.d.comb += self.out_z.copy(self.in_z)
 513         # tot[27] gets set when the sum overflows. shift result down
 514         with m.If(self.in_tot[-1]):
 515             m.d.comb += [
 516                 self.out_z.m.eq(self.in_tot[4:]),
 517                 self.out_of.m0.eq(self.in_tot[4]),
 518                 self.out_of.guard.eq(self.in_tot[3]),
 519                 self.out_of.round_bit.eq(self.in_tot[2]),
 520                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 521                 self.out_z.e.eq(self.in_z.e + 1)
 522         ]
 523         # tot[27] zero case
 524         with m.Else():
 525             m.d.comb += [
 526                 self.out_z.m.eq(self.in_tot[3:]),
 527                 self.out_of.m0.eq(self.in_tot[3]),
 528                 self.out_of.guard.eq(self.in_tot[2]),
 529                 self.out_of.round_bit.eq(self.in_tot[1]),
 530                 self.out_of.sticky.eq(self.in_tot[0])
 531         ]
 532         return m
 533
 534
 535 class FPAddStage1(FPState):
 536
 537     def __init__(self, width):
 538         FPState.__init__(self, "add_1")
 539         self.mod = FPAddStage1Mod(width)
 540         self.out_z = FPNumBase(width, False)
 541         self.out_of = Overflow()
 542         self.norm_stb = Signal()
 543
 544     def setup(self, m, in_tot, in_z):
 545         """ links module to inputs and outputs
 546         """
 547         m.submodules.add1 = self.mod
 548
 549         m.d.comb += self.mod.in_z.copy(in_z)
 550         m.d.comb += self.mod.in_tot.eq(in_tot)
 551
 552         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 553
 554     def action(self, m):
 555         m.submodules.add1_out_overflow = self.out_of
 556         m.d.sync += self.out_of.copy(self.mod.out_of)
 557         m.d.sync += self.out_z.copy(self.mod.out_z)
 558         m.d.sync += self.norm_stb.eq(1)
 559         m.next = "normalise_1"
 560
 561
 562 class FPNorm1ModSingle:
 563
 564     def __init__(self, width):
 565         self.width = width
 566         self.in_select = Signal(reset_less=True)
 567         self.out_norm = Signal(reset_less=True)
 568         self.in_z = FPNumBase(width, False)
 569         self.in_of = Overflow()
 570         self.temp_z = FPNumBase(width, False)
 571         self.temp_of = Overflow()
 572         self.out_z = FPNumBase(width, False)
 573         self.out_of = Overflow()
 574
 575     def elaborate(self, platform):
 576         m = Module()
 577
 578         mwid = self.out_z.m_width+2
 579         pe = PriorityEncoder(mwid)
 580         m.submodules.norm_pe = pe
 581
 582         m.submodules.norm1_out_z = self.out_z
 583         m.submodules.norm1_out_overflow = self.out_of
 584         m.submodules.norm1_temp_z = self.temp_z
 585         m.submodules.norm1_temp_of = self.temp_of
 586         m.submodules.norm1_in_z = self.in_z
 587         m.submodules.norm1_in_overflow = self.in_of
 588
 589         in_z = FPNumBase(self.width, False)
 590         in_of = Overflow()
 591         m.submodules.norm1_insel_z = in_z
 592         m.submodules.norm1_insel_overflow = in_of
 593
 594         espec = (len(in_z.e), True)
 595         ediff_n126 = Signal(espec, reset_less=True)
 596         msr = MultiShiftRMerge(mwid, espec)
 597         m.submodules.multishift_r = msr
 598
 599         # select which of temp or in z/of to use
 600         with m.If(self.in_select):
 601             m.d.comb += in_z.copy(self.in_z)
 602             m.d.comb += in_of.copy(self.in_of)
 603         with m.Else():
 604             m.d.comb += in_z.copy(self.temp_z)
 605             m.d.comb += in_of.copy(self.temp_of)
 606         # initialise out from in (overridden below)
 607         m.d.comb += self.out_z.copy(in_z)
 608         m.d.comb += self.out_of.copy(in_of)
 609         # normalisation increase/decrease conditions
 610         decrease = Signal(reset_less=True)
 611         increase = Signal(reset_less=True)
 612         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 613         m.d.comb += increase.eq(in_z.exp_lt_n126)
 614         m.d.comb += self.out_norm.eq(0) # loop-end condition
 615         # decrease exponent
 616         with m.If(decrease):
 617             # *sigh* not entirely obvious: count leading zeros (clz)
 618             # with a PriorityEncoder: to find from the MSB
 619             # we reverse the order of the bits.
 620             temp_m = Signal(mwid, reset_less=True)
 621             temp_s = Signal(mwid+1, reset_less=True)
 622             clz = Signal((len(in_z.e), True), reset_less=True)
 623             # make sure that the amount to decrease by does NOT
 624             # go below the minimum non-INF/NaN exponent
 625             limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 626                          in_z.exp_sub_n126)
 627             m.d.comb += [
 628                 # cat round and guard bits back into the mantissa
 629                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 630                 pe.i.eq(temp_m[::-1]),          # inverted
 631                 clz.eq(limclz),                 # count zeros from MSB down
 632                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 633                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 634                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 635                 self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 636                 # overflow in bits 0..1: got shifted too (leave sticky)
 637                 self.out_of.guard.eq(temp_s[1]),     # guard
 638                 self.out_of.round_bit.eq(temp_s[0]), # round
 639             ]
 640         # increase exponent
 641         with m.Elif(increase):
 642             temp_m = Signal(mwid+1, reset_less=True)
 643             m.d.comb += [
 644                 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
 645                               in_z.m)),
 646                 ediff_n126.eq(in_z.N126 - in_z.e),
 647                 # connect multi-shifter to inp/out mantissa (and ediff)
 648                 msr.inp.eq(temp_m),
 649                 msr.diff.eq(ediff_n126),
 650                 self.out_z.m.eq(msr.m[3:]),
 651                 self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
 652                 # overflow in bits 0..1: got shifted too (leave sticky)
 653                 self.out_of.guard.eq(temp_s[2]),     # guard
 654                 self.out_of.round_bit.eq(temp_s[1]), # round
 655                 self.out_of.sticky.eq(temp_s[0]), # sticky
 656                 self.out_z.e.eq(in_z.e + ediff_n126),
 657             ]
 658
 659         return m
 660
 661
 662 class FPNorm1ModMulti:
 663
 664     def __init__(self, width, single_cycle=True):
 665         self.width = width
 666         self.in_select = Signal(reset_less=True)
 667         self.out_norm = Signal(reset_less=True)
 668         self.in_z = FPNumBase(width, False)
 669         self.in_of = Overflow()
 670         self.temp_z = FPNumBase(width, False)
 671         self.temp_of = Overflow()
 672         self.out_z = FPNumBase(width, False)
 673         self.out_of = Overflow()
 674
 675     def elaborate(self, platform):
 676         m = Module()
 677
 678         m.submodules.norm1_out_z = self.out_z
 679         m.submodules.norm1_out_overflow = self.out_of
 680         m.submodules.norm1_temp_z = self.temp_z
 681         m.submodules.norm1_temp_of = self.temp_of
 682         m.submodules.norm1_in_z = self.in_z
 683         m.submodules.norm1_in_overflow = self.in_of
 684
 685         in_z = FPNumBase(self.width, False)
 686         in_of = Overflow()
 687         m.submodules.norm1_insel_z = in_z
 688         m.submodules.norm1_insel_overflow = in_of
 689
 690         # select which of temp or in z/of to use
 691         with m.If(self.in_select):
 692             m.d.comb += in_z.copy(self.in_z)
 693             m.d.comb += in_of.copy(self.in_of)
 694         with m.Else():
 695             m.d.comb += in_z.copy(self.temp_z)
 696             m.d.comb += in_of.copy(self.temp_of)
 697         # initialise out from in (overridden below)
 698         m.d.comb += self.out_z.copy(in_z)
 699         m.d.comb += self.out_of.copy(in_of)
 700         # normalisation increase/decrease conditions
 701         decrease = Signal(reset_less=True)
 702         increase = Signal(reset_less=True)
 703         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 704         m.d.comb += increase.eq(in_z.exp_lt_n126)
 705         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 706         # decrease exponent
 707         with m.If(decrease):
 708             m.d.comb += [
 709                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 710                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 711                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 712                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 713                 self.out_of.round_bit.eq(0),        # reset round bit
 714                 self.out_of.m0.eq(in_of.guard),
 715             ]
 716         # increase exponent
 717         with m.Elif(increase):
 718             m.d.comb += [
 719                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 720                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 721                 self.out_of.guard.eq(in_z.m[0]),
 722                 self.out_of.m0.eq(in_z.m[1]),
 723                 self.out_of.round_bit.eq(in_of.guard),
 724                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 725             ]
 726
 727         return m
 728
 729
 730 class FPNorm1(FPState):
 731
 732     def __init__(self, width, single_cycle=True):
 733         FPState.__init__(self, "normalise_1")
 734         if single_cycle:
 735             self.mod = FPNorm1ModSingle(width)
 736         else:
 737             self.mod = FPNorm1ModMulti(width)
 738         self.stb = Signal(reset_less=True)
 739         self.ack = Signal(reset=0, reset_less=True)
 740         self.out_norm = Signal(reset_less=True)
 741         self.in_accept = Signal(reset_less=True)
 742         self.temp_z = FPNumBase(width)
 743         self.temp_of = Overflow()
 744         self.out_z = FPNumBase(width)
 745         self.out_roundz = Signal(reset_less=True)
 746
 747     def setup(self, m, in_z, in_of, norm_stb):
 748         """ links module to inputs and outputs
 749         """
 750         m.submodules.normalise_1 = self.mod
 751
 752         m.d.comb += self.mod.in_z.copy(in_z)
 753         m.d.comb += self.mod.in_of.copy(in_of)
 754
 755         m.d.comb += self.mod.in_select.eq(self.in_accept)
 756         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 757         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 758
 759         m.d.comb += self.out_z.copy(self.mod.out_z)
 760         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 761
 762         m.d.comb += self.stb.eq(norm_stb)
 763         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 764
 765     def action(self, m):
 766
 767         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 768         m.d.sync += self.temp_of.copy(self.mod.out_of)
 769         m.d.sync += self.temp_z.copy(self.out_z)
 770         with m.If(self.out_norm):
 771             with m.If(self.in_accept):
 772                 m.d.sync += [
 773                     self.ack.eq(1),
 774                 ]
 775             with m.Else():
 776                 m.d.sync += self.ack.eq(0)
 777         with m.Else():
 778             # normalisation not required (or done).
 779             m.next = "round"
 780             m.d.sync += self.ack.eq(1)
 781             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 782
 783
 784 class FPRoundMod:
 785
 786     def __init__(self, width):
 787         self.in_roundz = Signal(reset_less=True)
 788         self.in_z = FPNumBase(width, False)
 789         self.out_z = FPNumBase(width, False)
 790
 791     def elaborate(self, platform):
 792         m = Module()
 793         m.d.comb += self.out_z.copy(self.in_z)
 794         with m.If(self.in_roundz):
 795             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 796             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 797                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 798         return m
 799
 800
 801 class FPRound(FPState):
 802
 803     def __init__(self, width):
 804         FPState.__init__(self, "round")
 805         self.mod = FPRoundMod(width)
 806         self.out_z = FPNumBase(width)
 807
 808     def setup(self, m, in_z, roundz):
 809         """ links module to inputs and outputs
 810         """
 811         m.submodules.roundz = self.mod
 812
 813         m.d.comb += self.mod.in_z.copy(in_z)
 814         m.d.comb += self.mod.in_roundz.eq(roundz)
 815
 816     def action(self, m):
 817         m.d.sync += self.out_z.copy(self.mod.out_z)
 818         m.next = "corrections"
 819
 820
 821 class FPCorrectionsMod:
 822
 823     def __init__(self, width):
 824         self.in_z = FPNumOut(width, False)
 825         self.out_z = FPNumOut(width, False)
 826
 827     def elaborate(self, platform):
 828         m = Module()
 829         m.submodules.corr_in_z = self.in_z
 830         m.submodules.corr_out_z = self.out_z
 831         m.d.comb += self.out_z.copy(self.in_z)
 832         with m.If(self.in_z.is_denormalised):
 833             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 834         return m
 835
 836
 837 class FPCorrections(FPState):
 838
 839     def __init__(self, width):
 840         FPState.__init__(self, "corrections")
 841         self.mod = FPCorrectionsMod(width)
 842         self.out_z = FPNumBase(width)
 843
 844     def setup(self, m, in_z):
 845         """ links module to inputs and outputs
 846         """
 847         m.submodules.corrections = self.mod
 848         m.d.comb += self.mod.in_z.copy(in_z)
 849
 850     def action(self, m):
 851         m.d.sync += self.out_z.copy(self.mod.out_z)
 852         m.next = "pack"
 853
 854
 855 class FPPackMod:
 856
 857     def __init__(self, width):
 858         self.in_z = FPNumOut(width, False)
 859         self.out_z = FPNumOut(width, False)
 860
 861     def elaborate(self, platform):
 862         m = Module()
 863         m.submodules.pack_in_z = self.in_z
 864         with m.If(self.in_z.is_overflowed):
 865             m.d.comb += self.out_z.inf(self.in_z.s)
 866         with m.Else():
 867             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 868         return m
 869
 870
 871 class FPPack(FPState):
 872
 873     def __init__(self, width):
 874         FPState.__init__(self, "pack")
 875         self.mod = FPPackMod(width)
 876         self.out_z = FPNumOut(width, False)
 877
 878     def setup(self, m, in_z):
 879         """ links module to inputs and outputs
 880         """
 881         m.submodules.pack = self.mod
 882         m.d.comb += self.mod.in_z.copy(in_z)
 883
 884     def action(self, m):
 885         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 886         m.next = "pack_put_z"
 887
 888
 889 class FPPutZ(FPState):
 890
 891     def __init__(self, state, in_z, out_z):
 892         FPState.__init__(self, state)
 893         self.in_z = in_z
 894         self.out_z = out_z
 895
 896     def action(self, m):
 897         m.d.sync += [
 898           self.out_z.v.eq(self.in_z.v)
 899         ]
 900         with m.If(self.out_z.stb & self.out_z.ack):
 901             m.d.sync += self.out_z.stb.eq(0)
 902             m.next = "get_a"
 903         with m.Else():
 904             m.d.sync += self.out_z.stb.eq(1)
 905
 906
 907 class FPADD:
 908
 909     def __init__(self, width, id_wid=None, single_cycle=False):
 910         """ IEEE754 FP Add
 911
 912             * width: bit-width of IEEE754.  supported: 16, 32, 64
 913             * id_wid: an identifier that is sync-connected to the input
 914             * single_cycle: True indicates each stage to complete in 1 clock
 915         """
 916         self.id_wid = id_wid
 917         self.width = width
 918         self.single_cycle = single_cycle
 919
 920         if self.id_wid:
 921             self.in_mid = Signal(self.id_wid)
 922             self.out_mid = Signal(self.id_wid)
 923         self.in_a  = FPOp(width)
 924         self.in_b  = FPOp(width)
 925         self.out_z = FPOp(width)
 926
 927         self.states = []
 928
 929     def add_state(self, state):
 930         self.states.append(state)
 931         return state
 932
 933     def get_fragment(self, platform=None):
 934         """ creates the HDL code-fragment for FPAdd
 935         """
 936         m = Module()
 937         m.submodules.in_a = self.in_a
 938         m.submodules.in_b = self.in_b
 939         m.submodules.out_z = self.out_z
 940
 941         geta = self.add_state(FPGetOp("get_a", "get_b",
 942                                       self.in_a, self.width))
 943         geta.setup(m, self.in_a)
 944         a = geta.out_op
 945
 946         getb = self.add_state(FPGetOp("get_b", "special_cases",
 947                                       self.in_b, self.width))
 948         getb.setup(m, self.in_b)
 949         b = getb.out_op
 950
 951         sc = self.add_state(FPAddSpecialCases(self.width))
 952         sc.setup(m, a, b)
 953
 954         dn = self.add_state(FPAddDeNorm(self.width))
 955         dn.setup(m, a, b)
 956
 957         if self.single_cycle:
 958             alm = self.add_state(FPAddAlignSingle(self.width))
 959             alm.setup(m, dn.out_a, dn.out_b)
 960         else:
 961             alm = self.add_state(FPAddAlignMulti(self.width))
 962             alm.setup(m, dn.out_a, dn.out_b)
 963
 964         add0 = self.add_state(FPAddStage0(self.width))
 965         add0.setup(m, alm.out_a, alm.out_b)
 966
 967         add1 = self.add_state(FPAddStage1(self.width))
 968         add1.setup(m, add0.out_tot, add0.out_z)
 969
 970         n1 = self.add_state(FPNorm1(self.width))
 971         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 972
 973         rn = self.add_state(FPRound(self.width))
 974         rn.setup(m, n1.out_z, n1.out_roundz)
 975
 976         cor = self.add_state(FPCorrections(self.width))
 977         cor.setup(m, rn.out_z)
 978
 979         pa = self.add_state(FPPack(self.width))
 980         pa.setup(m, cor.out_z)
 981
 982         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
 983
 984         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
 985
 986         with m.FSM() as fsm:
 987
 988             for state in self.states:
 989                 with m.State(state.state_from):
 990                     state.action(m)
 991
 992         return m
 993
 994
 995 if __name__ == "__main__":
 996     alu = FPADD(width=32, single_cycle=True)
 997     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 998
 999
1000     # works... but don't use, just do "python fname.py convert -t v"
1001     #print (verilog.convert(alu, ports=[
1002     #                        ports=alu.in_a.ports() + \
1003     #                              alu.in_b.ports() + \
1004     #                              alu.out_z.ports())