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use ispec/ospec in FPAddAlignSingleMod
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.a.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.a.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.out_a = FPNumIn(None, width)
712 self.out_b = FPNumIn(None, width)
713
714 self.a0mod = FPAddStage0Mod(width)
715 self.a0_out_z = FPNumBase(width, False)
716 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
717 self.a0_out_z = FPNumBase(width, False)
718
719 self.a1mod = FPAddStage1Mod(width)
720 self.out_z = FPNumBase(width, False)
721 self.out_of = Overflow()
722
723 def setup(self, m, in_a, in_b, in_mid):
724 """ links module to inputs and outputs
725 """
726 self.mod.setup(m, in_a, in_b)
727 m.d.comb += self.out_a.eq(self.mod.o.a)
728 m.d.comb += self.out_b.eq(self.mod.o.b)
729
730 self.a0mod.setup(m, self.out_a, self.out_b)
731 m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
732 m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
733
734 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
735
736 if self.in_mid is not None:
737 m.d.comb += self.in_mid.eq(in_mid)
738
739 def action(self, m):
740 self.idsync(m)
741 m.d.sync += self.out_of.eq(self.a1mod.out_of)
742 m.d.sync += self.out_z.eq(self.a1mod.out_z)
743 m.next = "normalise_1"
744
745
746 class FPAddStage0Mod:
747
748 def __init__(self, width):
749 self.in_a = FPNumBase(width)
750 self.in_b = FPNumBase(width)
751 self.in_z = FPNumBase(width, False)
752 self.out_z = FPNumBase(width, False)
753 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
754
755 def setup(self, m, in_a, in_b):
756 """ links module to inputs and outputs
757 """
758 m.submodules.add0 = self
759 m.d.comb += self.in_a.eq(in_a)
760 m.d.comb += self.in_b.eq(in_b)
761
762 def elaborate(self, platform):
763 m = Module()
764 m.submodules.add0_in_a = self.in_a
765 m.submodules.add0_in_b = self.in_b
766 m.submodules.add0_out_z = self.out_z
767
768 m.d.comb += self.out_z.e.eq(self.in_a.e)
769
770 # store intermediate tests (and zero-extended mantissas)
771 seq = Signal(reset_less=True)
772 mge = Signal(reset_less=True)
773 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
774 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
775 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
776 mge.eq(self.in_a.m >= self.in_b.m),
777 am0.eq(Cat(self.in_a.m, 0)),
778 bm0.eq(Cat(self.in_b.m, 0))
779 ]
780 # same-sign (both negative or both positive) add mantissas
781 with m.If(seq):
782 m.d.comb += [
783 self.out_tot.eq(am0 + bm0),
784 self.out_z.s.eq(self.in_a.s)
785 ]
786 # a mantissa greater than b, use a
787 with m.Elif(mge):
788 m.d.comb += [
789 self.out_tot.eq(am0 - bm0),
790 self.out_z.s.eq(self.in_a.s)
791 ]
792 # b mantissa greater than a, use b
793 with m.Else():
794 m.d.comb += [
795 self.out_tot.eq(bm0 - am0),
796 self.out_z.s.eq(self.in_b.s)
797 ]
798 return m
799
800
801 class FPAddStage0(FPState, FPID):
802 """ First stage of add. covers same-sign (add) and subtract
803 special-casing when mantissas are greater or equal, to
804 give greatest accuracy.
805 """
806
807 def __init__(self, width, id_wid):
808 FPState.__init__(self, "add_0")
809 FPID.__init__(self, id_wid)
810 self.mod = FPAddStage0Mod(width)
811 self.out_z = FPNumBase(width, False)
812 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
813
814 def setup(self, m, in_a, in_b, in_mid):
815 """ links module to inputs and outputs
816 """
817 self.mod.setup(m, in_a, in_b)
818 if self.in_mid is not None:
819 m.d.comb += self.in_mid.eq(in_mid)
820
821 def action(self, m):
822 self.idsync(m)
823 # NOTE: these could be done as combinatorial (merge add0+add1)
824 m.d.sync += self.out_z.eq(self.mod.out_z)
825 m.d.sync += self.out_tot.eq(self.mod.out_tot)
826 m.next = "add_1"
827
828
829 class FPAddStage1Mod(FPState):
830 """ Second stage of add: preparation for normalisation.
831 detects when tot sum is too big (tot[27] is kinda a carry bit)
832 """
833
834 def __init__(self, width):
835 self.out_norm = Signal(reset_less=True)
836 self.in_z = FPNumBase(width, False)
837 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
838 self.out_z = FPNumBase(width, False)
839 self.out_of = Overflow()
840
841 def setup(self, m, in_tot, in_z):
842 """ links module to inputs and outputs
843 """
844 m.submodules.add1 = self
845 m.submodules.add1_out_overflow = self.out_of
846
847 m.d.comb += self.in_z.eq(in_z)
848 m.d.comb += self.in_tot.eq(in_tot)
849
850 def elaborate(self, platform):
851 m = Module()
852 #m.submodules.norm1_in_overflow = self.in_of
853 #m.submodules.norm1_out_overflow = self.out_of
854 #m.submodules.norm1_in_z = self.in_z
855 #m.submodules.norm1_out_z = self.out_z
856 m.d.comb += self.out_z.eq(self.in_z)
857 # tot[-1] (MSB) gets set when the sum overflows. shift result down
858 with m.If(self.in_tot[-1]):
859 m.d.comb += [
860 self.out_z.m.eq(self.in_tot[4:]),
861 self.out_of.m0.eq(self.in_tot[4]),
862 self.out_of.guard.eq(self.in_tot[3]),
863 self.out_of.round_bit.eq(self.in_tot[2]),
864 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
865 self.out_z.e.eq(self.in_z.e + 1)
866 ]
867 # tot[-1] (MSB) zero case
868 with m.Else():
869 m.d.comb += [
870 self.out_z.m.eq(self.in_tot[3:]),
871 self.out_of.m0.eq(self.in_tot[3]),
872 self.out_of.guard.eq(self.in_tot[2]),
873 self.out_of.round_bit.eq(self.in_tot[1]),
874 self.out_of.sticky.eq(self.in_tot[0])
875 ]
876 return m
877
878
879 class FPAddStage1(FPState, FPID):
880
881 def __init__(self, width, id_wid):
882 FPState.__init__(self, "add_1")
883 FPID.__init__(self, id_wid)
884 self.mod = FPAddStage1Mod(width)
885 self.out_z = FPNumBase(width, False)
886 self.out_of = Overflow()
887 self.norm_stb = Signal()
888
889 def setup(self, m, in_tot, in_z, in_mid):
890 """ links module to inputs and outputs
891 """
892 self.mod.setup(m, in_tot, in_z)
893
894 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
895
896 if self.in_mid is not None:
897 m.d.comb += self.in_mid.eq(in_mid)
898
899 def action(self, m):
900 self.idsync(m)
901 m.d.sync += self.out_of.eq(self.mod.out_of)
902 m.d.sync += self.out_z.eq(self.mod.out_z)
903 m.d.sync += self.norm_stb.eq(1)
904 m.next = "normalise_1"
905
906
907 class FPNormaliseModSingle:
908
909 def __init__(self, width):
910 self.width = width
911 self.in_z = FPNumBase(width, False)
912 self.out_z = FPNumBase(width, False)
913
914 def setup(self, m, in_z, out_z, modname):
915 """ links module to inputs and outputs
916 """
917 m.submodules.normalise = self
918 m.d.comb += self.in_z.eq(in_z)
919 m.d.comb += out_z.eq(self.out_z)
920
921 def elaborate(self, platform):
922 m = Module()
923
924 mwid = self.out_z.m_width+2
925 pe = PriorityEncoder(mwid)
926 m.submodules.norm_pe = pe
927
928 m.submodules.norm1_out_z = self.out_z
929 m.submodules.norm1_in_z = self.in_z
930
931 in_z = FPNumBase(self.width, False)
932 in_of = Overflow()
933 m.submodules.norm1_insel_z = in_z
934 m.submodules.norm1_insel_overflow = in_of
935
936 espec = (len(in_z.e), True)
937 ediff_n126 = Signal(espec, reset_less=True)
938 msr = MultiShiftRMerge(mwid, espec)
939 m.submodules.multishift_r = msr
940
941 m.d.comb += in_z.eq(self.in_z)
942 m.d.comb += in_of.eq(self.in_of)
943 # initialise out from in (overridden below)
944 m.d.comb += self.out_z.eq(in_z)
945 m.d.comb += self.out_of.eq(in_of)
946 # normalisation increase/decrease conditions
947 decrease = Signal(reset_less=True)
948 m.d.comb += decrease.eq(in_z.m_msbzero)
949 # decrease exponent
950 with m.If(decrease):
951 # *sigh* not entirely obvious: count leading zeros (clz)
952 # with a PriorityEncoder: to find from the MSB
953 # we reverse the order of the bits.
954 temp_m = Signal(mwid, reset_less=True)
955 temp_s = Signal(mwid+1, reset_less=True)
956 clz = Signal((len(in_z.e), True), reset_less=True)
957 m.d.comb += [
958 # cat round and guard bits back into the mantissa
959 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
960 pe.i.eq(temp_m[::-1]), # inverted
961 clz.eq(pe.o), # count zeros from MSB down
962 temp_s.eq(temp_m << clz), # shift mantissa UP
963 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
964 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
965 ]
966
967 return m
968
969
970 class FPNorm1ModSingle:
971
972 def __init__(self, width):
973 self.width = width
974 self.out_norm = Signal(reset_less=True)
975 self.in_z = FPNumBase(width, False)
976 self.in_of = Overflow()
977 self.out_z = FPNumBase(width, False)
978 self.out_of = Overflow()
979
980 def setup(self, m, in_z, in_of, out_z):
981 """ links module to inputs and outputs
982 """
983 m.submodules.normalise_1 = self
984
985 m.d.comb += self.in_z.eq(in_z)
986 m.d.comb += self.in_of.eq(in_of)
987
988 m.d.comb += out_z.eq(self.out_z)
989
990 def elaborate(self, platform):
991 m = Module()
992
993 mwid = self.out_z.m_width+2
994 pe = PriorityEncoder(mwid)
995 m.submodules.norm_pe = pe
996
997 m.submodules.norm1_out_z = self.out_z
998 m.submodules.norm1_out_overflow = self.out_of
999 m.submodules.norm1_in_z = self.in_z
1000 m.submodules.norm1_in_overflow = self.in_of
1001
1002 in_z = FPNumBase(self.width, False)
1003 in_of = Overflow()
1004 m.submodules.norm1_insel_z = in_z
1005 m.submodules.norm1_insel_overflow = in_of
1006
1007 espec = (len(in_z.e), True)
1008 ediff_n126 = Signal(espec, reset_less=True)
1009 msr = MultiShiftRMerge(mwid, espec)
1010 m.submodules.multishift_r = msr
1011
1012 m.d.comb += in_z.eq(self.in_z)
1013 m.d.comb += in_of.eq(self.in_of)
1014 # initialise out from in (overridden below)
1015 m.d.comb += self.out_z.eq(in_z)
1016 m.d.comb += self.out_of.eq(in_of)
1017 # normalisation increase/decrease conditions
1018 decrease = Signal(reset_less=True)
1019 increase = Signal(reset_less=True)
1020 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1021 m.d.comb += increase.eq(in_z.exp_lt_n126)
1022 # decrease exponent
1023 with m.If(decrease):
1024 # *sigh* not entirely obvious: count leading zeros (clz)
1025 # with a PriorityEncoder: to find from the MSB
1026 # we reverse the order of the bits.
1027 temp_m = Signal(mwid, reset_less=True)
1028 temp_s = Signal(mwid+1, reset_less=True)
1029 clz = Signal((len(in_z.e), True), reset_less=True)
1030 # make sure that the amount to decrease by does NOT
1031 # go below the minimum non-INF/NaN exponent
1032 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1033 in_z.exp_sub_n126)
1034 m.d.comb += [
1035 # cat round and guard bits back into the mantissa
1036 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1037 pe.i.eq(temp_m[::-1]), # inverted
1038 clz.eq(limclz), # count zeros from MSB down
1039 temp_s.eq(temp_m << clz), # shift mantissa UP
1040 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1041 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1042 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1043 # overflow in bits 0..1: got shifted too (leave sticky)
1044 self.out_of.guard.eq(temp_s[1]), # guard
1045 self.out_of.round_bit.eq(temp_s[0]), # round
1046 ]
1047 # increase exponent
1048 with m.Elif(increase):
1049 temp_m = Signal(mwid+1, reset_less=True)
1050 m.d.comb += [
1051 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1052 in_z.m)),
1053 ediff_n126.eq(in_z.N126 - in_z.e),
1054 # connect multi-shifter to inp/out mantissa (and ediff)
1055 msr.inp.eq(temp_m),
1056 msr.diff.eq(ediff_n126),
1057 self.out_z.m.eq(msr.m[3:]),
1058 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1059 # overflow in bits 0..1: got shifted too (leave sticky)
1060 self.out_of.guard.eq(temp_s[2]), # guard
1061 self.out_of.round_bit.eq(temp_s[1]), # round
1062 self.out_of.sticky.eq(temp_s[0]), # sticky
1063 self.out_z.e.eq(in_z.e + ediff_n126),
1064 ]
1065
1066 return m
1067
1068
1069 class FPNorm1ModMulti:
1070
1071 def __init__(self, width, single_cycle=True):
1072 self.width = width
1073 self.in_select = Signal(reset_less=True)
1074 self.out_norm = Signal(reset_less=True)
1075 self.in_z = FPNumBase(width, False)
1076 self.in_of = Overflow()
1077 self.temp_z = FPNumBase(width, False)
1078 self.temp_of = Overflow()
1079 self.out_z = FPNumBase(width, False)
1080 self.out_of = Overflow()
1081
1082 def elaborate(self, platform):
1083 m = Module()
1084
1085 m.submodules.norm1_out_z = self.out_z
1086 m.submodules.norm1_out_overflow = self.out_of
1087 m.submodules.norm1_temp_z = self.temp_z
1088 m.submodules.norm1_temp_of = self.temp_of
1089 m.submodules.norm1_in_z = self.in_z
1090 m.submodules.norm1_in_overflow = self.in_of
1091
1092 in_z = FPNumBase(self.width, False)
1093 in_of = Overflow()
1094 m.submodules.norm1_insel_z = in_z
1095 m.submodules.norm1_insel_overflow = in_of
1096
1097 # select which of temp or in z/of to use
1098 with m.If(self.in_select):
1099 m.d.comb += in_z.eq(self.in_z)
1100 m.d.comb += in_of.eq(self.in_of)
1101 with m.Else():
1102 m.d.comb += in_z.eq(self.temp_z)
1103 m.d.comb += in_of.eq(self.temp_of)
1104 # initialise out from in (overridden below)
1105 m.d.comb += self.out_z.eq(in_z)
1106 m.d.comb += self.out_of.eq(in_of)
1107 # normalisation increase/decrease conditions
1108 decrease = Signal(reset_less=True)
1109 increase = Signal(reset_less=True)
1110 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1111 m.d.comb += increase.eq(in_z.exp_lt_n126)
1112 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1113 # decrease exponent
1114 with m.If(decrease):
1115 m.d.comb += [
1116 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1117 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1118 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1119 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1120 self.out_of.round_bit.eq(0), # reset round bit
1121 self.out_of.m0.eq(in_of.guard),
1122 ]
1123 # increase exponent
1124 with m.Elif(increase):
1125 m.d.comb += [
1126 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1127 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1128 self.out_of.guard.eq(in_z.m[0]),
1129 self.out_of.m0.eq(in_z.m[1]),
1130 self.out_of.round_bit.eq(in_of.guard),
1131 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1132 ]
1133
1134 return m
1135
1136
1137 class FPNorm1Single(FPState, FPID):
1138
1139 def __init__(self, width, id_wid, single_cycle=True):
1140 FPID.__init__(self, id_wid)
1141 FPState.__init__(self, "normalise_1")
1142 self.mod = FPNorm1ModSingle(width)
1143 self.out_norm = Signal(reset_less=True)
1144 self.out_z = FPNumBase(width)
1145 self.out_roundz = Signal(reset_less=True)
1146
1147 def setup(self, m, in_z, in_of, in_mid):
1148 """ links module to inputs and outputs
1149 """
1150 self.mod.setup(m, in_z, in_of, self.out_z)
1151
1152 if self.in_mid is not None:
1153 m.d.comb += self.in_mid.eq(in_mid)
1154
1155 def action(self, m):
1156 self.idsync(m)
1157 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1158 m.next = "round"
1159
1160
1161 class FPNorm1Multi(FPState, FPID):
1162
1163 def __init__(self, width, id_wid):
1164 FPID.__init__(self, id_wid)
1165 FPState.__init__(self, "normalise_1")
1166 self.mod = FPNorm1ModMulti(width)
1167 self.stb = Signal(reset_less=True)
1168 self.ack = Signal(reset=0, reset_less=True)
1169 self.out_norm = Signal(reset_less=True)
1170 self.in_accept = Signal(reset_less=True)
1171 self.temp_z = FPNumBase(width)
1172 self.temp_of = Overflow()
1173 self.out_z = FPNumBase(width)
1174 self.out_roundz = Signal(reset_less=True)
1175
1176 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1177 """ links module to inputs and outputs
1178 """
1179 self.mod.setup(m, in_z, in_of, norm_stb,
1180 self.in_accept, self.temp_z, self.temp_of,
1181 self.out_z, self.out_norm)
1182
1183 m.d.comb += self.stb.eq(norm_stb)
1184 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1185
1186 if self.in_mid is not None:
1187 m.d.comb += self.in_mid.eq(in_mid)
1188
1189 def action(self, m):
1190 self.idsync(m)
1191 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1192 m.d.sync += self.temp_of.eq(self.mod.out_of)
1193 m.d.sync += self.temp_z.eq(self.out_z)
1194 with m.If(self.out_norm):
1195 with m.If(self.in_accept):
1196 m.d.sync += [
1197 self.ack.eq(1),
1198 ]
1199 with m.Else():
1200 m.d.sync += self.ack.eq(0)
1201 with m.Else():
1202 # normalisation not required (or done).
1203 m.next = "round"
1204 m.d.sync += self.ack.eq(1)
1205 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1206
1207
1208 class FPNormToPack(FPState, FPID):
1209
1210 def __init__(self, width, id_wid):
1211 FPID.__init__(self, id_wid)
1212 FPState.__init__(self, "normalise_1")
1213 self.width = width
1214
1215 def setup(self, m, in_z, in_of, in_mid):
1216 """ links module to inputs and outputs
1217 """
1218
1219 # Normalisation (chained to input in_z+in_of)
1220 nmod = FPNorm1ModSingle(self.width)
1221 n_out_z = FPNumBase(self.width)
1222 n_out_roundz = Signal(reset_less=True)
1223 nmod.setup(m, in_z, in_of, n_out_z)
1224
1225 # Rounding (chained to normalisation)
1226 rmod = FPRoundMod(self.width)
1227 r_out_z = FPNumBase(self.width)
1228 rmod.setup(m, n_out_z, n_out_roundz)
1229 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1230 m.d.comb += r_out_z.eq(rmod.out_z)
1231
1232 # Corrections (chained to rounding)
1233 cmod = FPCorrectionsMod(self.width)
1234 c_out_z = FPNumBase(self.width)
1235 cmod.setup(m, r_out_z)
1236 m.d.comb += c_out_z.eq(cmod.out_z)
1237
1238 # Pack (chained to corrections)
1239 self.pmod = FPPackMod(self.width)
1240 self.out_z = FPNumBase(self.width)
1241 self.pmod.setup(m, c_out_z)
1242
1243 # Multiplex ID
1244 if self.in_mid is not None:
1245 m.d.comb += self.in_mid.eq(in_mid)
1246
1247 def action(self, m):
1248 self.idsync(m) # copies incoming ID to outgoing
1249 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1250 m.next = "pack_put_z"
1251
1252
1253 class FPRoundMod:
1254
1255 def __init__(self, width):
1256 self.in_roundz = Signal(reset_less=True)
1257 self.in_z = FPNumBase(width, False)
1258 self.out_z = FPNumBase(width, False)
1259
1260 def setup(self, m, in_z, roundz):
1261 m.submodules.roundz = self
1262
1263 m.d.comb += self.in_z.eq(in_z)
1264 m.d.comb += self.in_roundz.eq(roundz)
1265
1266 def elaborate(self, platform):
1267 m = Module()
1268 m.d.comb += self.out_z.eq(self.in_z)
1269 with m.If(self.in_roundz):
1270 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1271 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1272 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1273 return m
1274
1275
1276 class FPRound(FPState, FPID):
1277
1278 def __init__(self, width, id_wid):
1279 FPState.__init__(self, "round")
1280 FPID.__init__(self, id_wid)
1281 self.mod = FPRoundMod(width)
1282 self.out_z = FPNumBase(width)
1283
1284 def setup(self, m, in_z, roundz, in_mid):
1285 """ links module to inputs and outputs
1286 """
1287 self.mod.setup(m, in_z, roundz)
1288
1289 if self.in_mid is not None:
1290 m.d.comb += self.in_mid.eq(in_mid)
1291
1292 def action(self, m):
1293 self.idsync(m)
1294 m.d.sync += self.out_z.eq(self.mod.out_z)
1295 m.next = "corrections"
1296
1297
1298 class FPCorrectionsMod:
1299
1300 def __init__(self, width):
1301 self.in_z = FPNumOut(width, False)
1302 self.out_z = FPNumOut(width, False)
1303
1304 def setup(self, m, in_z):
1305 """ links module to inputs and outputs
1306 """
1307 m.submodules.corrections = self
1308 m.d.comb += self.in_z.eq(in_z)
1309
1310 def elaborate(self, platform):
1311 m = Module()
1312 m.submodules.corr_in_z = self.in_z
1313 m.submodules.corr_out_z = self.out_z
1314 m.d.comb += self.out_z.eq(self.in_z)
1315 with m.If(self.in_z.is_denormalised):
1316 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1317 return m
1318
1319
1320 class FPCorrections(FPState, FPID):
1321
1322 def __init__(self, width, id_wid):
1323 FPState.__init__(self, "corrections")
1324 FPID.__init__(self, id_wid)
1325 self.mod = FPCorrectionsMod(width)
1326 self.out_z = FPNumBase(width)
1327
1328 def setup(self, m, in_z, in_mid):
1329 """ links module to inputs and outputs
1330 """
1331 self.mod.setup(m, in_z)
1332 if self.in_mid is not None:
1333 m.d.comb += self.in_mid.eq(in_mid)
1334
1335 def action(self, m):
1336 self.idsync(m)
1337 m.d.sync += self.out_z.eq(self.mod.out_z)
1338 m.next = "pack"
1339
1340
1341 class FPPackMod:
1342
1343 def __init__(self, width):
1344 self.in_z = FPNumOut(width, False)
1345 self.out_z = FPNumOut(width, False)
1346
1347 def setup(self, m, in_z):
1348 """ links module to inputs and outputs
1349 """
1350 m.submodules.pack = self
1351 m.d.comb += self.in_z.eq(in_z)
1352
1353 def elaborate(self, platform):
1354 m = Module()
1355 m.submodules.pack_in_z = self.in_z
1356 with m.If(self.in_z.is_overflowed):
1357 m.d.comb += self.out_z.inf(self.in_z.s)
1358 with m.Else():
1359 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1360 return m
1361
1362
1363 class FPPack(FPState, FPID):
1364
1365 def __init__(self, width, id_wid):
1366 FPState.__init__(self, "pack")
1367 FPID.__init__(self, id_wid)
1368 self.mod = FPPackMod(width)
1369 self.out_z = FPNumOut(width, False)
1370
1371 def setup(self, m, in_z, in_mid):
1372 """ links module to inputs and outputs
1373 """
1374 self.mod.setup(m, in_z)
1375 if self.in_mid is not None:
1376 m.d.comb += self.in_mid.eq(in_mid)
1377
1378 def action(self, m):
1379 self.idsync(m)
1380 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1381 m.next = "pack_put_z"
1382
1383
1384 class FPPutZ(FPState):
1385
1386 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1387 FPState.__init__(self, state)
1388 if to_state is None:
1389 to_state = "get_ops"
1390 self.to_state = to_state
1391 self.in_z = in_z
1392 self.out_z = out_z
1393 self.in_mid = in_mid
1394 self.out_mid = out_mid
1395
1396 def action(self, m):
1397 if self.in_mid is not None:
1398 m.d.sync += self.out_mid.eq(self.in_mid)
1399 m.d.sync += [
1400 self.out_z.v.eq(self.in_z.v)
1401 ]
1402 with m.If(self.out_z.stb & self.out_z.ack):
1403 m.d.sync += self.out_z.stb.eq(0)
1404 m.next = self.to_state
1405 with m.Else():
1406 m.d.sync += self.out_z.stb.eq(1)
1407
1408
1409 class FPPutZIdx(FPState):
1410
1411 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1412 FPState.__init__(self, state)
1413 if to_state is None:
1414 to_state = "get_ops"
1415 self.to_state = to_state
1416 self.in_z = in_z
1417 self.out_zs = out_zs
1418 self.in_mid = in_mid
1419
1420 def action(self, m):
1421 outz_stb = Signal(reset_less=True)
1422 outz_ack = Signal(reset_less=True)
1423 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1424 outz_ack.eq(self.out_zs[self.in_mid].ack),
1425 ]
1426 m.d.sync += [
1427 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1428 ]
1429 with m.If(outz_stb & outz_ack):
1430 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1431 m.next = self.to_state
1432 with m.Else():
1433 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1434
1435
1436 class FPADDBaseMod(FPID):
1437
1438 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1439 """ IEEE754 FP Add
1440
1441 * width: bit-width of IEEE754. supported: 16, 32, 64
1442 * id_wid: an identifier that is sync-connected to the input
1443 * single_cycle: True indicates each stage to complete in 1 clock
1444 * compact: True indicates a reduced number of stages
1445 """
1446 FPID.__init__(self, id_wid)
1447 self.width = width
1448 self.single_cycle = single_cycle
1449 self.compact = compact
1450
1451 self.in_t = Trigger()
1452 self.in_a = Signal(width)
1453 self.in_b = Signal(width)
1454 self.out_z = FPOp(width)
1455
1456 self.states = []
1457
1458 def add_state(self, state):
1459 self.states.append(state)
1460 return state
1461
1462 def get_fragment(self, platform=None):
1463 """ creates the HDL code-fragment for FPAdd
1464 """
1465 m = Module()
1466 m.submodules.out_z = self.out_z
1467 m.submodules.in_t = self.in_t
1468 if self.compact:
1469 self.get_compact_fragment(m, platform)
1470 else:
1471 self.get_longer_fragment(m, platform)
1472
1473 with m.FSM() as fsm:
1474
1475 for state in self.states:
1476 with m.State(state.state_from):
1477 state.action(m)
1478
1479 return m
1480
1481 def get_longer_fragment(self, m, platform=None):
1482
1483 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1484 self.in_a, self.in_b, self.width))
1485 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1486 a = get.out_op1
1487 b = get.out_op2
1488
1489 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1490 sc.setup(m, a, b, self.in_mid)
1491
1492 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1493 dn.setup(m, a, b, sc.in_mid)
1494
1495 if self.single_cycle:
1496 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1497 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1498 else:
1499 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1500 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1501
1502 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1503 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1504
1505 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1506 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1507
1508 if self.single_cycle:
1509 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1510 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1511 else:
1512 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1513 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1514
1515 rn = self.add_state(FPRound(self.width, self.id_wid))
1516 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1517
1518 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1519 cor.setup(m, rn.out_z, rn.in_mid)
1520
1521 pa = self.add_state(FPPack(self.width, self.id_wid))
1522 pa.setup(m, cor.out_z, rn.in_mid)
1523
1524 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1525 pa.in_mid, self.out_mid))
1526
1527 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1528 pa.in_mid, self.out_mid))
1529
1530 def get_compact_fragment(self, m, platform=None):
1531
1532 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1533 self.in_a, self.in_b, self.width))
1534 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1535 a = get.out_op1
1536 b = get.out_op2
1537
1538 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1539 sc.setup(m, a, b, self.in_mid)
1540
1541 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1542 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1543
1544 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1545 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1546
1547 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1548 n1.in_mid, self.out_mid))
1549
1550 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1551 sc.in_mid, self.out_mid))
1552
1553
1554 class FPADDBase(FPState, FPID):
1555
1556 def __init__(self, width, id_wid=None, single_cycle=False):
1557 """ IEEE754 FP Add
1558
1559 * width: bit-width of IEEE754. supported: 16, 32, 64
1560 * id_wid: an identifier that is sync-connected to the input
1561 * single_cycle: True indicates each stage to complete in 1 clock
1562 """
1563 FPID.__init__(self, id_wid)
1564 FPState.__init__(self, "fpadd")
1565 self.width = width
1566 self.single_cycle = single_cycle
1567 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1568
1569 self.in_t = Trigger()
1570 self.in_a = Signal(width)
1571 self.in_b = Signal(width)
1572 #self.out_z = FPOp(width)
1573
1574 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1575 self.in_accept = Signal(reset_less=True)
1576 self.add_stb = Signal(reset_less=True)
1577 self.add_ack = Signal(reset=0, reset_less=True)
1578
1579 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1580 self.out_z = out_z
1581 self.out_mid = out_mid
1582 m.d.comb += [self.in_a.eq(a),
1583 self.in_b.eq(b),
1584 self.mod.in_a.eq(self.in_a),
1585 self.mod.in_b.eq(self.in_b),
1586 self.in_mid.eq(in_mid),
1587 self.mod.in_mid.eq(self.in_mid),
1588 self.z_done.eq(self.mod.out_z.trigger),
1589 #self.add_stb.eq(add_stb),
1590 self.mod.in_t.stb.eq(self.in_t.stb),
1591 self.in_t.ack.eq(self.mod.in_t.ack),
1592 self.out_mid.eq(self.mod.out_mid),
1593 self.out_z.v.eq(self.mod.out_z.v),
1594 self.out_z.stb.eq(self.mod.out_z.stb),
1595 self.mod.out_z.ack.eq(self.out_z.ack),
1596 ]
1597
1598 m.d.sync += self.add_stb.eq(add_stb)
1599 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1600 m.d.sync += self.out_z.ack.eq(0) # likewise
1601 #m.d.sync += self.in_t.stb.eq(0)
1602
1603 m.submodules.fpadd = self.mod
1604
1605 def action(self, m):
1606
1607 # in_accept is set on incoming strobe HIGH and ack LOW.
1608 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1609
1610 #with m.If(self.in_t.ack):
1611 # m.d.sync += self.in_t.stb.eq(0)
1612 with m.If(~self.z_done):
1613 # not done: test for accepting an incoming operand pair
1614 with m.If(self.in_accept):
1615 m.d.sync += [
1616 self.add_ack.eq(1), # acknowledge receipt...
1617 self.in_t.stb.eq(1), # initiate add
1618 ]
1619 with m.Else():
1620 m.d.sync += [self.add_ack.eq(0),
1621 self.in_t.stb.eq(0),
1622 self.out_z.ack.eq(1),
1623 ]
1624 with m.Else():
1625 # done: acknowledge, and write out id and value
1626 m.d.sync += [self.add_ack.eq(1),
1627 self.in_t.stb.eq(0)
1628 ]
1629 m.next = "put_z"
1630
1631 return
1632
1633 if self.in_mid is not None:
1634 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1635
1636 m.d.sync += [
1637 self.out_z.v.eq(self.mod.out_z.v)
1638 ]
1639 # move to output state on detecting z ack
1640 with m.If(self.out_z.trigger):
1641 m.d.sync += self.out_z.stb.eq(0)
1642 m.next = "put_z"
1643 with m.Else():
1644 m.d.sync += self.out_z.stb.eq(1)
1645
1646 class ResArray:
1647 def __init__(self, width, id_wid):
1648 self.width = width
1649 self.id_wid = id_wid
1650 res = []
1651 for i in range(rs_sz):
1652 out_z = FPOp(width)
1653 out_z.name = "out_z_%d" % i
1654 res.append(out_z)
1655 self.res = Array(res)
1656 self.in_z = FPOp(width)
1657 self.in_mid = Signal(self.id_wid, reset_less=True)
1658
1659 def setup(self, m, in_z, in_mid):
1660 m.d.comb += [self.in_z.eq(in_z),
1661 self.in_mid.eq(in_mid)]
1662
1663 def get_fragment(self, platform=None):
1664 """ creates the HDL code-fragment for FPAdd
1665 """
1666 m = Module()
1667 m.submodules.res_in_z = self.in_z
1668 m.submodules += self.res
1669
1670 return m
1671
1672 def ports(self):
1673 res = []
1674 for z in self.res:
1675 res += z.ports()
1676 return res
1677
1678
1679 class FPADD(FPID):
1680 """ FPADD: stages as follows:
1681
1682 FPGetOp (a)
1683 |
1684 FPGetOp (b)
1685 |
1686 FPAddBase---> FPAddBaseMod
1687 | |
1688 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1689
1690 FPAddBase is tricky: it is both a stage and *has* stages.
1691 Connection to FPAddBaseMod therefore requires an in stb/ack
1692 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1693 needs to be the thing that raises the incoming stb.
1694 """
1695
1696 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1697 """ IEEE754 FP Add
1698
1699 * width: bit-width of IEEE754. supported: 16, 32, 64
1700 * id_wid: an identifier that is sync-connected to the input
1701 * single_cycle: True indicates each stage to complete in 1 clock
1702 """
1703 self.width = width
1704 self.id_wid = id_wid
1705 self.single_cycle = single_cycle
1706
1707 #self.out_z = FPOp(width)
1708 self.ids = FPID(id_wid)
1709
1710 rs = []
1711 for i in range(rs_sz):
1712 in_a = FPOp(width)
1713 in_b = FPOp(width)
1714 in_a.name = "in_a_%d" % i
1715 in_b.name = "in_b_%d" % i
1716 rs.append((in_a, in_b))
1717 self.rs = Array(rs)
1718
1719 res = []
1720 for i in range(rs_sz):
1721 out_z = FPOp(width)
1722 out_z.name = "out_z_%d" % i
1723 res.append(out_z)
1724 self.res = Array(res)
1725
1726 self.states = []
1727
1728 def add_state(self, state):
1729 self.states.append(state)
1730 return state
1731
1732 def get_fragment(self, platform=None):
1733 """ creates the HDL code-fragment for FPAdd
1734 """
1735 m = Module()
1736 m.submodules += self.rs
1737
1738 in_a = self.rs[0][0]
1739 in_b = self.rs[0][1]
1740
1741 out_z = FPOp(self.width)
1742 out_mid = Signal(self.id_wid, reset_less=True)
1743 m.submodules.out_z = out_z
1744
1745 geta = self.add_state(FPGetOp("get_a", "get_b",
1746 in_a, self.width))
1747 geta.setup(m, in_a)
1748 a = geta.out_op
1749
1750 getb = self.add_state(FPGetOp("get_b", "fpadd",
1751 in_b, self.width))
1752 getb.setup(m, in_b)
1753 b = getb.out_op
1754
1755 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1756 ab = self.add_state(ab)
1757 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1758 out_z, out_mid)
1759
1760 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1761 out_mid, "get_a"))
1762
1763 with m.FSM() as fsm:
1764
1765 for state in self.states:
1766 with m.State(state.state_from):
1767 state.action(m)
1768
1769 return m
1770
1771
1772 if __name__ == "__main__":
1773 if True:
1774 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1775 main(alu, ports=alu.rs[0][0].ports() + \
1776 alu.rs[0][1].ports() + \
1777 alu.res[0].ports() + \
1778 [alu.ids.in_mid, alu.ids.out_mid])
1779 else:
1780 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1781 main(alu, ports=[alu.in_a, alu.in_b] + \
1782 alu.in_t.ports() + \
1783 alu.out_z.ports() + \
1784 [alu.in_mid, alu.out_mid])
1785
1786
1787 # works... but don't use, just do "python fname.py convert -t v"
1788 #print (verilog.convert(alu, ports=[
1789 # ports=alu.in_a.ports() + \
1790 # alu.in_b.ports() + \
1791 # alu.out_z.ports())