src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 #from fpbase import FPNumShiftMultiRight
  13
  14
  15 class FPState(FPBase):
  16     def __init__(self, state_from):
  17         self.state_from = state_from
  18
  19     def set_inputs(self, inputs):
  20         self.inputs = inputs
  21         for k,v in inputs.items():
  22             setattr(self, k, v)
  23
  24     def set_outputs(self, outputs):
  25         self.outputs = outputs
  26         for k,v in outputs.items():
  27             setattr(self, k, v)
  28
  29
  30 class FPGetSyncOpsMod:
  31     def __init__(self, width, num_ops=2):
  32         self.width = width
  33         self.num_ops = num_ops
  34         inops = []
  35         outops = []
  36         for i in range(num_ops):
  37             inops.append(Signal(width, reset_less=True))
  38             outops.append(Signal(width, reset_less=True))
  39         self.in_op = inops
  40         self.out_op = outops
  41         self.stb = Signal(num_ops)
  42         self.ack = Signal()
  43         self.ready = Signal(reset_less=True)
  44         self.out_decode = Signal(reset_less=True)
  45
  46     def elaborate(self, platform):
  47         m = Module()
  48         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  49         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  50         with m.If(self.out_decode):
  51             for i in range(self.num_ops):
  52                 m.d.comb += [
  53                         self.out_op[i].eq(self.in_op[i]),
  54                 ]
  55         return m
  56
  57     def ports(self):
  58         return self.in_op + self.out_op + [self.stb, self.ack]
  59
  60
  61 class FPOps(Trigger):
  62     def __init__(self, width, num_ops):
  63         Trigger.__init__(self)
  64         self.width = width
  65         self.num_ops = num_ops
  66
  67         res = []
  68         for i in range(num_ops):
  69             res.append(Signal(width))
  70         self.v  = Array(res)
  71
  72     def ports(self):
  73         res = []
  74         for i in range(self.num_ops):
  75             res.append(self.v[i])
  76         res.append(self.ack)
  77         res.append(self.stb)
  78         return res
  79
  80
  81 class InputGroup:
  82     def __init__(self, width, num_ops=2, num_rows=4):
  83         self.width = width
  84         self.num_ops = num_ops
  85         self.num_rows = num_rows
  86         self.mmax = int(log(self.num_rows) / log(2))
  87         self.rs = []
  88         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  89         for i in range(num_rows):
  90             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  91         self.rs = Array(self.rs)
  92
  93         self.out_op = FPOps(width, num_ops)
  94
  95     def elaborate(self, platform):
  96         m = Module()
  97
  98         pe = PriorityEncoder(self.num_rows)
  99         m.submodules.selector = pe
 100         m.submodules.out_op = self.out_op
 101         m.submodules += self.rs
 102
 103         # connect priority encoder
 104         in_ready = []
 105         for i in range(self.num_rows):
 106             in_ready.append(self.rs[i].ready)
 107         m.d.comb += pe.i.eq(Cat(*in_ready))
 108
 109         active = Signal(reset_less=True)
 110         out_en = Signal(reset_less=True)
 111         m.d.comb += active.eq(~pe.n) # encoder active
 112         m.d.comb += out_en.eq(active & self.out_op.trigger)
 113
 114         # encoder active: ack relevant input, record MID, pass output
 115         with m.If(out_en):
 116             rs = self.rs[pe.o]
 117             m.d.sync += self.mid.eq(pe.o)
 118             m.d.sync += rs.ack.eq(0)
 119             m.d.sync += self.out_op.stb.eq(0)
 120             for j in range(self.num_ops):
 121                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 122         with m.Else():
 123             m.d.sync += self.out_op.stb.eq(1)
 124             # acks all default to zero
 125             for i in range(self.num_rows):
 126                 m.d.sync += self.rs[i].ack.eq(1)
 127
 128         return m
 129
 130     def ports(self):
 131         res = []
 132         for i in range(self.num_rows):
 133             inop = self.rs[i]
 134             res += inop.in_op + [inop.stb]
 135         return self.out_op.ports() + res + [self.mid]
 136
 137
 138 class FPGetOpMod:
 139     def __init__(self, width):
 140         self.in_op = FPOp(width)
 141         self.out_op = Signal(width)
 142         self.out_decode = Signal(reset_less=True)
 143
 144     def elaborate(self, platform):
 145         m = Module()
 146         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 147         m.submodules.get_op_in = self.in_op
 148         #m.submodules.get_op_out = self.out_op
 149         with m.If(self.out_decode):
 150             m.d.comb += [
 151                 self.out_op.eq(self.in_op.v),
 152             ]
 153         return m
 154
 155
 156 class FPGetOp(FPState):
 157     """ gets operand
 158     """
 159
 160     def __init__(self, in_state, out_state, in_op, width):
 161         FPState.__init__(self, in_state)
 162         self.out_state = out_state
 163         self.mod = FPGetOpMod(width)
 164         self.in_op = in_op
 165         self.out_op = Signal(width)
 166         self.out_decode = Signal(reset_less=True)
 167
 168     def setup(self, m, in_op):
 169         """ links module to inputs and outputs
 170         """
 171         setattr(m.submodules, self.state_from, self.mod)
 172         m.d.comb += self.mod.in_op.eq(in_op)
 173         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 174
 175     def action(self, m):
 176         with m.If(self.out_decode):
 177             m.next = self.out_state
 178             m.d.sync += [
 179                 self.in_op.ack.eq(0),
 180                 self.out_op.eq(self.mod.out_op)
 181             ]
 182         with m.Else():
 183             m.d.sync += self.in_op.ack.eq(1)
 184
 185
 186 class FPGet2OpMod(Trigger):
 187     def __init__(self, width, id_wid):
 188         Trigger.__init__(self)
 189         self.width = width
 190         self.id_wid = id_wid
 191         self.i = self.ispec()
 192         self.o = self.ospec()
 193
 194     def ispec(self):
 195         return FPADDBaseData(self.width, self.id_wid)
 196
 197     def ospec(self):
 198         return FPNumBase2Ops(self.width, self.id_wid)
 199
 200     def elaborate(self, platform):
 201         m = Trigger.elaborate(self, platform)
 202         m.submodules.get_op1_out = self.o.a
 203         m.submodules.get_op2_out = self.o.b
 204         out_op1 = FPNumIn(None, self.width)
 205         out_op2 = FPNumIn(None, self.width)
 206         with m.If(self.trigger):
 207             m.d.comb += [
 208                 out_op1.decode(self.i.a),
 209                 out_op2.decode(self.i.b),
 210                 self.o.a.eq(out_op1),
 211                 self.o.b.eq(out_op2),
 212             ]
 213         return m
 214
 215
 216 class FPGet2Op(FPState):
 217     """ gets operands
 218     """
 219
 220     def __init__(self, in_state, out_state, width, id_wid):
 221         FPState.__init__(self, in_state)
 222         self.out_state = out_state
 223         self.mod = FPGet2OpMod(width, id_wid)
 224         self.o = self.mod.ospec()
 225         self.in_stb = Signal(reset_less=True)
 226         self.out_ack = Signal(reset_less=True)
 227         self.out_decode = Signal(reset_less=True)
 228
 229     def setup(self, m, i, in_stb, in_ack):
 230         """ links module to inputs and outputs
 231         """
 232         m.submodules.get_ops = self.mod
 233         m.d.comb += self.mod.i.eq(i)
 234         m.d.comb += self.mod.stb.eq(in_stb)
 235         m.d.comb += self.out_ack.eq(self.mod.ack)
 236         m.d.comb += self.out_decode.eq(self.mod.trigger)
 237         m.d.comb += in_ack.eq(self.mod.ack)
 238
 239     def action(self, m):
 240         with m.If(self.out_decode):
 241             m.next = self.out_state
 242             m.d.sync += [
 243                 self.mod.ack.eq(0),
 244                 self.o.eq(self.mod.o),
 245             ]
 246         with m.Else():
 247             m.d.sync += self.mod.ack.eq(1)
 248
 249
 250 class FPNumBase2Ops:
 251
 252     def __init__(self, width, id_wid, m_extra=True):
 253         self.a = FPNumBase(width, m_extra)
 254         self.b = FPNumBase(width, m_extra)
 255         self.mid = Signal(id_wid, reset_less=True)
 256
 257     def eq(self, i):
 258         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 259
 260
 261 class FPAddSpecialCasesMod:
 262     """ special cases: NaNs, infs, zeros, denormalised
 263         NOTE: some of these are unique to add.  see "Special Operations"
 264         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 265     """
 266
 267     def __init__(self, width, id_wid):
 268         self.width = width
 269         self.id_wid = id_wid
 270         self.i = self.ispec()
 271         self.o = self.ospec()
 272         self.out_do_z = Signal(reset_less=True)
 273
 274     def ispec(self):
 275         return FPNumBase2Ops(self.width, self.id_wid)
 276
 277     def ospec(self):
 278         return FPPackData(self.width, self.id_wid)
 279
 280     def setup(self, m, i, out_do_z):
 281         """ links module to inputs and outputs
 282         """
 283         m.submodules.specialcases = self
 284         m.d.comb += self.i.eq(i)
 285         m.d.comb += out_do_z.eq(self.out_do_z)
 286
 287     def elaborate(self, platform):
 288         m = Module()
 289
 290         m.submodules.sc_in_a = self.i.a
 291         m.submodules.sc_in_b = self.i.b
 292         m.submodules.sc_out_z = self.o.z
 293
 294         s_nomatch = Signal()
 295         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 296
 297         m_match = Signal()
 298         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 299
 300         # if a is NaN or b is NaN return NaN
 301         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 302             m.d.comb += self.out_do_z.eq(1)
 303             m.d.comb += self.o.z.nan(0)
 304
 305         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 306         # under review
 307
 308         ## if a is zero and b is NaN return -b
 309         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 310         #    m.d.comb += self.out_do_z.eq(1)
 311         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 312
 313         ## if b is zero and a is NaN return -a
 314         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 315         #    m.d.comb += self.out_do_z.eq(1)
 316         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 317
 318         ## if a is -zero and b is NaN return -b
 319         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 320         #    m.d.comb += self.out_do_z.eq(1)
 321         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 322
 323         ## if b is -zero and a is NaN return -a
 324         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 325         #    m.d.comb += self.out_do_z.eq(1)
 326         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 327
 328         # if a is inf return inf (or NaN)
 329         with m.Elif(self.i.a.is_inf):
 330             m.d.comb += self.out_do_z.eq(1)
 331             m.d.comb += self.o.z.inf(self.i.a.s)
 332             # if a is inf and signs don't match return NaN
 333             with m.If(self.i.b.exp_128 & s_nomatch):
 334                 m.d.comb += self.o.z.nan(0)
 335
 336         # if b is inf return inf
 337         with m.Elif(self.i.b.is_inf):
 338             m.d.comb += self.out_do_z.eq(1)
 339             m.d.comb += self.o.z.inf(self.i.b.s)
 340
 341         # if a is zero and b zero return signed-a/b
 342         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 343             m.d.comb += self.out_do_z.eq(1)
 344             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 345                                           self.i.b.e,
 346                                           self.i.b.m[3:-1])
 347
 348         # if a is zero return b
 349         with m.Elif(self.i.a.is_zero):
 350             m.d.comb += self.out_do_z.eq(1)
 351             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 352                                       self.i.b.m[3:-1])
 353
 354         # if b is zero return a
 355         with m.Elif(self.i.b.is_zero):
 356             m.d.comb += self.out_do_z.eq(1)
 357             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 358                                       self.i.a.m[3:-1])
 359
 360         # if a equal to -b return zero (+ve zero)
 361         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 362             m.d.comb += self.out_do_z.eq(1)
 363             m.d.comb += self.o.z.zero(0)
 364
 365         # Denormalised Number checks
 366         with m.Else():
 367             m.d.comb += self.out_do_z.eq(0)
 368
 369         return m
 370
 371
 372 class FPID:
 373     def __init__(self, id_wid):
 374         self.id_wid = id_wid
 375         if self.id_wid:
 376             self.in_mid = Signal(id_wid, reset_less=True)
 377             self.out_mid = Signal(id_wid, reset_less=True)
 378         else:
 379             self.in_mid = None
 380             self.out_mid = None
 381
 382     def idsync(self, m):
 383         if self.id_wid is not None:
 384             m.d.sync += self.out_mid.eq(self.in_mid)
 385
 386
 387 class FPAddSpecialCases(FPState, FPID):
 388     """ special cases: NaNs, infs, zeros, denormalised
 389         NOTE: some of these are unique to add.  see "Special Operations"
 390         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 391     """
 392
 393     def __init__(self, width, id_wid):
 394         FPState.__init__(self, "special_cases")
 395         FPID.__init__(self, id_wid)
 396         self.mod = FPAddSpecialCasesMod(width)
 397         self.out_z = self.mod.ospec()
 398         self.out_do_z = Signal(reset_less=True)
 399
 400     def setup(self, m, in_a, in_b, in_mid):
 401         """ links module to inputs and outputs
 402         """
 403         self.mod.setup(m, in_a, in_b, self.out_do_z)
 404         if self.in_mid is not None:
 405             m.d.comb += self.in_mid.eq(in_mid)
 406
 407     def action(self, m):
 408         self.idsync(m)
 409         with m.If(self.out_do_z):
 410             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 411             m.next = "put_z"
 412         with m.Else():
 413             m.next = "denormalise"
 414
 415
 416 class FPAddSpecialCasesDeNorm(FPState, FPID):
 417     """ special cases: NaNs, infs, zeros, denormalised
 418         NOTE: some of these are unique to add.  see "Special Operations"
 419         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 420     """
 421
 422     def __init__(self, width, id_wid):
 423         FPState.__init__(self, "special_cases")
 424         FPID.__init__(self, id_wid)
 425         self.smod = FPAddSpecialCasesMod(width, id_wid)
 426         self.out_z = self.smod.ospec()
 427         self.out_do_z = Signal(reset_less=True)
 428
 429         self.dmod = FPAddDeNormMod(width, id_wid)
 430         self.o = self.dmod.ospec()
 431
 432     def setup(self, m, i, in_mid):
 433         """ links module to inputs and outputs
 434         """
 435         self.smod.setup(m, i, self.out_do_z)
 436         self.dmod.setup(m, i)
 437         if self.in_mid is not None:
 438             m.d.comb += self.in_mid.eq(in_mid)
 439
 440     def action(self, m):
 441         self.idsync(m)
 442         with m.If(self.out_do_z):
 443             m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 444             m.next = "put_z"
 445         with m.Else():
 446             m.next = "align"
 447             m.d.sync += self.o.a.eq(self.dmod.o.a)
 448             m.d.sync += self.o.b.eq(self.dmod.o.b)
 449
 450
 451 class FPAddDeNormMod(FPState):
 452
 453     def __init__(self, width, id_wid):
 454         self.width = width
 455         self.id_wid = id_wid
 456         self.i = self.ispec()
 457         self.o = self.ospec()
 458
 459     def ispec(self):
 460         return FPNumBase2Ops(self.width, self.id_wid)
 461
 462     def ospec(self):
 463         return FPNumBase2Ops(self.width, self.id_wid)
 464
 465     def setup(self, m, i):
 466         """ links module to inputs and outputs
 467         """
 468         m.submodules.denormalise = self
 469         m.d.comb += self.i.eq(i)
 470
 471     def elaborate(self, platform):
 472         m = Module()
 473         m.submodules.denorm_in_a = self.i.a
 474         m.submodules.denorm_in_b = self.i.b
 475         m.submodules.denorm_out_a = self.o.a
 476         m.submodules.denorm_out_b = self.o.b
 477         # hmmm, don't like repeating identical code
 478         m.d.comb += self.o.a.eq(self.i.a)
 479         with m.If(self.i.a.exp_n127):
 480             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 481         with m.Else():
 482             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 483
 484         m.d.comb += self.o.b.eq(self.i.b)
 485         with m.If(self.i.b.exp_n127):
 486             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 487         with m.Else():
 488             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 489
 490         return m
 491
 492
 493 class FPAddDeNorm(FPState, FPID):
 494
 495     def __init__(self, width, id_wid):
 496         FPState.__init__(self, "denormalise")
 497         FPID.__init__(self, id_wid)
 498         self.mod = FPAddDeNormMod(width)
 499         self.out_a = FPNumBase(width)
 500         self.out_b = FPNumBase(width)
 501
 502     def setup(self, m, in_a, in_b, in_mid):
 503         """ links module to inputs and outputs
 504         """
 505         self.mod.setup(m, in_a, in_b)
 506         if self.in_mid is not None:
 507             m.d.comb += self.in_mid.eq(in_mid)
 508
 509     def action(self, m):
 510         self.idsync(m)
 511         # Denormalised Number checks
 512         m.next = "align"
 513         m.d.sync += self.out_a.eq(self.mod.out_a)
 514         m.d.sync += self.out_b.eq(self.mod.out_b)
 515
 516
 517 class FPAddAlignMultiMod(FPState):
 518
 519     def __init__(self, width):
 520         self.in_a = FPNumBase(width)
 521         self.in_b = FPNumBase(width)
 522         self.out_a = FPNumIn(None, width)
 523         self.out_b = FPNumIn(None, width)
 524         self.exp_eq = Signal(reset_less=True)
 525
 526     def elaborate(self, platform):
 527         # This one however (single-cycle) will do the shift
 528         # in one go.
 529
 530         m = Module()
 531
 532         m.submodules.align_in_a = self.in_a
 533         m.submodules.align_in_b = self.in_b
 534         m.submodules.align_out_a = self.out_a
 535         m.submodules.align_out_b = self.out_b
 536
 537         # NOTE: this does *not* do single-cycle multi-shifting,
 538         #       it *STAYS* in the align state until exponents match
 539
 540         # exponent of a greater than b: shift b down
 541         m.d.comb += self.exp_eq.eq(0)
 542         m.d.comb += self.out_a.eq(self.in_a)
 543         m.d.comb += self.out_b.eq(self.in_b)
 544         agtb = Signal(reset_less=True)
 545         altb = Signal(reset_less=True)
 546         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 547         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 548         with m.If(agtb):
 549             m.d.comb += self.out_b.shift_down(self.in_b)
 550         # exponent of b greater than a: shift a down
 551         with m.Elif(altb):
 552             m.d.comb += self.out_a.shift_down(self.in_a)
 553         # exponents equal: move to next stage.
 554         with m.Else():
 555             m.d.comb += self.exp_eq.eq(1)
 556         return m
 557
 558
 559 class FPAddAlignMulti(FPState, FPID):
 560
 561     def __init__(self, width, id_wid):
 562         FPID.__init__(self, id_wid)
 563         FPState.__init__(self, "align")
 564         self.mod = FPAddAlignMultiMod(width)
 565         self.out_a = FPNumIn(None, width)
 566         self.out_b = FPNumIn(None, width)
 567         self.exp_eq = Signal(reset_less=True)
 568
 569     def setup(self, m, in_a, in_b, in_mid):
 570         """ links module to inputs and outputs
 571         """
 572         m.submodules.align = self.mod
 573         m.d.comb += self.mod.in_a.eq(in_a)
 574         m.d.comb += self.mod.in_b.eq(in_b)
 575         #m.d.comb += self.out_a.eq(self.mod.out_a)
 576         #m.d.comb += self.out_b.eq(self.mod.out_b)
 577         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 578         if self.in_mid is not None:
 579             m.d.comb += self.in_mid.eq(in_mid)
 580
 581     def action(self, m):
 582         self.idsync(m)
 583         m.d.sync += self.out_a.eq(self.mod.out_a)
 584         m.d.sync += self.out_b.eq(self.mod.out_b)
 585         with m.If(self.exp_eq):
 586             m.next = "add_0"
 587
 588
 589 class FPNumIn2Ops:
 590
 591     def __init__(self, width, id_wid):
 592         self.a = FPNumIn(None, width)
 593         self.b = FPNumIn(None, width)
 594         self.mid = Signal(id_wid, reset_less=True)
 595
 596     def eq(self, i):
 597         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 598
 599
 600 class FPAddAlignSingleMod:
 601
 602     def __init__(self, width, id_wid):
 603         self.width = width
 604         self.id_wid = id_wid
 605         self.i = self.ispec()
 606         self.o = self.ospec()
 607
 608     def ispec(self):
 609         return FPNumBase2Ops(self.width, self.id_wid)
 610
 611     def ospec(self):
 612         return FPNumIn2Ops(self.width, self.id_wid)
 613
 614     def setup(self, m, i):
 615         """ links module to inputs and outputs
 616         """
 617         m.submodules.align = self
 618         m.d.comb += self.i.eq(i)
 619
 620     def elaborate(self, platform):
 621         """ Aligns A against B or B against A, depending on which has the
 622             greater exponent.  This is done in a *single* cycle using
 623             variable-width bit-shift
 624
 625             the shifter used here is quite expensive in terms of gates.
 626             Mux A or B in (and out) into temporaries, as only one of them
 627             needs to be aligned against the other
 628         """
 629         m = Module()
 630
 631         m.submodules.align_in_a = self.i.a
 632         m.submodules.align_in_b = self.i.b
 633         m.submodules.align_out_a = self.o.a
 634         m.submodules.align_out_b = self.o.b
 635
 636         # temporary (muxed) input and output to be shifted
 637         t_inp = FPNumBase(self.width)
 638         t_out = FPNumIn(None, self.width)
 639         espec = (len(self.i.a.e), True)
 640         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 641         m.submodules.align_t_in = t_inp
 642         m.submodules.align_t_out = t_out
 643         m.submodules.multishift_r = msr
 644
 645         ediff = Signal(espec, reset_less=True)
 646         ediffr = Signal(espec, reset_less=True)
 647         tdiff = Signal(espec, reset_less=True)
 648         elz = Signal(reset_less=True)
 649         egz = Signal(reset_less=True)
 650
 651         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 652         m.d.comb += msr.inp.eq(t_inp.m)
 653         m.d.comb += msr.diff.eq(tdiff)
 654         m.d.comb += t_out.m.eq(msr.m)
 655         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 656         m.d.comb += t_out.s.eq(t_inp.s)
 657
 658         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 659         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 660         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 661         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 662
 663         # default: A-exp == B-exp, A and B untouched (fall through)
 664         m.d.comb += self.o.a.eq(self.i.a)
 665         m.d.comb += self.o.b.eq(self.i.b)
 666         # only one shifter (muxed)
 667         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 668         # exponent of a greater than b: shift b down
 669         with m.If(egz):
 670             m.d.comb += [t_inp.eq(self.i.b),
 671                          tdiff.eq(ediff),
 672                          self.o.b.eq(t_out),
 673                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 674                         ]
 675         # exponent of b greater than a: shift a down
 676         with m.Elif(elz):
 677             m.d.comb += [t_inp.eq(self.i.a),
 678                          tdiff.eq(ediffr),
 679                          self.o.a.eq(t_out),
 680                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 681                         ]
 682         return m
 683
 684
 685 class FPAddAlignSingle(FPState, FPID):
 686
 687     def __init__(self, width, id_wid):
 688         FPState.__init__(self, "align")
 689         FPID.__init__(self, id_wid)
 690         self.mod = FPAddAlignSingleMod(width, id_wid)
 691         self.out_a = FPNumIn(None, width)
 692         self.out_b = FPNumIn(None, width)
 693
 694     def setup(self, m, in_a, in_b, in_mid):
 695         """ links module to inputs and outputs
 696         """
 697         self.mod.setup(m, in_a, in_b)
 698         if self.in_mid is not None:
 699             m.d.comb += self.in_mid.eq(in_mid)
 700
 701     def action(self, m):
 702         self.idsync(m)
 703         # NOTE: could be done as comb
 704         m.d.sync += self.out_a.eq(self.mod.out_a)
 705         m.d.sync += self.out_b.eq(self.mod.out_b)
 706         m.next = "add_0"
 707
 708
 709 class FPAddAlignSingleAdd(FPState, FPID):
 710
 711     def __init__(self, width, id_wid):
 712         FPState.__init__(self, "align")
 713         FPID.__init__(self, id_wid)
 714         self.width = width
 715         self.id_wid = id_wid
 716         self.a1o = self.ospec()
 717
 718     def ispec(self):
 719         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 720
 721     def ospec(self):
 722         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 723
 724     def setup(self, m, i, in_mid):
 725         """ links module to inputs and outputs
 726         """
 727         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 728         mod.setup(m, i)
 729         o = mod.ospec()
 730         m.d.comb += o.eq(mod.o)
 731
 732         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 733         a0mod.setup(m, o)
 734         a0o = a0mod.ospec()
 735         m.d.comb += a0o.eq(a0mod.o)
 736
 737         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 738         a1mod.setup(m, a0o)
 739         self.a1modo = a1mod.o
 740
 741         if self.in_mid is not None:
 742             m.d.comb += self.in_mid.eq(in_mid)
 743
 744         m.d.sync += self.a1o.eq(self.a1modo)
 745         self.idsync(m)
 746
 747     def action(self, m):
 748         m.next = "normalise_1"
 749
 750
 751 class FPAddStage0Data:
 752
 753     def __init__(self, width, id_wid):
 754         self.z = FPNumBase(width, False)
 755         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 756         self.mid = Signal(id_wid, reset_less=True)
 757
 758     def eq(self, i):
 759         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 760
 761
 762 class FPAddStage0Mod:
 763
 764     def __init__(self, width, id_wid):
 765         self.width = width
 766         self.id_wid = id_wid
 767         self.i = self.ispec()
 768         self.o = self.ospec()
 769
 770     def ispec(self):
 771         return FPNumBase2Ops(self.width, self.id_wid)
 772
 773     def ospec(self):
 774         return FPAddStage0Data(self.width, self.id_wid)
 775
 776     def setup(self, m, i):
 777         """ links module to inputs and outputs
 778         """
 779         m.submodules.add0 = self
 780         m.d.comb += self.i.eq(i)
 781
 782     def elaborate(self, platform):
 783         m = Module()
 784         m.submodules.add0_in_a = self.i.a
 785         m.submodules.add0_in_b = self.i.b
 786         m.submodules.add0_out_z = self.o.z
 787
 788         m.d.comb += self.o.z.e.eq(self.i.a.e)
 789
 790         # store intermediate tests (and zero-extended mantissas)
 791         seq = Signal(reset_less=True)
 792         mge = Signal(reset_less=True)
 793         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 794         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 795         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 796                      mge.eq(self.i.a.m >= self.i.b.m),
 797                      am0.eq(Cat(self.i.a.m, 0)),
 798                      bm0.eq(Cat(self.i.b.m, 0))
 799                     ]
 800         # same-sign (both negative or both positive) add mantissas
 801         with m.If(seq):
 802             m.d.comb += [
 803                 self.o.tot.eq(am0 + bm0),
 804                 self.o.z.s.eq(self.i.a.s)
 805             ]
 806         # a mantissa greater than b, use a
 807         with m.Elif(mge):
 808             m.d.comb += [
 809                 self.o.tot.eq(am0 - bm0),
 810                 self.o.z.s.eq(self.i.a.s)
 811             ]
 812         # b mantissa greater than a, use b
 813         with m.Else():
 814             m.d.comb += [
 815                 self.o.tot.eq(bm0 - am0),
 816                 self.o.z.s.eq(self.i.b.s)
 817         ]
 818         return m
 819
 820
 821 class FPAddStage0(FPState, FPID):
 822     """ First stage of add.  covers same-sign (add) and subtract
 823         special-casing when mantissas are greater or equal, to
 824         give greatest accuracy.
 825     """
 826
 827     def __init__(self, width, id_wid):
 828         FPState.__init__(self, "add_0")
 829         FPID.__init__(self, id_wid)
 830         self.mod = FPAddStage0Mod(width)
 831         self.o = self.mod.ospec()
 832
 833     def setup(self, m, i, in_mid):
 834         """ links module to inputs and outputs
 835         """
 836         self.mod.setup(m, i)
 837         if self.in_mid is not None:
 838             m.d.comb += self.in_mid.eq(in_mid)
 839
 840         self.idsync(m)
 841         # NOTE: these could be done as combinatorial (merge add0+add1)
 842         m.d.sync += self.o.eq(self.mod.o)
 843
 844     def action(self, m):
 845         m.next = "add_1"
 846
 847
 848 class FPAddStage1Data:
 849
 850     def __init__(self, width, id_wid):
 851         self.z = FPNumBase(width, False)
 852         self.of = Overflow()
 853         self.mid = Signal(id_wid, reset_less=True)
 854
 855     def eq(self, i):
 856         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 857
 858
 859
 860 class FPAddStage1Mod(FPState):
 861     """ Second stage of add: preparation for normalisation.
 862         detects when tot sum is too big (tot[27] is kinda a carry bit)
 863     """
 864
 865     def __init__(self, width, id_wid):
 866         self.width = width
 867         self.id_wid = id_wid
 868         self.i = self.ispec()
 869         self.o = self.ospec()
 870
 871     def ispec(self):
 872         return FPAddStage0Data(self.width, self.id_wid)
 873
 874     def ospec(self):
 875         return FPAddStage1Data(self.width, self.id_wid)
 876
 877     def setup(self, m, i):
 878         """ links module to inputs and outputs
 879         """
 880         m.submodules.add1 = self
 881         m.submodules.add1_out_overflow = self.o.of
 882
 883         m.d.comb += self.i.eq(i)
 884
 885     def elaborate(self, platform):
 886         m = Module()
 887         #m.submodules.norm1_in_overflow = self.in_of
 888         #m.submodules.norm1_out_overflow = self.out_of
 889         #m.submodules.norm1_in_z = self.in_z
 890         #m.submodules.norm1_out_z = self.out_z
 891         m.d.comb += self.o.z.eq(self.i.z)
 892         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 893         with m.If(self.i.tot[-1]):
 894             m.d.comb += [
 895                 self.o.z.m.eq(self.i.tot[4:]),
 896                 self.o.of.m0.eq(self.i.tot[4]),
 897                 self.o.of.guard.eq(self.i.tot[3]),
 898                 self.o.of.round_bit.eq(self.i.tot[2]),
 899                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 900                 self.o.z.e.eq(self.i.z.e + 1)
 901         ]
 902         # tot[-1] (MSB) zero case
 903         with m.Else():
 904             m.d.comb += [
 905                 self.o.z.m.eq(self.i.tot[3:]),
 906                 self.o.of.m0.eq(self.i.tot[3]),
 907                 self.o.of.guard.eq(self.i.tot[2]),
 908                 self.o.of.round_bit.eq(self.i.tot[1]),
 909                 self.o.of.sticky.eq(self.i.tot[0])
 910         ]
 911         return m
 912
 913
 914 class FPAddStage1(FPState, FPID):
 915
 916     def __init__(self, width, id_wid):
 917         FPState.__init__(self, "add_1")
 918         FPID.__init__(self, id_wid)
 919         self.mod = FPAddStage1Mod(width)
 920         self.out_z = FPNumBase(width, False)
 921         self.out_of = Overflow()
 922         self.norm_stb = Signal()
 923
 924     def setup(self, m, i, in_mid):
 925         """ links module to inputs and outputs
 926         """
 927         self.mod.setup(m, i)
 928
 929         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 930
 931         if self.in_mid is not None:
 932             m.d.comb += self.in_mid.eq(in_mid)
 933
 934         self.idsync(m)
 935         m.d.sync += self.out_of.eq(self.mod.out_of)
 936         m.d.sync += self.out_z.eq(self.mod.out_z)
 937         m.d.sync += self.norm_stb.eq(1)
 938
 939     def action(self, m):
 940         m.next = "normalise_1"
 941
 942
 943 class FPNormaliseModSingle:
 944
 945     def __init__(self, width):
 946         self.width = width
 947         self.in_z = self.ispec()
 948         self.out_z = self.ospec()
 949
 950     def ispec(self):
 951         return FPNumBase(self.width, False)
 952
 953     def ospec(self):
 954         return FPNumBase(self.width, False)
 955
 956     def setup(self, m, i):
 957         """ links module to inputs and outputs
 958         """
 959         m.submodules.normalise = self
 960         m.d.comb += self.i.eq(i)
 961
 962     def elaborate(self, platform):
 963         m = Module()
 964
 965         mwid = self.out_z.m_width+2
 966         pe = PriorityEncoder(mwid)
 967         m.submodules.norm_pe = pe
 968
 969         m.submodules.norm1_out_z = self.out_z
 970         m.submodules.norm1_in_z = self.in_z
 971
 972         in_z = FPNumBase(self.width, False)
 973         in_of = Overflow()
 974         m.submodules.norm1_insel_z = in_z
 975         m.submodules.norm1_insel_overflow = in_of
 976
 977         espec = (len(in_z.e), True)
 978         ediff_n126 = Signal(espec, reset_less=True)
 979         msr = MultiShiftRMerge(mwid, espec)
 980         m.submodules.multishift_r = msr
 981
 982         m.d.comb += in_z.eq(self.in_z)
 983         m.d.comb += in_of.eq(self.in_of)
 984         # initialise out from in (overridden below)
 985         m.d.comb += self.out_z.eq(in_z)
 986         m.d.comb += self.out_of.eq(in_of)
 987         # normalisation decrease condition
 988         decrease = Signal(reset_less=True)
 989         m.d.comb += decrease.eq(in_z.m_msbzero)
 990         # decrease exponent
 991         with m.If(decrease):
 992             # *sigh* not entirely obvious: count leading zeros (clz)
 993             # with a PriorityEncoder: to find from the MSB
 994             # we reverse the order of the bits.
 995             temp_m = Signal(mwid, reset_less=True)
 996             temp_s = Signal(mwid+1, reset_less=True)
 997             clz = Signal((len(in_z.e), True), reset_less=True)
 998             m.d.comb += [
 999                 # cat round and guard bits back into the mantissa
1000                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1001                 pe.i.eq(temp_m[::-1]),          # inverted
1002                 clz.eq(pe.o),                   # count zeros from MSB down
1003                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1004                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1005                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1006             ]
1007
1008         return m
1009
1010 class FPNorm1Data:
1011
1012     def __init__(self, width, id_wid):
1013         self.roundz = Signal(reset_less=True)
1014         self.z = FPNumBase(width, False)
1015         self.mid = Signal(id_wid, reset_less=True)
1016
1017     def eq(self, i):
1018         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1019
1020
1021 class FPNorm1ModSingle:
1022
1023     def __init__(self, width, id_wid):
1024         self.width = width
1025         self.id_wid = id_wid
1026         self.i = self.ispec()
1027         self.o = self.ospec()
1028
1029     def ispec(self):
1030         return FPAddStage1Data(self.width, self.id_wid)
1031
1032     def ospec(self):
1033         return FPNorm1Data(self.width, self.id_wid)
1034
1035     def setup(self, m, i):
1036         """ links module to inputs and outputs
1037         """
1038         m.submodules.normalise_1 = self
1039         m.d.comb += self.i.eq(i)
1040
1041     def elaborate(self, platform):
1042         m = Module()
1043
1044         mwid = self.o.z.m_width+2
1045         pe = PriorityEncoder(mwid)
1046         m.submodules.norm_pe = pe
1047
1048         of = Overflow()
1049         m.d.comb += self.o.roundz.eq(of.roundz)
1050
1051         m.submodules.norm1_out_z = self.o.z
1052         m.submodules.norm1_out_overflow = of
1053         m.submodules.norm1_in_z = self.i.z
1054         m.submodules.norm1_in_overflow = self.i.of
1055
1056         i = self.ispec()
1057         m.submodules.norm1_insel_z = i.z
1058         m.submodules.norm1_insel_overflow = i.of
1059
1060         espec = (len(i.z.e), True)
1061         ediff_n126 = Signal(espec, reset_less=True)
1062         msr = MultiShiftRMerge(mwid, espec)
1063         m.submodules.multishift_r = msr
1064
1065         m.d.comb += i.eq(self.i)
1066         # initialise out from in (overridden below)
1067         m.d.comb += self.o.z.eq(i.z)
1068         m.d.comb += of.eq(i.of)
1069         # normalisation increase/decrease conditions
1070         decrease = Signal(reset_less=True)
1071         increase = Signal(reset_less=True)
1072         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1073         m.d.comb += increase.eq(i.z.exp_lt_n126)
1074         # decrease exponent
1075         with m.If(decrease):
1076             # *sigh* not entirely obvious: count leading zeros (clz)
1077             # with a PriorityEncoder: to find from the MSB
1078             # we reverse the order of the bits.
1079             temp_m = Signal(mwid, reset_less=True)
1080             temp_s = Signal(mwid+1, reset_less=True)
1081             clz = Signal((len(i.z.e), True), reset_less=True)
1082             # make sure that the amount to decrease by does NOT
1083             # go below the minimum non-INF/NaN exponent
1084             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1085                          i.z.exp_sub_n126)
1086             m.d.comb += [
1087                 # cat round and guard bits back into the mantissa
1088                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1089                 pe.i.eq(temp_m[::-1]),          # inverted
1090                 clz.eq(limclz),                 # count zeros from MSB down
1091                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1092                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1093                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1094                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1095                 # overflow in bits 0..1: got shifted too (leave sticky)
1096                 of.guard.eq(temp_s[1]),       # guard
1097                 of.round_bit.eq(temp_s[0]),   # round
1098             ]
1099         # increase exponent
1100         with m.Elif(increase):
1101             temp_m = Signal(mwid+1, reset_less=True)
1102             m.d.comb += [
1103                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1104                               i.z.m)),
1105                 ediff_n126.eq(i.z.N126 - i.z.e),
1106                 # connect multi-shifter to inp/out mantissa (and ediff)
1107                 msr.inp.eq(temp_m),
1108                 msr.diff.eq(ediff_n126),
1109                 self.o.z.m.eq(msr.m[3:]),
1110                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1111                 # overflow in bits 0..1: got shifted too (leave sticky)
1112                 of.guard.eq(temp_s[2]),     # guard
1113                 of.round_bit.eq(temp_s[1]), # round
1114                 of.sticky.eq(temp_s[0]),    # sticky
1115                 self.o.z.e.eq(i.z.e + ediff_n126),
1116             ]
1117
1118         return m
1119
1120
1121 class FPNorm1ModMulti:
1122
1123     def __init__(self, width, single_cycle=True):
1124         self.width = width
1125         self.in_select = Signal(reset_less=True)
1126         self.in_z = FPNumBase(width, False)
1127         self.in_of = Overflow()
1128         self.temp_z = FPNumBase(width, False)
1129         self.temp_of = Overflow()
1130         self.out_z = FPNumBase(width, False)
1131         self.out_of = Overflow()
1132
1133     def elaborate(self, platform):
1134         m = Module()
1135
1136         m.submodules.norm1_out_z = self.out_z
1137         m.submodules.norm1_out_overflow = self.out_of
1138         m.submodules.norm1_temp_z = self.temp_z
1139         m.submodules.norm1_temp_of = self.temp_of
1140         m.submodules.norm1_in_z = self.in_z
1141         m.submodules.norm1_in_overflow = self.in_of
1142
1143         in_z = FPNumBase(self.width, False)
1144         in_of = Overflow()
1145         m.submodules.norm1_insel_z = in_z
1146         m.submodules.norm1_insel_overflow = in_of
1147
1148         # select which of temp or in z/of to use
1149         with m.If(self.in_select):
1150             m.d.comb += in_z.eq(self.in_z)
1151             m.d.comb += in_of.eq(self.in_of)
1152         with m.Else():
1153             m.d.comb += in_z.eq(self.temp_z)
1154             m.d.comb += in_of.eq(self.temp_of)
1155         # initialise out from in (overridden below)
1156         m.d.comb += self.out_z.eq(in_z)
1157         m.d.comb += self.out_of.eq(in_of)
1158         # normalisation increase/decrease conditions
1159         decrease = Signal(reset_less=True)
1160         increase = Signal(reset_less=True)
1161         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1162         m.d.comb += increase.eq(in_z.exp_lt_n126)
1163         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1164         # decrease exponent
1165         with m.If(decrease):
1166             m.d.comb += [
1167                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1168                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1169                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1170                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1171                 self.out_of.round_bit.eq(0),        # reset round bit
1172                 self.out_of.m0.eq(in_of.guard),
1173             ]
1174         # increase exponent
1175         with m.Elif(increase):
1176             m.d.comb += [
1177                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1178                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1179                 self.out_of.guard.eq(in_z.m[0]),
1180                 self.out_of.m0.eq(in_z.m[1]),
1181                 self.out_of.round_bit.eq(in_of.guard),
1182                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1183             ]
1184
1185         return m
1186
1187
1188 class FPNorm1Single(FPState, FPID):
1189
1190     def __init__(self, width, id_wid, single_cycle=True):
1191         FPID.__init__(self, id_wid)
1192         FPState.__init__(self, "normalise_1")
1193         self.mod = FPNorm1ModSingle(width)
1194         self.out_z = FPNumBase(width, False)
1195         self.out_roundz = Signal(reset_less=True)
1196
1197     def setup(self, m, i, in_mid):
1198         """ links module to inputs and outputs
1199         """
1200         self.mod.setup(m, i, self.out_z)
1201
1202         if self.in_mid is not None:
1203             m.d.comb += self.in_mid.eq(in_mid)
1204
1205         self.idsync(m)
1206         m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1207
1208     def action(self, m):
1209         m.next = "round"
1210
1211
1212 class FPNorm1Multi(FPState, FPID):
1213
1214     def __init__(self, width, id_wid):
1215         FPID.__init__(self, id_wid)
1216         FPState.__init__(self, "normalise_1")
1217         self.mod = FPNorm1ModMulti(width)
1218         self.stb = Signal(reset_less=True)
1219         self.ack = Signal(reset=0, reset_less=True)
1220         self.out_norm = Signal(reset_less=True)
1221         self.in_accept = Signal(reset_less=True)
1222         self.temp_z = FPNumBase(width)
1223         self.temp_of = Overflow()
1224         self.out_z = FPNumBase(width)
1225         self.out_roundz = Signal(reset_less=True)
1226
1227     def setup(self, m, in_z, in_of, norm_stb, in_mid):
1228         """ links module to inputs and outputs
1229         """
1230         self.mod.setup(m, in_z, in_of, norm_stb,
1231                        self.in_accept, self.temp_z, self.temp_of,
1232                        self.out_z, self.out_norm)
1233
1234         m.d.comb += self.stb.eq(norm_stb)
1235         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1236
1237         if self.in_mid is not None:
1238             m.d.comb += self.in_mid.eq(in_mid)
1239
1240     def action(self, m):
1241         self.idsync(m)
1242         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1243         m.d.sync += self.temp_of.eq(self.mod.out_of)
1244         m.d.sync += self.temp_z.eq(self.out_z)
1245         with m.If(self.out_norm):
1246             with m.If(self.in_accept):
1247                 m.d.sync += [
1248                     self.ack.eq(1),
1249                 ]
1250             with m.Else():
1251                 m.d.sync += self.ack.eq(0)
1252         with m.Else():
1253             # normalisation not required (or done).
1254             m.next = "round"
1255             m.d.sync += self.ack.eq(1)
1256             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1257
1258
1259 class FPNormToPack(FPState, FPID):
1260
1261     def __init__(self, width, id_wid):
1262         FPID.__init__(self, id_wid)
1263         FPState.__init__(self, "normalise_1")
1264         self.id_wid = id_wid
1265         self.width = width
1266
1267     def ispec(self):
1268         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1269
1270     def ospec(self):
1271         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1272
1273     def setup(self, m, i, in_mid):
1274         """ links module to inputs and outputs
1275         """
1276
1277         # Normalisation (chained to input in_z+in_of)
1278         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1279         nmod.setup(m, i)
1280         n_out = nmod.ospec()
1281         m.d.comb += n_out.eq(nmod.o)
1282
1283         # Rounding (chained to normalisation)
1284         rmod = FPRoundMod(self.width, self.id_wid)
1285         rmod.setup(m, n_out)
1286         r_out_z = rmod.ospec()
1287         m.d.comb += r_out_z.eq(rmod.out_z)
1288
1289         # Corrections (chained to rounding)
1290         cmod = FPCorrectionsMod(self.width, self.id_wid)
1291         cmod.setup(m, r_out_z)
1292         c_out_z = cmod.ospec()
1293         m.d.comb += c_out_z.eq(cmod.out_z)
1294
1295         # Pack (chained to corrections)
1296         self.pmod = FPPackMod(self.width, self.id_wid)
1297         self.pmod.setup(m, c_out_z)
1298         self.out_z = self.pmod.ospec()
1299
1300         # Multiplex ID
1301         if self.in_mid is not None:
1302             m.d.comb += self.in_mid.eq(in_mid)
1303
1304         self.idsync(m) # copies incoming ID to outgoing
1305         m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1306
1307     def action(self, m):
1308         m.next = "pack_put_z"
1309
1310
1311 class FPRoundData:
1312
1313     def __init__(self, width, id_wid):
1314         self.z = FPNumBase(width, False)
1315         self.mid = Signal(id_wid, reset_less=True)
1316
1317     def eq(self, i):
1318         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1319
1320
1321 class FPRoundMod:
1322
1323     def __init__(self, width, id_wid):
1324         self.width = width
1325         self.id_wid = id_wid
1326         self.i = self.ispec()
1327         self.out_z = self.ospec()
1328
1329     def ispec(self):
1330         return FPNorm1Data(self.width, self.id_wid)
1331
1332     def ospec(self):
1333         return FPRoundData(self.width, self.id_wid)
1334
1335     def setup(self, m, i):
1336         m.submodules.roundz = self
1337         m.d.comb += self.i.eq(i)
1338
1339     def elaborate(self, platform):
1340         m = Module()
1341         m.d.comb += self.out_z.eq(self.i)
1342         with m.If(self.i.roundz):
1343             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1344             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1345                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1346         return m
1347
1348
1349 class FPRound(FPState, FPID):
1350
1351     def __init__(self, width, id_wid):
1352         FPState.__init__(self, "round")
1353         FPID.__init__(self, id_wid)
1354         self.mod = FPRoundMod(width)
1355         self.out_z = self.ospec()
1356
1357     def ispec(self):
1358         return self.mod.ispec()
1359
1360     def ospec(self):
1361         return self.mod.ospec()
1362
1363     def setup(self, m, i, in_mid):
1364         """ links module to inputs and outputs
1365         """
1366         self.mod.setup(m, i)
1367
1368         if self.in_mid is not None:
1369             m.d.comb += self.in_mid.eq(in_mid)
1370
1371         self.idsync(m)
1372         m.d.sync += self.out_z.eq(self.mod.out_z)
1373
1374     def action(self, m):
1375         m.next = "corrections"
1376
1377
1378 class FPCorrectionsMod:
1379
1380     def __init__(self, width, id_wid):
1381         self.width = width
1382         self.id_wid = id_wid
1383         self.i = self.ispec()
1384         self.out_z = self.ospec()
1385
1386     def ispec(self):
1387         return FPRoundData(self.width, self.id_wid)
1388
1389     def ospec(self):
1390         return FPRoundData(self.width, self.id_wid)
1391
1392     def setup(self, m, i):
1393         """ links module to inputs and outputs
1394         """
1395         m.submodules.corrections = self
1396         m.d.comb += self.i.eq(i)
1397
1398     def elaborate(self, platform):
1399         m = Module()
1400         m.submodules.corr_in_z = self.i.z
1401         m.submodules.corr_out_z = self.out_z.z
1402         m.d.comb += self.out_z.eq(self.i)
1403         with m.If(self.i.z.is_denormalised):
1404             m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1405         return m
1406
1407
1408 class FPCorrections(FPState, FPID):
1409
1410     def __init__(self, width, id_wid):
1411         FPState.__init__(self, "corrections")
1412         FPID.__init__(self, id_wid)
1413         self.mod = FPCorrectionsMod(width)
1414         self.out_z = self.ospec()
1415
1416     def ispec(self):
1417         return self.mod.ispec()
1418
1419     def ospec(self):
1420         return self.mod.ospec()
1421
1422     def setup(self, m, in_z, in_mid):
1423         """ links module to inputs and outputs
1424         """
1425         self.mod.setup(m, in_z)
1426         if self.in_mid is not None:
1427             m.d.comb += self.in_mid.eq(in_mid)
1428
1429         self.idsync(m)
1430         m.d.sync += self.out_z.eq(self.mod.out_z)
1431
1432     def action(self, m):
1433         m.next = "pack"
1434
1435
1436 class FPPackData:
1437
1438     def __init__(self, width, id_wid):
1439         self.z = FPNumOut(width, False)
1440         self.mid = Signal(id_wid, reset_less=True)
1441
1442     def eq(self, i):
1443         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1444
1445
1446 class FPPackMod:
1447
1448     def __init__(self, width, id_wid):
1449         self.width = width
1450         self.id_wid = id_wid
1451         self.i = self.ispec()
1452         self.o = self.ospec()
1453
1454     def ispec(self):
1455         return FPRoundData(self.width, self.id_wid)
1456
1457     def ospec(self):
1458         return FPPackData(self.width, self.id_wid)
1459
1460     def setup(self, m, in_z):
1461         """ links module to inputs and outputs
1462         """
1463         m.submodules.pack = self
1464         m.d.comb += self.i.eq(in_z)
1465
1466     def elaborate(self, platform):
1467         m = Module()
1468         m.submodules.pack_in_z = self.i.z
1469         with m.If(self.i.z.is_overflowed):
1470             m.d.comb += self.o.z.inf(self.i.z.s)
1471         with m.Else():
1472             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1473         return m
1474
1475
1476 class FPPackData:
1477     def __init__(self, width, id_wid):
1478         self.z = FPNumOut(width, False)
1479         self.mid = Signal(id_wid, reset_less=True)
1480
1481     def eq(self, i):
1482         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1483
1484
1485 class FPPack(FPState, FPID):
1486
1487     def __init__(self, width, id_wid):
1488         FPState.__init__(self, "pack")
1489         FPID.__init__(self, id_wid)
1490         self.mod = FPPackMod(width)
1491         self.out_z = self.ospec()
1492
1493     def ispec(self):
1494         return self.mod.ispec()
1495
1496     def ospec(self):
1497         return self.mod.ospec()
1498
1499     def setup(self, m, in_z, in_mid):
1500         """ links module to inputs and outputs
1501         """
1502         self.mod.setup(m, in_z)
1503         if self.in_mid is not None:
1504             m.d.comb += self.in_mid.eq(in_mid)
1505
1506         self.idsync(m)
1507         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1508
1509     def action(self, m):
1510         m.next = "pack_put_z"
1511
1512
1513 class FPPutZ(FPState):
1514
1515     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1516         FPState.__init__(self, state)
1517         if to_state is None:
1518             to_state = "get_ops"
1519         self.to_state = to_state
1520         self.in_z = in_z
1521         self.out_z = out_z
1522         self.in_mid = in_mid
1523         self.out_mid = out_mid
1524
1525     def action(self, m):
1526         if self.in_mid is not None:
1527             m.d.sync += self.out_mid.eq(self.in_mid)
1528         m.d.sync += [
1529           self.out_z.z.v.eq(self.in_z.v)
1530         ]
1531         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1532             m.d.sync += self.out_z.z.stb.eq(0)
1533             m.next = self.to_state
1534         with m.Else():
1535             m.d.sync += self.out_z.z.stb.eq(1)
1536
1537
1538 class FPPutZIdx(FPState):
1539
1540     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1541         FPState.__init__(self, state)
1542         if to_state is None:
1543             to_state = "get_ops"
1544         self.to_state = to_state
1545         self.in_z = in_z
1546         self.out_zs = out_zs
1547         self.in_mid = in_mid
1548
1549     def action(self, m):
1550         outz_stb = Signal(reset_less=True)
1551         outz_ack = Signal(reset_less=True)
1552         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1553                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1554                     ]
1555         m.d.sync += [
1556           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1557         ]
1558         with m.If(outz_stb & outz_ack):
1559             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1560             m.next = self.to_state
1561         with m.Else():
1562             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1563
1564 class FPADDBaseData:
1565
1566     def __init__(self, width, id_wid):
1567         self.width = width
1568         self.id_wid = id_wid
1569         self.a  = Signal(width)
1570         self.b  = Signal(width)
1571         self.mid = Signal(id_wid, reset_less=True)
1572
1573     def eq(self, i):
1574         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1575
1576
1577 class FPOpData:
1578     def __init__(self, width, id_wid):
1579         self.z = FPOp(width)
1580         self.mid = Signal(id_wid, reset_less=True)
1581
1582     def eq(self, i):
1583         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1584
1585
1586 class FPADDBaseMod(FPID):
1587
1588     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1589         """ IEEE754 FP Add
1590
1591             * width: bit-width of IEEE754.  supported: 16, 32, 64
1592             * id_wid: an identifier that is sync-connected to the input
1593             * single_cycle: True indicates each stage to complete in 1 clock
1594             * compact: True indicates a reduced number of stages
1595         """
1596         FPID.__init__(self, id_wid)
1597         self.width = width
1598         self.id_wid = id_wid
1599         self.single_cycle = single_cycle
1600         self.compact = compact
1601
1602         self.in_t = Trigger()
1603         self.i = self.ispec()
1604         self.o = self.ospec()
1605
1606         self.states = []
1607
1608     def ispec(self):
1609         return FPADDBaseData(self.width, self.id_wid)
1610
1611     def ospec(self):
1612         return FPOpData(self.width, self.id_wid)
1613
1614     def add_state(self, state):
1615         self.states.append(state)
1616         return state
1617
1618     def get_fragment(self, platform=None):
1619         """ creates the HDL code-fragment for FPAdd
1620         """
1621         m = Module()
1622         m.submodules.out_z = self.o.z
1623         m.submodules.in_t = self.in_t
1624         if self.compact:
1625             self.get_compact_fragment(m, platform)
1626         else:
1627             self.get_longer_fragment(m, platform)
1628
1629         with m.FSM() as fsm:
1630
1631             for state in self.states:
1632                 with m.State(state.state_from):
1633                     state.action(m)
1634
1635         return m
1636
1637     def get_longer_fragment(self, m, platform=None):
1638
1639         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1640                                       self.width))
1641         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1642         a = get.out_op1
1643         b = get.out_op2
1644
1645         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1646         sc.setup(m, a, b, self.in_mid)
1647
1648         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1649         dn.setup(m, a, b, sc.in_mid)
1650
1651         if self.single_cycle:
1652             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1653             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1654         else:
1655             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1656             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1657
1658         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1659         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1660
1661         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1662         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1663
1664         if self.single_cycle:
1665             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1666             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1667         else:
1668             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1669             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1670
1671         rn = self.add_state(FPRound(self.width, self.id_wid))
1672         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1673
1674         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1675         cor.setup(m, rn.out_z, rn.in_mid)
1676
1677         pa = self.add_state(FPPack(self.width, self.id_wid))
1678         pa.setup(m, cor.out_z, rn.in_mid)
1679
1680         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1681                                     pa.in_mid, self.out_mid))
1682
1683         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1684                                     pa.in_mid, self.out_mid))
1685
1686     def get_compact_fragment(self, m, platform=None):
1687
1688         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1689                                       self.width, self.id_wid))
1690         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1691
1692         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1693         sc.setup(m, get.o, self.in_mid)
1694
1695         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1696         alm.setup(m, sc.o, sc.in_mid)
1697
1698         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1699         n1.setup(m, alm.a1o, alm.in_mid)
1700
1701         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1702                                     n1.in_mid, self.out_mid))
1703
1704         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1705                                     sc.in_mid, self.out_mid))
1706
1707
1708 class FPADDBase(FPState, FPID):
1709
1710     def __init__(self, width, id_wid=None, single_cycle=False):
1711         """ IEEE754 FP Add
1712
1713             * width: bit-width of IEEE754.  supported: 16, 32, 64
1714             * id_wid: an identifier that is sync-connected to the input
1715             * single_cycle: True indicates each stage to complete in 1 clock
1716         """
1717         FPID.__init__(self, id_wid)
1718         FPState.__init__(self, "fpadd")
1719         self.width = width
1720         self.single_cycle = single_cycle
1721         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1722         self.o = self.ospec()
1723
1724         self.in_t = Trigger()
1725         self.i = self.ispec()
1726
1727         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1728         self.in_accept = Signal(reset_less=True)
1729         self.add_stb = Signal(reset_less=True)
1730         self.add_ack = Signal(reset=0, reset_less=True)
1731
1732     def ispec(self):
1733         return self.mod.ispec()
1734
1735     def ospec(self):
1736         return self.mod.ospec()
1737
1738     def setup(self, m, i, add_stb, in_mid):
1739         m.d.comb += [self.i.eq(i),
1740                      self.mod.i.eq(self.i),
1741                      self.in_mid.eq(in_mid),
1742                      self.mod.in_mid.eq(self.in_mid),
1743                      self.z_done.eq(self.mod.o.z.trigger),
1744                      #self.add_stb.eq(add_stb),
1745                      self.mod.in_t.stb.eq(self.in_t.stb),
1746                      self.in_t.ack.eq(self.mod.in_t.ack),
1747                      self.o.mid.eq(self.mod.o.mid),
1748                      self.o.z.v.eq(self.mod.o.z.v),
1749                      self.o.z.stb.eq(self.mod.o.z.stb),
1750                      self.mod.o.z.ack.eq(self.o.z.ack),
1751                     ]
1752
1753         m.d.sync += self.add_stb.eq(add_stb)
1754         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1755         m.d.sync += self.o.z.ack.eq(0) # likewise
1756         #m.d.sync += self.in_t.stb.eq(0)
1757
1758         m.submodules.fpadd = self.mod
1759
1760     def action(self, m):
1761
1762         # in_accept is set on incoming strobe HIGH and ack LOW.
1763         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1764
1765         #with m.If(self.in_t.ack):
1766         #    m.d.sync += self.in_t.stb.eq(0)
1767         with m.If(~self.z_done):
1768             # not done: test for accepting an incoming operand pair
1769             with m.If(self.in_accept):
1770                 m.d.sync += [
1771                     self.add_ack.eq(1), # acknowledge receipt...
1772                     self.in_t.stb.eq(1), # initiate add
1773                 ]
1774             with m.Else():
1775                 m.d.sync += [self.add_ack.eq(0),
1776                              self.in_t.stb.eq(0),
1777                              self.o.z.ack.eq(1),
1778                             ]
1779         with m.Else():
1780             # done: acknowledge, and write out id and value
1781             m.d.sync += [self.add_ack.eq(1),
1782                          self.in_t.stb.eq(0)
1783                         ]
1784             m.next = "put_z"
1785
1786             return
1787
1788             if self.in_mid is not None:
1789                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1790
1791             m.d.sync += [
1792               self.out_z.v.eq(self.mod.out_z.v)
1793             ]
1794             # move to output state on detecting z ack
1795             with m.If(self.out_z.trigger):
1796                 m.d.sync += self.out_z.stb.eq(0)
1797                 m.next = "put_z"
1798             with m.Else():
1799                 m.d.sync += self.out_z.stb.eq(1)
1800
1801
1802 class ResArray:
1803     def __init__(self, width, id_wid):
1804         self.width = width
1805         self.id_wid = id_wid
1806         res = []
1807         for i in range(rs_sz):
1808             out_z = FPOp(width)
1809             out_z.name = "out_z_%d" % i
1810             res.append(out_z)
1811         self.res = Array(res)
1812         self.in_z = FPOp(width)
1813         self.in_mid = Signal(self.id_wid, reset_less=True)
1814
1815     def setup(self, m, in_z, in_mid):
1816         m.d.comb += [self.in_z.eq(in_z),
1817                      self.in_mid.eq(in_mid)]
1818
1819     def get_fragment(self, platform=None):
1820         """ creates the HDL code-fragment for FPAdd
1821         """
1822         m = Module()
1823         m.submodules.res_in_z = self.in_z
1824         m.submodules += self.res
1825
1826         return m
1827
1828     def ports(self):
1829         res = []
1830         for z in self.res:
1831             res += z.ports()
1832         return res
1833
1834
1835 class FPADD(FPID):
1836     """ FPADD: stages as follows:
1837
1838         FPGetOp (a)
1839            |
1840         FPGetOp (b)
1841            |
1842         FPAddBase---> FPAddBaseMod
1843            |            |
1844         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1845
1846         FPAddBase is tricky: it is both a stage and *has* stages.
1847         Connection to FPAddBaseMod therefore requires an in stb/ack
1848         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1849         needs to be the thing that raises the incoming stb.
1850     """
1851
1852     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1853         """ IEEE754 FP Add
1854
1855             * width: bit-width of IEEE754.  supported: 16, 32, 64
1856             * id_wid: an identifier that is sync-connected to the input
1857             * single_cycle: True indicates each stage to complete in 1 clock
1858         """
1859         self.width = width
1860         self.id_wid = id_wid
1861         self.single_cycle = single_cycle
1862
1863         #self.out_z = FPOp(width)
1864         self.ids = FPID(id_wid)
1865
1866         rs = []
1867         for i in range(rs_sz):
1868             in_a  = FPOp(width)
1869             in_b  = FPOp(width)
1870             in_a.name = "in_a_%d" % i
1871             in_b.name = "in_b_%d" % i
1872             rs.append((in_a, in_b))
1873         self.rs = Array(rs)
1874
1875         res = []
1876         for i in range(rs_sz):
1877             out_z = FPOp(width)
1878             out_z.name = "out_z_%d" % i
1879             res.append(out_z)
1880         self.res = Array(res)
1881
1882         self.states = []
1883
1884     def add_state(self, state):
1885         self.states.append(state)
1886         return state
1887
1888     def get_fragment(self, platform=None):
1889         """ creates the HDL code-fragment for FPAdd
1890         """
1891         m = Module()
1892         m.submodules += self.rs
1893
1894         in_a = self.rs[0][0]
1895         in_b = self.rs[0][1]
1896
1897         geta = self.add_state(FPGetOp("get_a", "get_b",
1898                                       in_a, self.width))
1899         geta.setup(m, in_a)
1900         a = geta.out_op
1901
1902         getb = self.add_state(FPGetOp("get_b", "fpadd",
1903                                       in_b, self.width))
1904         getb.setup(m, in_b)
1905         b = getb.out_op
1906
1907         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1908         ab = self.add_state(ab)
1909         abd = ab.ispec() # create an input spec object for FPADDBase
1910         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1911         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1912         o = ab.o
1913
1914         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1915                                     o.mid, "get_a"))
1916
1917         with m.FSM() as fsm:
1918
1919             for state in self.states:
1920                 with m.State(state.state_from):
1921                     state.action(m)
1922
1923         return m
1924
1925
1926 if __name__ == "__main__":
1927     if True:
1928         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1929         main(alu, ports=alu.rs[0][0].ports() + \
1930                         alu.rs[0][1].ports() + \
1931                         alu.res[0].ports() + \
1932                         [alu.ids.in_mid, alu.ids.out_mid])
1933     else:
1934         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1935         main(alu, ports=[alu.in_a, alu.in_b] + \
1936                         alu.in_t.ports() + \
1937                         alu.out_z.ports() + \
1938                         [alu.in_mid, alu.out_mid])
1939
1940
1941     # works... but don't use, just do "python fname.py convert -t v"
1942     #print (verilog.convert(alu, ports=[
1943     #                        ports=alu.in_a.ports() + \
1944     #                              alu.in_b.ports() + \
1945     #                              alu.out_z.ports())