src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  37         #m.submodules.get_op_in = self.in_op
  38         m.submodules.get_op_out = self.out_op
  39         with m.If(self.out_decode):
  40             m.d.comb += [
  41                 self.out_op.decode(self.in_op.v),
  42             ]
  43         return m
  44
  45
  46 class FPGetOp(FPState):
  47     """ gets operand
  48     """
  49
  50     def __init__(self, in_state, out_state, in_op, width):
  51         FPState.__init__(self, in_state)
  52         self.out_state = out_state
  53         self.mod = FPGetOpMod(width)
  54         self.in_op = in_op
  55         self.out_op = FPNumIn(in_op, width)
  56         self.out_decode = Signal(reset_less=True)
  57
  58     def setup(self, m, in_op):
  59         """ links module to inputs and outputs
  60         """
  61         setattr(m.submodules, self.state_from, self.mod)
  62         m.d.comb += self.mod.in_op.copy(in_op)
  63         m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
  64         m.d.comb += self.out_decode.eq(self.mod.out_decode)
  65
  66     def action(self, m):
  67         with m.If(self.out_decode):
  68             m.next = self.out_state
  69             m.d.sync += [
  70                 self.in_op.ack.eq(0),
  71                 self.out_op.copy(self.mod.out_op)
  72             ]
  73         with m.Else():
  74             m.d.sync += self.in_op.ack.eq(1)
  75
  76
  77 class FPAddSpecialCasesMod:
  78     """ special cases: NaNs, infs, zeros, denormalised
  79         NOTE: some of these are unique to add.  see "Special Operations"
  80         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  81     """
  82
  83     def __init__(self, width):
  84         self.in_a = FPNumBase(width)
  85         self.in_b = FPNumBase(width)
  86         self.out_z = FPNumOut(width, False)
  87         self.out_do_z = Signal(reset_less=True)
  88
  89     def elaborate(self, platform):
  90         m = Module()
  91
  92         m.submodules.sc_in_a = self.in_a
  93         m.submodules.sc_in_b = self.in_b
  94         m.submodules.sc_out_z = self.out_z
  95
  96         s_nomatch = Signal()
  97         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
  98
  99         m_match = Signal()
 100         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 101
 102         # if a is NaN or b is NaN return NaN
 103         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 104             m.d.comb += self.out_do_z.eq(1)
 105             m.d.comb += self.out_z.nan(0)
 106
 107         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 108         # under review
 109
 110         ## if a is zero and b is NaN return -b
 111         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 112         #    m.d.comb += self.out_do_z.eq(1)
 113         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 114
 115         ## if b is zero and a is NaN return -a
 116         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 117         #    m.d.comb += self.out_do_z.eq(1)
 118         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 119
 120         ## if a is -zero and b is NaN return -b
 121         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 122         #    m.d.comb += self.out_do_z.eq(1)
 123         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 124
 125         ## if b is -zero and a is NaN return -a
 126         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 127         #    m.d.comb += self.out_do_z.eq(1)
 128         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 129
 130         # if a is inf return inf (or NaN)
 131         with m.Elif(self.in_a.is_inf):
 132             m.d.comb += self.out_do_z.eq(1)
 133             m.d.comb += self.out_z.inf(self.in_a.s)
 134             # if a is inf and signs don't match return NaN
 135             with m.If(self.in_b.exp_128 & s_nomatch):
 136                 m.d.comb += self.out_z.nan(0)
 137
 138         # if b is inf return inf
 139         with m.Elif(self.in_b.is_inf):
 140             m.d.comb += self.out_do_z.eq(1)
 141             m.d.comb += self.out_z.inf(self.in_b.s)
 142
 143         # if a is zero and b zero return signed-a/b
 144         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 145             m.d.comb += self.out_do_z.eq(1)
 146             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 147                                           self.in_b.e,
 148                                           self.in_b.m[3:-1])
 149
 150         # if a is zero return b
 151         with m.Elif(self.in_a.is_zero):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 154                                       self.in_b.m[3:-1])
 155
 156         # if b is zero return a
 157         with m.Elif(self.in_b.is_zero):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 160                                       self.in_a.m[3:-1])
 161
 162         # if a equal to -b return zero (+ve zero)
 163         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 164             m.d.comb += self.out_do_z.eq(1)
 165             m.d.comb += self.out_z.zero(0)
 166
 167         # Denormalised Number checks
 168         with m.Else():
 169             m.d.comb += self.out_do_z.eq(0)
 170
 171         return m
 172
 173
 174 class FPID:
 175     def __init__(self, id_wid):
 176         self.id_wid = id_wid
 177         if self.id_wid:
 178             self.in_mid = Signal(width, reset_less)
 179             self.out_mid = Signal(width, reset_less)
 180         else:
 181             self.in_mid = None
 182             self.out_mid = None
 183
 184     def idsync(self, m):
 185         if self.id_wid:
 186             m.d.sync += self.out_mid.eq(self.in_mid)
 187
 188
 189 class FPAddSpecialCases(FPState, FPID):
 190     """ special cases: NaNs, infs, zeros, denormalised
 191         NOTE: some of these are unique to add.  see "Special Operations"
 192         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 193     """
 194
 195     def __init__(self, width, id_wid):
 196         FPState.__init__(self, "special_cases")
 197         FPID.__init__(self, id_wid)
 198         self.mod = FPAddSpecialCasesMod(width)
 199         self.out_z = FPNumOut(width, False)
 200         self.out_do_z = Signal(reset_less=True)
 201
 202     def setup(self, m, in_a, in_b, in_mid):
 203         """ links module to inputs and outputs
 204         """
 205         m.submodules.specialcases = self.mod
 206         m.d.comb += self.mod.in_a.copy(in_a)
 207         m.d.comb += self.mod.in_b.copy(in_b)
 208         #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
 209         m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
 210         if self.in_mid:
 211             m.d.comb += self.in_mid.eq(in_mid)
 212
 213     def action(self, m):
 214         self.idsync(m)
 215         with m.If(self.out_do_z):
 216             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 217             m.next = "put_z"
 218         with m.Else():
 219             m.next = "denormalise"
 220
 221
 222 class FPAddDeNormMod(FPState):
 223
 224     def __init__(self, width):
 225         self.in_a = FPNumBase(width)
 226         self.in_b = FPNumBase(width)
 227         self.out_a = FPNumBase(width)
 228         self.out_b = FPNumBase(width)
 229
 230     def elaborate(self, platform):
 231         m = Module()
 232         m.submodules.denorm_in_a = self.in_a
 233         m.submodules.denorm_in_b = self.in_b
 234         m.submodules.denorm_out_a = self.out_a
 235         m.submodules.denorm_out_b = self.out_b
 236         # hmmm, don't like repeating identical code
 237         m.d.comb += self.out_a.copy(self.in_a)
 238         with m.If(self.in_a.exp_n127):
 239             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 240         with m.Else():
 241             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 242
 243         m.d.comb += self.out_b.copy(self.in_b)
 244         with m.If(self.in_b.exp_n127):
 245             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 246         with m.Else():
 247             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 248
 249         return m
 250
 251
 252 class FPAddDeNorm(FPState):
 253
 254     def __init__(self, width):
 255         FPState.__init__(self, "denormalise")
 256         self.mod = FPAddDeNormMod(width)
 257         self.out_a = FPNumBase(width)
 258         self.out_b = FPNumBase(width)
 259
 260     def setup(self, m, in_a, in_b):
 261         """ links module to inputs and outputs
 262         """
 263         m.submodules.denormalise = self.mod
 264         m.d.comb += self.mod.in_a.copy(in_a)
 265         m.d.comb += self.mod.in_b.copy(in_b)
 266
 267     def action(self, m):
 268         # Denormalised Number checks
 269         m.next = "align"
 270         m.d.sync += self.out_a.copy(self.mod.out_a)
 271         m.d.sync += self.out_b.copy(self.mod.out_b)
 272
 273
 274 class FPAddAlignMultiMod(FPState):
 275
 276     def __init__(self, width):
 277         self.in_a = FPNumBase(width)
 278         self.in_b = FPNumBase(width)
 279         self.out_a = FPNumIn(None, width)
 280         self.out_b = FPNumIn(None, width)
 281         self.exp_eq = Signal(reset_less=True)
 282
 283     def elaborate(self, platform):
 284         # This one however (single-cycle) will do the shift
 285         # in one go.
 286
 287         m = Module()
 288
 289         m.submodules.align_in_a = self.in_a
 290         m.submodules.align_in_b = self.in_b
 291         m.submodules.align_out_a = self.out_a
 292         m.submodules.align_out_b = self.out_b
 293
 294         # NOTE: this does *not* do single-cycle multi-shifting,
 295         #       it *STAYS* in the align state until exponents match
 296
 297         # exponent of a greater than b: shift b down
 298         m.d.comb += self.exp_eq.eq(0)
 299         m.d.comb += self.out_a.copy(self.in_a)
 300         m.d.comb += self.out_b.copy(self.in_b)
 301         agtb = Signal(reset_less=True)
 302         altb = Signal(reset_less=True)
 303         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 304         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 305         with m.If(agtb):
 306             m.d.comb += self.out_b.shift_down(self.in_b)
 307         # exponent of b greater than a: shift a down
 308         with m.Elif(altb):
 309             m.d.comb += self.out_a.shift_down(self.in_a)
 310         # exponents equal: move to next stage.
 311         with m.Else():
 312             m.d.comb += self.exp_eq.eq(1)
 313         return m
 314
 315
 316 class FPAddAlignMulti(FPState):
 317
 318     def __init__(self, width):
 319         FPState.__init__(self, "align")
 320         self.mod = FPAddAlignMultiMod(width)
 321         self.out_a = FPNumIn(None, width)
 322         self.out_b = FPNumIn(None, width)
 323         self.exp_eq = Signal(reset_less=True)
 324
 325     def setup(self, m, in_a, in_b):
 326         """ links module to inputs and outputs
 327         """
 328         m.submodules.align = self.mod
 329         m.d.comb += self.mod.in_a.copy(in_a)
 330         m.d.comb += self.mod.in_b.copy(in_b)
 331         #m.d.comb += self.out_a.copy(self.mod.out_a)
 332         #m.d.comb += self.out_b.copy(self.mod.out_b)
 333         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 334
 335     def action(self, m):
 336         m.d.sync += self.out_a.copy(self.mod.out_a)
 337         m.d.sync += self.out_b.copy(self.mod.out_b)
 338         with m.If(self.exp_eq):
 339             m.next = "add_0"
 340
 341
 342 class FPAddAlignSingleMod:
 343
 344     def __init__(self, width):
 345         self.width = width
 346         self.in_a = FPNumBase(width)
 347         self.in_b = FPNumBase(width)
 348         self.out_a = FPNumIn(None, width)
 349         self.out_b = FPNumIn(None, width)
 350
 351     def elaborate(self, platform):
 352         """ Aligns A against B or B against A, depending on which has the
 353             greater exponent.  This is done in a *single* cycle using
 354             variable-width bit-shift
 355
 356             the shifter used here is quite expensive in terms of gates.
 357             Mux A or B in (and out) into temporaries, as only one of them
 358             needs to be aligned against the other
 359         """
 360         m = Module()
 361
 362         m.submodules.align_in_a = self.in_a
 363         m.submodules.align_in_b = self.in_b
 364         m.submodules.align_out_a = self.out_a
 365         m.submodules.align_out_b = self.out_b
 366
 367         # temporary (muxed) input and output to be shifted
 368         t_inp = FPNumBase(self.width)
 369         t_out = FPNumIn(None, self.width)
 370         espec = (len(self.in_a.e), True)
 371         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 372         m.submodules.align_t_in = t_inp
 373         m.submodules.align_t_out = t_out
 374         m.submodules.multishift_r = msr
 375
 376         ediff = Signal(espec, reset_less=True)
 377         ediffr = Signal(espec, reset_less=True)
 378         tdiff = Signal(espec, reset_less=True)
 379         elz = Signal(reset_less=True)
 380         egz = Signal(reset_less=True)
 381
 382         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 383         m.d.comb += msr.inp.eq(t_inp.m)
 384         m.d.comb += msr.diff.eq(tdiff)
 385         m.d.comb += t_out.m.eq(msr.m)
 386         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 387         m.d.comb += t_out.s.eq(t_inp.s)
 388
 389         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 390         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 391         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 392         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 393
 394         # default: A-exp == B-exp, A and B untouched (fall through)
 395         m.d.comb += self.out_a.copy(self.in_a)
 396         m.d.comb += self.out_b.copy(self.in_b)
 397         # only one shifter (muxed)
 398         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 399         # exponent of a greater than b: shift b down
 400         with m.If(egz):
 401             m.d.comb += [t_inp.copy(self.in_b),
 402                          tdiff.eq(ediff),
 403                          self.out_b.copy(t_out),
 404                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 405                         ]
 406         # exponent of b greater than a: shift a down
 407         with m.Elif(elz):
 408             m.d.comb += [t_inp.copy(self.in_a),
 409                          tdiff.eq(ediffr),
 410                          self.out_a.copy(t_out),
 411                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 412                         ]
 413         return m
 414
 415
 416 class FPAddAlignSingle(FPState):
 417
 418     def __init__(self, width):
 419         FPState.__init__(self, "align")
 420         self.mod = FPAddAlignSingleMod(width)
 421         self.out_a = FPNumIn(None, width)
 422         self.out_b = FPNumIn(None, width)
 423
 424     def setup(self, m, in_a, in_b):
 425         """ links module to inputs and outputs
 426         """
 427         m.submodules.align = self.mod
 428         m.d.comb += self.mod.in_a.copy(in_a)
 429         m.d.comb += self.mod.in_b.copy(in_b)
 430
 431     def action(self, m):
 432         # NOTE: could be done as comb
 433         m.d.sync += self.out_a.copy(self.mod.out_a)
 434         m.d.sync += self.out_b.copy(self.mod.out_b)
 435         m.next = "add_0"
 436
 437
 438 class FPAddStage0Mod:
 439
 440     def __init__(self, width):
 441         self.in_a = FPNumBase(width)
 442         self.in_b = FPNumBase(width)
 443         self.in_z = FPNumBase(width, False)
 444         self.out_z = FPNumBase(width, False)
 445         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 446
 447     def elaborate(self, platform):
 448         m = Module()
 449         m.submodules.add0_in_a = self.in_a
 450         m.submodules.add0_in_b = self.in_b
 451         m.submodules.add0_out_z = self.out_z
 452
 453         m.d.comb += self.out_z.e.eq(self.in_a.e)
 454
 455         # store intermediate tests (and zero-extended mantissas)
 456         seq = Signal(reset_less=True)
 457         mge = Signal(reset_less=True)
 458         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 459         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 460         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 461                      mge.eq(self.in_a.m >= self.in_b.m),
 462                      am0.eq(Cat(self.in_a.m, 0)),
 463                      bm0.eq(Cat(self.in_b.m, 0))
 464                     ]
 465         # same-sign (both negative or both positive) add mantissas
 466         with m.If(seq):
 467             m.d.comb += [
 468                 self.out_tot.eq(am0 + bm0),
 469                 self.out_z.s.eq(self.in_a.s)
 470             ]
 471         # a mantissa greater than b, use a
 472         with m.Elif(mge):
 473             m.d.comb += [
 474                 self.out_tot.eq(am0 - bm0),
 475                 self.out_z.s.eq(self.in_a.s)
 476             ]
 477         # b mantissa greater than a, use b
 478         with m.Else():
 479             m.d.comb += [
 480                 self.out_tot.eq(bm0 - am0),
 481                 self.out_z.s.eq(self.in_b.s)
 482         ]
 483         return m
 484
 485
 486 class FPAddStage0(FPState):
 487     """ First stage of add.  covers same-sign (add) and subtract
 488         special-casing when mantissas are greater or equal, to
 489         give greatest accuracy.
 490     """
 491
 492     def __init__(self, width):
 493         FPState.__init__(self, "add_0")
 494         self.mod = FPAddStage0Mod(width)
 495         self.out_z = FPNumBase(width, False)
 496         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 497
 498     def setup(self, m, in_a, in_b):
 499         """ links module to inputs and outputs
 500         """
 501         m.submodules.add0 = self.mod
 502
 503         m.d.comb += self.mod.in_a.copy(in_a)
 504         m.d.comb += self.mod.in_b.copy(in_b)
 505
 506     def action(self, m):
 507         m.next = "add_1"
 508         # NOTE: these could be done as combinatorial (merge add0+add1)
 509         m.d.sync += self.out_z.copy(self.mod.out_z)
 510         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 511
 512
 513 class FPAddStage1Mod(FPState):
 514     """ Second stage of add: preparation for normalisation.
 515         detects when tot sum is too big (tot[27] is kinda a carry bit)
 516     """
 517
 518     def __init__(self, width):
 519         self.out_norm = Signal(reset_less=True)
 520         self.in_z = FPNumBase(width, False)
 521         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 522         self.out_z = FPNumBase(width, False)
 523         self.out_of = Overflow()
 524
 525     def elaborate(self, platform):
 526         m = Module()
 527         #m.submodules.norm1_in_overflow = self.in_of
 528         #m.submodules.norm1_out_overflow = self.out_of
 529         #m.submodules.norm1_in_z = self.in_z
 530         #m.submodules.norm1_out_z = self.out_z
 531         m.d.comb += self.out_z.copy(self.in_z)
 532         # tot[27] gets set when the sum overflows. shift result down
 533         with m.If(self.in_tot[-1]):
 534             m.d.comb += [
 535                 self.out_z.m.eq(self.in_tot[4:]),
 536                 self.out_of.m0.eq(self.in_tot[4]),
 537                 self.out_of.guard.eq(self.in_tot[3]),
 538                 self.out_of.round_bit.eq(self.in_tot[2]),
 539                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 540                 self.out_z.e.eq(self.in_z.e + 1)
 541         ]
 542         # tot[27] zero case
 543         with m.Else():
 544             m.d.comb += [
 545                 self.out_z.m.eq(self.in_tot[3:]),
 546                 self.out_of.m0.eq(self.in_tot[3]),
 547                 self.out_of.guard.eq(self.in_tot[2]),
 548                 self.out_of.round_bit.eq(self.in_tot[1]),
 549                 self.out_of.sticky.eq(self.in_tot[0])
 550         ]
 551         return m
 552
 553
 554 class FPAddStage1(FPState):
 555
 556     def __init__(self, width):
 557         FPState.__init__(self, "add_1")
 558         self.mod = FPAddStage1Mod(width)
 559         self.out_z = FPNumBase(width, False)
 560         self.out_of = Overflow()
 561         self.norm_stb = Signal()
 562
 563     def setup(self, m, in_tot, in_z):
 564         """ links module to inputs and outputs
 565         """
 566         m.submodules.add1 = self.mod
 567
 568         m.d.comb += self.mod.in_z.copy(in_z)
 569         m.d.comb += self.mod.in_tot.eq(in_tot)
 570
 571         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 572
 573     def action(self, m):
 574         m.submodules.add1_out_overflow = self.out_of
 575         m.d.sync += self.out_of.copy(self.mod.out_of)
 576         m.d.sync += self.out_z.copy(self.mod.out_z)
 577         m.d.sync += self.norm_stb.eq(1)
 578         m.next = "normalise_1"
 579
 580
 581 class FPNorm1ModSingle:
 582
 583     def __init__(self, width):
 584         self.width = width
 585         self.in_select = Signal(reset_less=True)
 586         self.out_norm = Signal(reset_less=True)
 587         self.in_z = FPNumBase(width, False)
 588         self.in_of = Overflow()
 589         self.temp_z = FPNumBase(width, False)
 590         self.temp_of = Overflow()
 591         self.out_z = FPNumBase(width, False)
 592         self.out_of = Overflow()
 593
 594     def elaborate(self, platform):
 595         m = Module()
 596
 597         mwid = self.out_z.m_width+2
 598         pe = PriorityEncoder(mwid)
 599         m.submodules.norm_pe = pe
 600
 601         m.submodules.norm1_out_z = self.out_z
 602         m.submodules.norm1_out_overflow = self.out_of
 603         m.submodules.norm1_temp_z = self.temp_z
 604         m.submodules.norm1_temp_of = self.temp_of
 605         m.submodules.norm1_in_z = self.in_z
 606         m.submodules.norm1_in_overflow = self.in_of
 607
 608         in_z = FPNumBase(self.width, False)
 609         in_of = Overflow()
 610         m.submodules.norm1_insel_z = in_z
 611         m.submodules.norm1_insel_overflow = in_of
 612
 613         espec = (len(in_z.e), True)
 614         ediff_n126 = Signal(espec, reset_less=True)
 615         msr = MultiShiftRMerge(mwid, espec)
 616         m.submodules.multishift_r = msr
 617
 618         # select which of temp or in z/of to use
 619         with m.If(self.in_select):
 620             m.d.comb += in_z.copy(self.in_z)
 621             m.d.comb += in_of.copy(self.in_of)
 622         with m.Else():
 623             m.d.comb += in_z.copy(self.temp_z)
 624             m.d.comb += in_of.copy(self.temp_of)
 625         # initialise out from in (overridden below)
 626         m.d.comb += self.out_z.copy(in_z)
 627         m.d.comb += self.out_of.copy(in_of)
 628         # normalisation increase/decrease conditions
 629         decrease = Signal(reset_less=True)
 630         increase = Signal(reset_less=True)
 631         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 632         m.d.comb += increase.eq(in_z.exp_lt_n126)
 633         m.d.comb += self.out_norm.eq(0) # loop-end condition
 634         # decrease exponent
 635         with m.If(decrease):
 636             # *sigh* not entirely obvious: count leading zeros (clz)
 637             # with a PriorityEncoder: to find from the MSB
 638             # we reverse the order of the bits.
 639             temp_m = Signal(mwid, reset_less=True)
 640             temp_s = Signal(mwid+1, reset_less=True)
 641             clz = Signal((len(in_z.e), True), reset_less=True)
 642             # make sure that the amount to decrease by does NOT
 643             # go below the minimum non-INF/NaN exponent
 644             limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 645                          in_z.exp_sub_n126)
 646             m.d.comb += [
 647                 # cat round and guard bits back into the mantissa
 648                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 649                 pe.i.eq(temp_m[::-1]),          # inverted
 650                 clz.eq(limclz),                 # count zeros from MSB down
 651                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 652                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 653                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 654                 self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 655                 # overflow in bits 0..1: got shifted too (leave sticky)
 656                 self.out_of.guard.eq(temp_s[1]),     # guard
 657                 self.out_of.round_bit.eq(temp_s[0]), # round
 658             ]
 659         # increase exponent
 660         with m.Elif(increase):
 661             temp_m = Signal(mwid+1, reset_less=True)
 662             m.d.comb += [
 663                 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
 664                               in_z.m)),
 665                 ediff_n126.eq(in_z.N126 - in_z.e),
 666                 # connect multi-shifter to inp/out mantissa (and ediff)
 667                 msr.inp.eq(temp_m),
 668                 msr.diff.eq(ediff_n126),
 669                 self.out_z.m.eq(msr.m[3:]),
 670                 self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
 671                 # overflow in bits 0..1: got shifted too (leave sticky)
 672                 self.out_of.guard.eq(temp_s[2]),     # guard
 673                 self.out_of.round_bit.eq(temp_s[1]), # round
 674                 self.out_of.sticky.eq(temp_s[0]), # sticky
 675                 self.out_z.e.eq(in_z.e + ediff_n126),
 676             ]
 677
 678         return m
 679
 680
 681 class FPNorm1ModMulti:
 682
 683     def __init__(self, width, single_cycle=True):
 684         self.width = width
 685         self.in_select = Signal(reset_less=True)
 686         self.out_norm = Signal(reset_less=True)
 687         self.in_z = FPNumBase(width, False)
 688         self.in_of = Overflow()
 689         self.temp_z = FPNumBase(width, False)
 690         self.temp_of = Overflow()
 691         self.out_z = FPNumBase(width, False)
 692         self.out_of = Overflow()
 693
 694     def elaborate(self, platform):
 695         m = Module()
 696
 697         m.submodules.norm1_out_z = self.out_z
 698         m.submodules.norm1_out_overflow = self.out_of
 699         m.submodules.norm1_temp_z = self.temp_z
 700         m.submodules.norm1_temp_of = self.temp_of
 701         m.submodules.norm1_in_z = self.in_z
 702         m.submodules.norm1_in_overflow = self.in_of
 703
 704         in_z = FPNumBase(self.width, False)
 705         in_of = Overflow()
 706         m.submodules.norm1_insel_z = in_z
 707         m.submodules.norm1_insel_overflow = in_of
 708
 709         # select which of temp or in z/of to use
 710         with m.If(self.in_select):
 711             m.d.comb += in_z.copy(self.in_z)
 712             m.d.comb += in_of.copy(self.in_of)
 713         with m.Else():
 714             m.d.comb += in_z.copy(self.temp_z)
 715             m.d.comb += in_of.copy(self.temp_of)
 716         # initialise out from in (overridden below)
 717         m.d.comb += self.out_z.copy(in_z)
 718         m.d.comb += self.out_of.copy(in_of)
 719         # normalisation increase/decrease conditions
 720         decrease = Signal(reset_less=True)
 721         increase = Signal(reset_less=True)
 722         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 723         m.d.comb += increase.eq(in_z.exp_lt_n126)
 724         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 725         # decrease exponent
 726         with m.If(decrease):
 727             m.d.comb += [
 728                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 729                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 730                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 731                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 732                 self.out_of.round_bit.eq(0),        # reset round bit
 733                 self.out_of.m0.eq(in_of.guard),
 734             ]
 735         # increase exponent
 736         with m.Elif(increase):
 737             m.d.comb += [
 738                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 739                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 740                 self.out_of.guard.eq(in_z.m[0]),
 741                 self.out_of.m0.eq(in_z.m[1]),
 742                 self.out_of.round_bit.eq(in_of.guard),
 743                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 744             ]
 745
 746         return m
 747
 748
 749 class FPNorm1(FPState):
 750
 751     def __init__(self, width, single_cycle=True):
 752         FPState.__init__(self, "normalise_1")
 753         if single_cycle:
 754             self.mod = FPNorm1ModSingle(width)
 755         else:
 756             self.mod = FPNorm1ModMulti(width)
 757         self.stb = Signal(reset_less=True)
 758         self.ack = Signal(reset=0, reset_less=True)
 759         self.out_norm = Signal(reset_less=True)
 760         self.in_accept = Signal(reset_less=True)
 761         self.temp_z = FPNumBase(width)
 762         self.temp_of = Overflow()
 763         self.out_z = FPNumBase(width)
 764         self.out_roundz = Signal(reset_less=True)
 765
 766     def setup(self, m, in_z, in_of, norm_stb):
 767         """ links module to inputs and outputs
 768         """
 769         m.submodules.normalise_1 = self.mod
 770
 771         m.d.comb += self.mod.in_z.copy(in_z)
 772         m.d.comb += self.mod.in_of.copy(in_of)
 773
 774         m.d.comb += self.mod.in_select.eq(self.in_accept)
 775         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 776         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 777
 778         m.d.comb += self.out_z.copy(self.mod.out_z)
 779         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 780
 781         m.d.comb += self.stb.eq(norm_stb)
 782         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 783
 784     def action(self, m):
 785
 786         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 787         m.d.sync += self.temp_of.copy(self.mod.out_of)
 788         m.d.sync += self.temp_z.copy(self.out_z)
 789         with m.If(self.out_norm):
 790             with m.If(self.in_accept):
 791                 m.d.sync += [
 792                     self.ack.eq(1),
 793                 ]
 794             with m.Else():
 795                 m.d.sync += self.ack.eq(0)
 796         with m.Else():
 797             # normalisation not required (or done).
 798             m.next = "round"
 799             m.d.sync += self.ack.eq(1)
 800             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 801
 802
 803 class FPRoundMod:
 804
 805     def __init__(self, width):
 806         self.in_roundz = Signal(reset_less=True)
 807         self.in_z = FPNumBase(width, False)
 808         self.out_z = FPNumBase(width, False)
 809
 810     def elaborate(self, platform):
 811         m = Module()
 812         m.d.comb += self.out_z.copy(self.in_z)
 813         with m.If(self.in_roundz):
 814             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 815             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 816                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 817         return m
 818
 819
 820 class FPRound(FPState):
 821
 822     def __init__(self, width):
 823         FPState.__init__(self, "round")
 824         self.mod = FPRoundMod(width)
 825         self.out_z = FPNumBase(width)
 826
 827     def setup(self, m, in_z, roundz):
 828         """ links module to inputs and outputs
 829         """
 830         m.submodules.roundz = self.mod
 831
 832         m.d.comb += self.mod.in_z.copy(in_z)
 833         m.d.comb += self.mod.in_roundz.eq(roundz)
 834
 835     def action(self, m):
 836         m.d.sync += self.out_z.copy(self.mod.out_z)
 837         m.next = "corrections"
 838
 839
 840 class FPCorrectionsMod:
 841
 842     def __init__(self, width):
 843         self.in_z = FPNumOut(width, False)
 844         self.out_z = FPNumOut(width, False)
 845
 846     def elaborate(self, platform):
 847         m = Module()
 848         m.submodules.corr_in_z = self.in_z
 849         m.submodules.corr_out_z = self.out_z
 850         m.d.comb += self.out_z.copy(self.in_z)
 851         with m.If(self.in_z.is_denormalised):
 852             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 853         return m
 854
 855
 856 class FPCorrections(FPState):
 857
 858     def __init__(self, width):
 859         FPState.__init__(self, "corrections")
 860         self.mod = FPCorrectionsMod(width)
 861         self.out_z = FPNumBase(width)
 862
 863     def setup(self, m, in_z):
 864         """ links module to inputs and outputs
 865         """
 866         m.submodules.corrections = self.mod
 867         m.d.comb += self.mod.in_z.copy(in_z)
 868
 869     def action(self, m):
 870         m.d.sync += self.out_z.copy(self.mod.out_z)
 871         m.next = "pack"
 872
 873
 874 class FPPackMod:
 875
 876     def __init__(self, width):
 877         self.in_z = FPNumOut(width, False)
 878         self.out_z = FPNumOut(width, False)
 879
 880     def elaborate(self, platform):
 881         m = Module()
 882         m.submodules.pack_in_z = self.in_z
 883         with m.If(self.in_z.is_overflowed):
 884             m.d.comb += self.out_z.inf(self.in_z.s)
 885         with m.Else():
 886             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 887         return m
 888
 889
 890 class FPPack(FPState):
 891
 892     def __init__(self, width):
 893         FPState.__init__(self, "pack")
 894         self.mod = FPPackMod(width)
 895         self.out_z = FPNumOut(width, False)
 896
 897     def setup(self, m, in_z):
 898         """ links module to inputs and outputs
 899         """
 900         m.submodules.pack = self.mod
 901         m.d.comb += self.mod.in_z.copy(in_z)
 902
 903     def action(self, m):
 904         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 905         m.next = "pack_put_z"
 906
 907
 908 class FPPutZ(FPState):
 909
 910     def __init__(self, state, in_z, out_z):
 911         FPState.__init__(self, state)
 912         self.in_z = in_z
 913         self.out_z = out_z
 914
 915     def action(self, m):
 916         m.d.sync += [
 917           self.out_z.v.eq(self.in_z.v)
 918         ]
 919         with m.If(self.out_z.stb & self.out_z.ack):
 920             m.d.sync += self.out_z.stb.eq(0)
 921             m.next = "get_a"
 922         with m.Else():
 923             m.d.sync += self.out_z.stb.eq(1)
 924
 925
 926 class FPADD(FPID):
 927
 928     def __init__(self, width, id_wid=None, single_cycle=False):
 929         """ IEEE754 FP Add
 930
 931             * width: bit-width of IEEE754.  supported: 16, 32, 64
 932             * id_wid: an identifier that is sync-connected to the input
 933             * single_cycle: True indicates each stage to complete in 1 clock
 934         """
 935         FPID.__init__(self, id_wid)
 936         self.width = width
 937         self.single_cycle = single_cycle
 938
 939         self.in_a  = FPOp(width)
 940         self.in_b  = FPOp(width)
 941         self.out_z = FPOp(width)
 942
 943         self.states = []
 944
 945     def add_state(self, state):
 946         self.states.append(state)
 947         return state
 948
 949     def get_fragment(self, platform=None):
 950         """ creates the HDL code-fragment for FPAdd
 951         """
 952         m = Module()
 953         m.submodules.in_a = self.in_a
 954         m.submodules.in_b = self.in_b
 955         m.submodules.out_z = self.out_z
 956
 957         geta = self.add_state(FPGetOp("get_a", "get_b",
 958                                       self.in_a, self.width))
 959         geta.setup(m, self.in_a)
 960         a = geta.out_op
 961
 962         getb = self.add_state(FPGetOp("get_b", "special_cases",
 963                                       self.in_b, self.width))
 964         getb.setup(m, self.in_b)
 965         b = getb.out_op
 966
 967         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
 968         sc.setup(m, a, b, self.in_mid)
 969
 970         dn = self.add_state(FPAddDeNorm(self.width))
 971         dn.setup(m, a, b)
 972
 973         if self.single_cycle:
 974             alm = self.add_state(FPAddAlignSingle(self.width))
 975             alm.setup(m, dn.out_a, dn.out_b)
 976         else:
 977             alm = self.add_state(FPAddAlignMulti(self.width))
 978             alm.setup(m, dn.out_a, dn.out_b)
 979
 980         add0 = self.add_state(FPAddStage0(self.width))
 981         add0.setup(m, alm.out_a, alm.out_b)
 982
 983         add1 = self.add_state(FPAddStage1(self.width))
 984         add1.setup(m, add0.out_tot, add0.out_z)
 985
 986         n1 = self.add_state(FPNorm1(self.width))
 987         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 988
 989         rn = self.add_state(FPRound(self.width))
 990         rn.setup(m, n1.out_z, n1.out_roundz)
 991
 992         cor = self.add_state(FPCorrections(self.width))
 993         cor.setup(m, rn.out_z)
 994
 995         pa = self.add_state(FPPack(self.width))
 996         pa.setup(m, cor.out_z)
 997
 998         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
 999
1000         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
1001
1002         with m.FSM() as fsm:
1003
1004             for state in self.states:
1005                 with m.State(state.state_from):
1006                     state.action(m)
1007
1008         return m
1009
1010
1011 if __name__ == "__main__":
1012     alu = FPADD(width=32, single_cycle=True)
1013     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
1014
1015
1016     # works... but don't use, just do "python fname.py convert -t v"
1017     #print (verilog.convert(alu, ports=[
1018     #                        ports=alu.in_a.ports() + \
1019     #                              alu.in_b.ports() + \
1020     #                              alu.out_z.ports())