src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
   9
  10
  11 class FPState(FPBase):
  12     def __init__(self, state_from):
  13         self.state_from = state_from
  14
  15     def set_inputs(self, inputs):
  16         self.inputs = inputs
  17         for k,v in inputs.items():
  18             setattr(self, k, v)
  19
  20     def set_outputs(self, outputs):
  21         self.outputs = outputs
  22         for k,v in outputs.items():
  23             setattr(self, k, v)
  24
  25
  26 class FPGetOpMod:
  27     def __init__(self, width):
  28         self.in_op = FPOp(width)
  29         self.out_op = FPNumIn(self.in_op, width)
  30         self.out_decode = Signal(reset_less=True)
  31
  32     def setup(self, m, in_op, out_op, out_decode):
  33         """ links module to inputs and outputs
  34         """
  35         m.d.comb += self.in_op.copy(in_op)
  36         m.d.comb += out_op.v.eq(self.out_op.v)
  37         m.d.comb += out_decode.eq(self.out_decode)
  38
  39     def elaborate(self, platform):
  40         m = Module()
  41         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  42         #m.submodules.get_op_in = self.in_op
  43         m.submodules.get_op_out = self.out_op
  44         with m.If(self.out_decode):
  45             m.d.comb += [
  46                 self.out_op.decode(self.in_op.v),
  47             ]
  48         return m
  49
  50
  51 class FPGetOp(FPState):
  52     """ gets operand
  53     """
  54
  55     def __init__(self, in_state, out_state, in_op, width):
  56         FPState.__init__(self, in_state)
  57         self.out_state = out_state
  58         self.mod = FPGetOpMod(width)
  59         self.in_op = in_op
  60         self.out_op = FPNumIn(in_op, width)
  61         self.out_decode = Signal(reset_less=True)
  62
  63     def action(self, m):
  64         with m.If(self.out_decode):
  65             m.next = self.out_state
  66             m.d.sync += [
  67                 self.in_op.ack.eq(0),
  68                 self.out_op.copy(self.mod.out_op)
  69             ]
  70         with m.Else():
  71             m.d.sync += self.in_op.ack.eq(1)
  72
  73
  74 class FPGetOpB(FPState):
  75     """ gets operand b
  76     """
  77
  78     def __init__(self, in_b, width):
  79         FPState.__init__(self, "get_b")
  80         self.in_b = in_b
  81         self.b = FPNumIn(self.in_b, width)
  82
  83     def action(self, m):
  84         self.get_op(m, self.in_b, self.b, "special_cases")
  85
  86
  87 class FPAddSpecialCasesMod:
  88     """ special cases: NaNs, infs, zeros, denormalised
  89         NOTE: some of these are unique to add.  see "Special Operations"
  90         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  91     """
  92
  93     def __init__(self, width):
  94         self.in_a = FPNumBase(width)
  95         self.in_b = FPNumBase(width)
  96         self.out_z = FPNumOut(width, False)
  97         self.out_do_z = Signal(reset_less=True)
  98
  99     def setup(self, m, in_a, in_b, out_z, out_do_z):
 100         """ links module to inputs and outputs
 101         """
 102         m.d.comb += self.in_a.copy(in_a)
 103         m.d.comb += self.in_b.copy(in_b)
 104         m.d.comb += out_z.v.eq(self.out_z.v)
 105         m.d.comb += out_do_z.eq(self.out_do_z)
 106
 107     def elaborate(self, platform):
 108         m = Module()
 109
 110         m.submodules.sc_in_a = self.in_a
 111         m.submodules.sc_in_b = self.in_b
 112         m.submodules.sc_out_z = self.out_z
 113
 114         s_nomatch = Signal()
 115         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
 116
 117         m_match = Signal()
 118         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 119
 120         # if a is NaN or b is NaN return NaN
 121         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 122             m.d.comb += self.out_do_z.eq(1)
 123             m.d.comb += self.out_z.nan(0)
 124
 125         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 126         # under review
 127
 128         ## if a is zero and b is NaN return -b
 129         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 130         #    m.d.comb += self.out_do_z.eq(1)
 131         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 132
 133         ## if b is zero and a is NaN return -a
 134         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 135         #    m.d.comb += self.out_do_z.eq(1)
 136         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 137
 138         ## if a is -zero and b is NaN return -b
 139         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 140         #    m.d.comb += self.out_do_z.eq(1)
 141         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 142
 143         ## if b is -zero and a is NaN return -a
 144         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 145         #    m.d.comb += self.out_do_z.eq(1)
 146         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 147
 148         # if a is inf return inf (or NaN)
 149         with m.Elif(self.in_a.is_inf):
 150             m.d.comb += self.out_do_z.eq(1)
 151             m.d.comb += self.out_z.inf(self.in_a.s)
 152             # if a is inf and signs don't match return NaN
 153             with m.If(self.in_b.exp_128 & s_nomatch):
 154                 m.d.comb += self.out_z.nan(0)
 155
 156         # if b is inf return inf
 157         with m.Elif(self.in_b.is_inf):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.inf(self.in_b.s)
 160
 161         # if a is zero and b zero return signed-a/b
 162         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 163             m.d.comb += self.out_do_z.eq(1)
 164             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 165                                           self.in_b.e,
 166                                           self.in_b.m[3:-1])
 167
 168         # if a is zero return b
 169         with m.Elif(self.in_a.is_zero):
 170             m.d.comb += self.out_do_z.eq(1)
 171             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 172                                       self.in_b.m[3:-1])
 173
 174         # if b is zero return a
 175         with m.Elif(self.in_b.is_zero):
 176             m.d.comb += self.out_do_z.eq(1)
 177             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 178                                       self.in_a.m[3:-1])
 179
 180         # if a equal to -b return zero (+ve zero)
 181         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 182             m.d.comb += self.out_do_z.eq(1)
 183             m.d.comb += self.out_z.zero(0)
 184
 185         # Denormalised Number checks
 186         with m.Else():
 187             m.d.comb += self.out_do_z.eq(0)
 188
 189         return m
 190
 191
 192 class FPAddSpecialCases(FPState):
 193     """ special cases: NaNs, infs, zeros, denormalised
 194         NOTE: some of these are unique to add.  see "Special Operations"
 195         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 196     """
 197
 198     def __init__(self, width):
 199         FPState.__init__(self, "special_cases")
 200         self.mod = FPAddSpecialCasesMod(width)
 201         self.out_z = FPNumOut(width, False)
 202         self.out_do_z = Signal(reset_less=True)
 203
 204     def action(self, m):
 205         with m.If(self.out_do_z):
 206             m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
 207             m.next = "put_z"
 208         with m.Else():
 209             m.next = "denormalise"
 210
 211
 212 class FPAddDeNormMod(FPState):
 213
 214     def __init__(self, width):
 215         self.in_a = FPNumBase(width)
 216         self.in_b = FPNumBase(width)
 217         self.out_a = FPNumBase(width)
 218         self.out_b = FPNumBase(width)
 219
 220     def setup(self, m, in_a, in_b, out_a, out_b):
 221         """ links module to inputs and outputs
 222         """
 223         m.d.comb += self.in_a.copy(in_a)
 224         m.d.comb += self.in_b.copy(in_b)
 225         m.d.comb += out_a.copy(self.out_a)
 226         m.d.comb += out_b.copy(self.out_b)
 227
 228     def elaborate(self, platform):
 229         m = Module()
 230         m.submodules.denorm_in_a = self.in_a
 231         m.submodules.denorm_in_b = self.in_b
 232         m.submodules.denorm_out_a = self.out_a
 233         m.submodules.denorm_out_b = self.out_b
 234         # hmmm, don't like repeating identical code
 235         m.d.comb += self.out_a.copy(self.in_a)
 236         with m.If(self.in_a.exp_n127):
 237             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 238         with m.Else():
 239             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 240
 241         m.d.comb += self.out_b.copy(self.in_b)
 242         with m.If(self.in_b.exp_n127):
 243             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 244         with m.Else():
 245             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 246
 247         return m
 248
 249
 250 class FPAddDeNorm(FPState):
 251
 252     def __init__(self, width):
 253         FPState.__init__(self, "denormalise")
 254         self.mod = FPAddDeNormMod(width)
 255         self.out_a = FPNumBase(width)
 256         self.out_b = FPNumBase(width)
 257
 258     def action(self, m):
 259         # Denormalised Number checks
 260         m.next = "align"
 261         m.d.sync += self.a.copy(self.out_a)
 262         m.d.sync += self.b.copy(self.out_b)
 263
 264
 265 class FPAddAlignMultiMod(FPState):
 266
 267     def __init__(self, width):
 268         self.in_a = FPNumBase(width)
 269         self.in_b = FPNumBase(width)
 270         self.out_a = FPNumIn(None, width)
 271         self.out_b = FPNumIn(None, width)
 272         self.exp_eq = Signal(reset_less=True)
 273
 274     def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
 275         """ links module to inputs and outputs
 276         """
 277         m.d.comb += self.in_a.copy(in_a)
 278         m.d.comb += self.in_b.copy(in_b)
 279         m.d.comb += out_a.copy(self.out_a)
 280         m.d.comb += out_b.copy(self.out_b)
 281         m.d.comb += exp_eq.eq(self.exp_eq)
 282
 283     def elaborate(self, platform):
 284         # This one however (single-cycle) will do the shift
 285         # in one go.
 286
 287         m = Module()
 288
 289         #m.submodules.align_in_a = self.in_a
 290         #m.submodules.align_in_b = self.in_b
 291         m.submodules.align_out_a = self.out_a
 292         m.submodules.align_out_b = self.out_b
 293
 294         # NOTE: this does *not* do single-cycle multi-shifting,
 295         #       it *STAYS* in the align state until exponents match
 296
 297         # exponent of a greater than b: shift b down
 298         m.d.comb += self.exp_eq.eq(0)
 299         m.d.comb += self.out_a.copy(self.in_a)
 300         m.d.comb += self.out_b.copy(self.in_b)
 301         agtb = Signal(reset_less=True)
 302         altb = Signal(reset_less=True)
 303         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 304         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 305         with m.If(agtb):
 306             m.d.comb += self.out_b.shift_down(self.in_b)
 307         # exponent of b greater than a: shift a down
 308         with m.Elif(altb):
 309             m.d.comb += self.out_a.shift_down(self.in_a)
 310         # exponents equal: move to next stage.
 311         with m.Else():
 312             m.d.comb += self.exp_eq.eq(1)
 313         return m
 314
 315
 316 class FPAddAlignMulti(FPState):
 317
 318     def __init__(self, width):
 319         FPState.__init__(self, "align")
 320         self.mod = FPAddAlignMultiMod(width)
 321         self.out_a = FPNumIn(None, width)
 322         self.out_b = FPNumIn(None, width)
 323         self.exp_eq = Signal(reset_less=True)
 324
 325     def action(self, m):
 326         m.d.sync += self.a.copy(self.out_a)
 327         m.d.sync += self.b.copy(self.out_b)
 328         with m.If(self.exp_eq):
 329             m.next = "add_0"
 330
 331
 332 class FPAddAlignSingleMod:
 333
 334     def __init__(self, width):
 335         self.in_a = FPNumBase(width)
 336         self.in_b = FPNumBase(width)
 337         self.out_a = FPNumIn(None, width)
 338         self.out_b = FPNumIn(None, width)
 339         #self.out_a = FPNumBase(width)
 340         #self.out_b = FPNumBase(width)
 341
 342     def setup(self, m, in_a, in_b, out_a, out_b):
 343         """ links module to inputs and outputs
 344         """
 345         m.d.comb += self.in_a.copy(in_a)
 346         m.d.comb += self.in_b.copy(in_b)
 347         m.d.comb += out_a.copy(self.out_a)
 348         m.d.comb += out_b.copy(self.out_b)
 349
 350     def elaborate(self, platform):
 351         # This one however (single-cycle) will do the shift
 352         # in one go.
 353
 354         m = Module()
 355
 356         #m.submodules.align_in_a = self.in_a
 357         #m.submodules.align_in_b = self.in_b
 358         m.submodules.align_out_a = self.out_a
 359         m.submodules.align_out_b = self.out_b
 360
 361         # XXX TODO: the shifter used here is quite expensive
 362         # having only one would be better
 363
 364         ediff = Signal((len(self.in_a.e), True), reset_less=True)
 365         ediffr = Signal((len(self.in_a.e), True), reset_less=True)
 366         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 367         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 368         m.d.comb += self.out_a.copy(self.in_a)
 369         m.d.comb += self.out_b.copy(self.in_b)
 370         with m.If(ediff > 0):
 371             m.d.comb += self.out_b.shift_down_multi(ediff)
 372         # exponent of b greater than a: shift a down
 373         with m.Elif(ediff < 0):
 374             m.d.comb += self.out_a.shift_down_multi(ediffr)
 375         return m
 376
 377
 378 class FPAddAlignSingle(FPState):
 379
 380     def __init__(self, width):
 381         FPState.__init__(self, "align")
 382         self.mod = FPAddAlignSingleMod(width)
 383         self.out_a = FPNumIn(None, width)
 384         self.out_b = FPNumIn(None, width)
 385
 386     def action(self, m):
 387         m.d.sync += self.a.copy(self.out_a)
 388         m.d.sync += self.b.copy(self.out_b)
 389         m.next = "add_0"
 390
 391
 392 class FPAddStage0Mod:
 393
 394     def __init__(self, width):
 395         self.in_a = FPNumBase(width)
 396         self.in_b = FPNumBase(width)
 397         self.in_z = FPNumBase(width, False)
 398         self.out_z = FPNumBase(width, False)
 399         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 400
 401     def setup(self, m, in_a, in_b, in_z, out_z, out_tot):
 402         """ links module to inputs and outputs
 403         """
 404         m.d.comb += self.in_a.copy(in_a)
 405         m.d.comb += self.in_b.copy(in_b)
 406         m.d.comb += self.in_z.copy(in_z)
 407         m.d.comb += out_z.copy(self.out_z)
 408         m.d.comb += out_tot.eq(self.out_tot)
 409
 410     def elaborate(self, platform):
 411         m = Module()
 412         m.submodules.add0_in_a = self.in_a
 413         m.submodules.add0_in_b = self.in_b
 414         #m.submodules.add0_in_z = self.in_z
 415         #m.submodules.add0_out_z = self.out_z
 416
 417         m.d.comb += self.out_z.e.eq(self.in_a.e)
 418         # same-sign (both negative or both positive) add mantissas
 419         seq = Signal(reset_less=True)
 420         mge = Signal(reset_less=True)
 421         m.d.comb += seq.eq(self.in_a.s == self.in_b.s)
 422         m.d.comb += mge.eq(self.in_a.m >= self.in_b.m)
 423         with m.If(seq):
 424             m.d.comb += [
 425                 self.out_tot.eq(Cat(self.in_a.m, 0) + Cat(self.in_b.m, 0)),
 426                 self.out_z.s.eq(self.in_a.s)
 427             ]
 428         # a mantissa greater than b, use a
 429         with m.Elif(mge):
 430             m.d.comb += [
 431                 self.out_tot.eq(Cat(self.in_a.m, 0) - Cat(self.in_b.m, 0)),
 432                 self.out_z.s.eq(self.in_a.s)
 433             ]
 434         # b mantissa greater than a, use b
 435         with m.Else():
 436             m.d.comb += [
 437                 self.out_tot.eq(Cat(self.in_b.m, 0) - Cat(self.in_a.m, 0)),
 438                 self.out_z.s.eq(self.in_b.s)
 439         ]
 440         return m
 441
 442
 443 class FPAddStage0(FPState):
 444     """ First stage of add.  covers same-sign (add) and subtract
 445         special-casing when mantissas are greater or equal, to
 446         give greatest accuracy.
 447     """
 448
 449     def __init__(self, width):
 450         FPState.__init__(self, "add_0")
 451         self.mod = FPAddStage0Mod(width)
 452         self.out_z = FPNumBase(width, False)
 453         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 454
 455     def action(self, m):
 456         m.next = "add_1"
 457         m.d.sync += self.z.copy(self.out_z)
 458
 459
 460 class FPAddStage1Mod(FPState):
 461     """ Second stage of add: preparation for normalisation.
 462         detects when tot sum is too big (tot[27] is kinda a carry bit)
 463     """
 464
 465     def __init__(self, width):
 466         self.out_norm = Signal(reset_less=True)
 467         self.in_z = FPNumBase(width, False)
 468         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 469         self.out_z = FPNumBase(width, False)
 470         self.out_of = Overflow()
 471
 472     def setup(self, m, in_tot, in_z, out_z, out_of):
 473         """ links module to inputs and outputs
 474         """
 475         m.d.comb += self.in_z.copy(in_z)
 476         m.d.comb += self.in_tot.eq(in_tot)
 477         m.d.comb += out_z.copy(self.out_z)
 478         m.d.comb += out_of.copy(self.out_of)
 479
 480     def elaborate(self, platform):
 481         m = Module()
 482         #m.submodules.norm1_in_overflow = self.in_of
 483         #m.submodules.norm1_out_overflow = self.out_of
 484         #m.submodules.norm1_in_z = self.in_z
 485         #m.submodules.norm1_out_z = self.out_z
 486         m.d.comb += self.out_z.copy(self.in_z)
 487         # tot[27] gets set when the sum overflows. shift result down
 488         with m.If(self.in_tot[-1]):
 489             m.d.comb += [
 490                 self.out_z.m.eq(self.in_tot[4:]),
 491                 self.out_of.m0.eq(self.in_tot[4]),
 492                 self.out_of.guard.eq(self.in_tot[3]),
 493                 self.out_of.round_bit.eq(self.in_tot[2]),
 494                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 495                 self.out_z.e.eq(self.in_z.e + 1)
 496         ]
 497         # tot[27] zero case
 498         with m.Else():
 499             m.d.comb += [
 500                 self.out_z.m.eq(self.in_tot[3:]),
 501                 self.out_of.m0.eq(self.in_tot[3]),
 502                 self.out_of.guard.eq(self.in_tot[2]),
 503                 self.out_of.round_bit.eq(self.in_tot[1]),
 504                 self.out_of.sticky.eq(self.in_tot[0])
 505         ]
 506         return m
 507
 508
 509 class FPAddStage1(FPState):
 510
 511     def __init__(self, width):
 512         FPState.__init__(self, "add_1")
 513         self.mod = FPAddStage1Mod(width)
 514         self.out_z = FPNumBase(width, False)
 515         self.out_of = Overflow()
 516
 517     def action(self, m):
 518         m.d.sync += self.of.copy(self.out_of)
 519         m.d.sync += self.z.copy(self.out_z)
 520         m.next = "normalise_1"
 521
 522
 523 class FPNorm1Mod:
 524
 525     def __init__(self, width):
 526         self.out_norm = Signal(reset_less=True)
 527         self.in_z = FPNumBase(width, False)
 528         self.out_z = FPNumBase(width, False)
 529         self.in_of = Overflow()
 530         self.out_of = Overflow()
 531
 532     def setup(self, m, in_z, out_z, in_of, out_of, out_norm):
 533         """ links module to inputs and outputs
 534         """
 535         m.d.comb += self.in_z.copy(in_z)
 536         m.d.comb += out_z.copy(self.out_z)
 537         m.d.comb += self.in_of.copy(in_of)
 538         m.d.comb += out_of.copy(self.out_of)
 539         m.d.comb += out_norm.eq(self.out_norm)
 540
 541     def elaborate(self, platform):
 542         m = Module()
 543         m.submodules.norm1_in_overflow = self.in_of
 544         m.submodules.norm1_out_overflow = self.out_of
 545         m.submodules.norm1_in_z = self.in_z
 546         m.submodules.norm1_out_z = self.out_z
 547         m.d.comb += self.out_z.copy(self.in_z)
 548         m.d.comb += self.out_of.copy(self.in_of)
 549         m.d.comb += self.out_norm.eq((self.in_z.m_msbzero) & \
 550                                      (self.in_z.exp_gt_n126))
 551         with m.If(self.out_norm):
 552             m.d.comb += [
 553                 self.out_z.e.eq(self.in_z.e - 1),  # DECREASE exponent
 554                 self.out_z.m.eq(self.in_z.m << 1), # shift mantissa UP
 555                 self.out_z.m[0].eq(self.in_of.guard), # steal guard (was tot[2])
 556                 self.out_of.guard.eq(self.in_of.round_bit), # round (was tot[1])
 557                 self.out_of.round_bit.eq(0),        # reset round bit
 558                 self.out_of.m0.eq(self.in_of.guard),
 559             ]
 560
 561         return m
 562
 563
 564 class FPNorm1(FPState):
 565
 566     def __init__(self, width):
 567         FPState.__init__(self, "normalise_1")
 568         self.mod = FPNorm1Mod(width)
 569         self.out_norm = Signal(reset_less=True)
 570         self.out_z = FPNumBase(width)
 571         self.out_of = Overflow()
 572
 573     def action(self, m):
 574         m.d.sync += self.of.copy(self.out_of)
 575         m.d.sync += self.z.copy(self.out_z)
 576         with m.If(~self.out_norm):
 577             m.next = "normalise_2"
 578
 579
 580 class FPNorm2Mod:
 581
 582     def __init__(self, width):
 583         self.out_norm = Signal(reset_less=True)
 584         self.in_z = FPNumBase(width, False)
 585         self.out_z = FPNumBase(width, False)
 586         self.in_of = Overflow()
 587         self.out_of = Overflow()
 588
 589     def setup(self, m, in_z, out_z, in_of, out_of, out_norm):
 590         """ links module to inputs and outputs
 591         """
 592         m.d.comb += self.in_z.copy(in_z)
 593         m.d.comb += out_z.copy(self.out_z)
 594         m.d.comb += self.in_of.copy(in_of)
 595         m.d.comb += out_of.copy(self.out_of)
 596         m.d.comb += out_norm.eq(self.out_norm)
 597
 598     def elaborate(self, platform):
 599         m = Module()
 600         m.submodules.norm2_in_overflow = self.in_of
 601         m.submodules.norm2_out_overflow = self.out_of
 602         m.submodules.norm2_in_z = self.in_z
 603         m.submodules.norm2_out_z = self.out_z
 604         m.d.comb += self.out_z.copy(self.in_z)
 605         m.d.comb += self.out_of.copy(self.in_of)
 606         m.d.comb += self.out_norm.eq(self.in_z.exp_lt_n126)
 607         with m.If(self.out_norm):
 608             m.d.comb += [
 609                 self.out_z.e.eq(self.in_z.e + 1),  # INCREASE exponent
 610                 self.out_z.m.eq(self.in_z.m >> 1), # shift mantissa DOWN
 611                 self.out_of.guard.eq(self.in_z.m[0]),
 612                 self.out_of.m0.eq(self.in_z.m[1]),
 613                 self.out_of.round_bit.eq(self.in_of.guard),
 614                 self.out_of.sticky.eq(self.in_of.sticky | self.in_of.round_bit)
 615             ]
 616
 617         return m
 618
 619
 620 class FPNorm2(FPState):
 621
 622     def __init__(self, width):
 623         FPState.__init__(self, "normalise_2")
 624         self.mod = FPNorm2Mod(width)
 625         self.out_norm = Signal(reset_less=True)
 626         self.out_z = FPNumBase(width)
 627         self.out_of = Overflow()
 628
 629     def action(self, m):
 630         #m.d.sync += self.of.copy(self.out_of)
 631         m.d.sync += self.z.copy(self.out_z)
 632         with m.If(~self.out_norm):
 633             m.next = "round"
 634
 635
 636 class FPRoundMod:
 637
 638     def __init__(self, width):
 639         self.in_roundz = Signal(reset_less=True)
 640         self.in_z = FPNumBase(width, False)
 641         self.out_z = FPNumBase(width, False)
 642
 643     def setup(self, m, in_z, out_z, in_of):
 644         """ links module to inputs and outputs
 645         """
 646         m.d.comb += self.in_z.copy(in_z)
 647         m.d.comb += out_z.copy(self.out_z)
 648         m.d.comb += self.in_roundz.eq(in_of.roundz)
 649
 650     def elaborate(self, platform):
 651         m = Module()
 652         m.d.comb += self.out_z.copy(self.in_z)
 653         with m.If(self.in_roundz):
 654             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 655             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 656                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 657         return m
 658
 659
 660 class FPRound(FPState):
 661
 662     def __init__(self, width):
 663         FPState.__init__(self, "round")
 664         self.mod = FPRoundMod(width)
 665         self.out_z = FPNumBase(width)
 666
 667     def action(self, m):
 668         m.d.sync += self.z.copy(self.out_z)
 669         m.next = "corrections"
 670
 671
 672 class FPCorrectionsMod:
 673
 674     def __init__(self, width):
 675         self.in_z = FPNumOut(width, False)
 676         self.out_z = FPNumOut(width, False)
 677
 678     def setup(self, m, in_z, out_z):
 679         """ links module to inputs and outputs
 680         """
 681         m.d.comb += self.in_z.copy(in_z)
 682         m.d.comb += out_z.copy(self.out_z)
 683
 684     def elaborate(self, platform):
 685         m = Module()
 686         m.submodules.corr_in_z = self.in_z
 687         m.submodules.corr_out_z = self.out_z
 688         m.d.comb += self.out_z.copy(self.in_z)
 689         with m.If(self.in_z.is_denormalised):
 690             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 691
 692         #        with m.If(self.in_z.is_overflowed):
 693         #            m.d.comb += self.out_z.inf(self.in_z.s)
 694         #        with m.Else():
 695         #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 696         return m
 697
 698
 699 class FPCorrections(FPState):
 700
 701     def __init__(self, width):
 702         FPState.__init__(self, "corrections")
 703         self.mod = FPCorrectionsMod(width)
 704         self.out_z = FPNumBase(width)
 705
 706     def action(self, m):
 707         m.d.sync += self.z.copy(self.out_z)
 708         m.next = "pack"
 709
 710
 711 class FPPackMod:
 712
 713     def __init__(self, width):
 714         self.in_z = FPNumOut(width, False)
 715         self.out_z = FPNumOut(width, False)
 716
 717     def setup(self, m, in_z, out_z):
 718         """ links module to inputs and outputs
 719         """
 720         m.d.comb += self.in_z.copy(in_z)
 721         m.d.comb += out_z.v.eq(self.out_z.v)
 722
 723     def elaborate(self, platform):
 724         m = Module()
 725         m.submodules.pack_in_z = self.in_z
 726         with m.If(self.in_z.is_overflowed):
 727             m.d.comb += self.out_z.inf(self.in_z.s)
 728         with m.Else():
 729             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 730         return m
 731
 732
 733 class FPPack(FPState):
 734
 735     def __init__(self, width):
 736         FPState.__init__(self, "pack")
 737         self.mod = FPPackMod(width)
 738         self.out_z = FPNumOut(width, False)
 739
 740     def action(self, m):
 741         m.d.sync += self.z.v.eq(self.out_z.v)
 742         m.next = "put_z"
 743
 744
 745 class FPPutZ(FPState):
 746
 747     def action(self, m):
 748         self.put_z(m, self.z, self.out_z, "get_a")
 749
 750
 751 class FPADD:
 752
 753     def __init__(self, width, single_cycle=False):
 754         self.width = width
 755         self.single_cycle = single_cycle
 756
 757         self.in_a  = FPOp(width)
 758         self.in_b  = FPOp(width)
 759         self.out_z = FPOp(width)
 760
 761         self.states = []
 762
 763     def add_state(self, state):
 764         self.states.append(state)
 765         return state
 766
 767     def get_fragment(self, platform=None):
 768         """ creates the HDL code-fragment for FPAdd
 769         """
 770         m = Module()
 771
 772         # Latches
 773         z = FPNumOut(self.width, False)
 774         m.submodules.fpnum_z = z
 775
 776         w = z.m_width + 4
 777
 778         of = Overflow()
 779         m.submodules.overflow = of
 780
 781         geta = self.add_state(FPGetOp("get_a", "get_b",
 782                                       self.in_a, self.width))
 783         a = geta.out_op
 784         geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
 785         m.submodules.get_a = geta.mod
 786
 787         getb = self.add_state(FPGetOp("get_b", "special_cases",
 788                                       self.in_b, self.width))
 789         b = getb.out_op
 790         getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
 791         m.submodules.get_b = getb.mod
 792
 793         sc = self.add_state(FPAddSpecialCases(self.width))
 794         sc.set_inputs({"a": a, "b": b})
 795         sc.set_outputs({"z": z})
 796         sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
 797         m.submodules.specialcases = sc.mod
 798
 799         dn = self.add_state(FPAddDeNorm(self.width))
 800         dn.set_inputs({"a": a, "b": b})
 801         #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 802         dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
 803         m.submodules.denormalise = dn.mod
 804
 805         if self.single_cycle:
 806             alm = self.add_state(FPAddAlignSingle(self.width))
 807             alm.set_inputs({"a": a, "b": b})
 808             alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 809             alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
 810         else:
 811             alm = self.add_state(FPAddAlignMulti(self.width))
 812             alm.set_inputs({"a": a, "b": b})
 813             #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 814             alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
 815         m.submodules.align = alm.mod
 816
 817         add0 = self.add_state(FPAddStage0(self.width))
 818         add0.set_inputs({"a": alm.out_a, "b": alm.out_b})
 819         add0.set_outputs({"z": z})
 820         add0.mod.setup(m, alm.out_a, alm.out_b, z, add0.out_z, add0.out_tot)
 821         m.submodules.add0 = add0.mod
 822
 823         add1 = self.add_state(FPAddStage1(self.width))
 824         add1.set_inputs({"tot": add0.out_tot, "z": add0.out_z})
 825         add1.set_outputs({"z": z, "of": of})  # XXX Z as output
 826         add1.mod.setup(m, add0.out_tot, z, add1.out_z, add1.out_of)
 827         m.submodules.add1 = add1.mod
 828
 829         n1 = self.add_state(FPNorm1(self.width))
 830         n1.set_inputs({"z": z, "of": of})  # XXX Z as output
 831         n1.set_outputs({"z": z})  # XXX Z as output
 832         n1.mod.setup(m, z, n1.out_z, of, n1.out_of, n1.out_norm)
 833         m.submodules.normalise_1 = n1.mod
 834
 835         n2 = self.add_state(FPNorm2(self.width))
 836         n2.set_inputs({"z": n1.out_z, "of": n1.out_of})
 837         n2.set_outputs({"z": z})
 838         n2.mod.setup(m, n1.out_z, n2.out_z, n1.out_of, n2.out_of, n2.out_norm)
 839         m.submodules.normalise_2 = n2.mod
 840
 841         rn = self.add_state(FPRound(self.width))
 842         rn.set_inputs({"z": n2.out_z, "of": n2.out_of})
 843         rn.set_outputs({"z": z})
 844         rn.mod.setup(m, n2.out_z, rn.out_z, of)
 845         m.submodules.roundz = rn.mod
 846
 847         cor = self.add_state(FPCorrections(self.width))
 848         cor.set_inputs({"z": z})  # XXX Z as output
 849         cor.set_outputs({"z": z})  # XXX Z as output
 850         cor.mod.setup(m, z, cor.out_z)
 851         m.submodules.corrections = cor.mod
 852
 853         pa = self.add_state(FPPack(self.width))
 854         pa.set_inputs({"z": z})  # XXX Z as output
 855         pa.set_outputs({"z": z})  # XXX Z as output
 856         pa.mod.setup(m, z, pa.out_z)
 857         m.submodules.pack = pa.mod
 858
 859         pz = self.add_state(FPPutZ("put_z"))
 860         pz.set_inputs({"z": z})
 861         pz.set_outputs({"out_z": self.out_z})
 862
 863         with m.FSM() as fsm:
 864
 865             for state in self.states:
 866                 with m.State(state.state_from):
 867                     state.action(m)
 868
 869         return m
 870
 871
 872 if __name__ == "__main__":
 873     alu = FPADD(width=32)
 874     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 875
 876
 877     # works... but don't use, just do "python fname.py convert -t v"
 878     #print (verilog.convert(alu, ports=[
 879     #                        ports=alu.in_a.ports() + \
 880     #                              alu.in_b.ports() + \
 881     #                              alu.out_z.ports())