src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain, UnbufferedPipeline
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPSCData:
 264
 265     def __init__(self, width, id_wid):
 266         self.a = FPNumBase(width, True)
 267         self.b = FPNumBase(width, True)
 268         self.z = FPNumOut(width, False)
 269         self.oz = Signal(width, reset_less=True)
 270         self.out_do_z = Signal(reset_less=True)
 271         self.mid = Signal(id_wid, reset_less=True)
 272
 273     def eq(self, i):
 274         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 275                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 276
 277
 278 class FPAddSpecialCasesMod:
 279     """ special cases: NaNs, infs, zeros, denormalised
 280         NOTE: some of these are unique to add.  see "Special Operations"
 281         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 282     """
 283
 284     def __init__(self, width, id_wid):
 285         self.width = width
 286         self.id_wid = id_wid
 287         self.i = self.ispec()
 288         self.o = self.ospec()
 289
 290     def ispec(self):
 291         return FPNumBase2Ops(self.width, self.id_wid)
 292
 293     def ospec(self):
 294         return FPSCData(self.width, self.id_wid)
 295
 296     def setup(self, m, i):
 297         """ links module to inputs and outputs
 298         """
 299         m.submodules.specialcases = self
 300         m.d.comb += self.i.eq(i)
 301
 302     def elaborate(self, platform):
 303         m = Module()
 304
 305         m.submodules.sc_in_a = self.i.a
 306         m.submodules.sc_in_b = self.i.b
 307         m.submodules.sc_out_z = self.o.z
 308
 309         s_nomatch = Signal()
 310         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 311
 312         m_match = Signal()
 313         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 314
 315         # if a is NaN or b is NaN return NaN
 316         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 317             m.d.comb += self.o.out_do_z.eq(1)
 318             m.d.comb += self.o.z.nan(0)
 319
 320         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 321         # under review
 322
 323         ## if a is zero and b is NaN return -b
 324         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 325         #    m.d.comb += self.o.out_do_z.eq(1)
 326         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 327
 328         ## if b is zero and a is NaN return -a
 329         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 330         #    m.d.comb += self.o.out_do_z.eq(1)
 331         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 332
 333         ## if a is -zero and b is NaN return -b
 334         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 335         #    m.d.comb += self.o.out_do_z.eq(1)
 336         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 337
 338         ## if b is -zero and a is NaN return -a
 339         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 340         #    m.d.comb += self.o.out_do_z.eq(1)
 341         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 342
 343         # if a is inf return inf (or NaN)
 344         with m.Elif(self.i.a.is_inf):
 345             m.d.comb += self.o.out_do_z.eq(1)
 346             m.d.comb += self.o.z.inf(self.i.a.s)
 347             # if a is inf and signs don't match return NaN
 348             with m.If(self.i.b.exp_128 & s_nomatch):
 349                 m.d.comb += self.o.z.nan(0)
 350
 351         # if b is inf return inf
 352         with m.Elif(self.i.b.is_inf):
 353             m.d.comb += self.o.out_do_z.eq(1)
 354             m.d.comb += self.o.z.inf(self.i.b.s)
 355
 356         # if a is zero and b zero return signed-a/b
 357         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 358             m.d.comb += self.o.out_do_z.eq(1)
 359             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 360                                           self.i.b.e,
 361                                           self.i.b.m[3:-1])
 362
 363         # if a is zero return b
 364         with m.Elif(self.i.a.is_zero):
 365             m.d.comb += self.o.out_do_z.eq(1)
 366             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 367                                       self.i.b.m[3:-1])
 368
 369         # if b is zero return a
 370         with m.Elif(self.i.b.is_zero):
 371             m.d.comb += self.o.out_do_z.eq(1)
 372             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 373                                       self.i.a.m[3:-1])
 374
 375         # if a equal to -b return zero (+ve zero)
 376         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 377             m.d.comb += self.o.out_do_z.eq(1)
 378             m.d.comb += self.o.z.zero(0)
 379
 380         # Denormalised Number checks next, so pass a/b data through
 381         with m.Else():
 382             m.d.comb += self.o.out_do_z.eq(0)
 383             m.d.comb += self.o.a.eq(self.i.a)
 384             m.d.comb += self.o.b.eq(self.i.b)
 385
 386         m.d.comb += self.o.oz.eq(self.o.z.v)
 387         m.d.comb += self.o.mid.eq(self.i.mid)
 388
 389         return m
 390
 391
 392 class FPID:
 393     def __init__(self, id_wid):
 394         self.id_wid = id_wid
 395         if self.id_wid:
 396             self.in_mid = Signal(id_wid, reset_less=True)
 397             self.out_mid = Signal(id_wid, reset_less=True)
 398         else:
 399             self.in_mid = None
 400             self.out_mid = None
 401
 402     def idsync(self, m):
 403         if self.id_wid is not None:
 404             m.d.sync += self.out_mid.eq(self.in_mid)
 405
 406
 407 class FPAddSpecialCases(FPState):
 408     """ special cases: NaNs, infs, zeros, denormalised
 409         NOTE: some of these are unique to add.  see "Special Operations"
 410         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 411     """
 412
 413     def __init__(self, width, id_wid):
 414         FPState.__init__(self, "special_cases")
 415         self.mod = FPAddSpecialCasesMod(width)
 416         self.out_z = self.mod.ospec()
 417         self.out_do_z = Signal(reset_less=True)
 418
 419     def setup(self, m, i):
 420         """ links module to inputs and outputs
 421         """
 422         self.mod.setup(m, i, self.out_do_z)
 423         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 424         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 425
 426     def action(self, m):
 427         self.idsync(m)
 428         with m.If(self.out_do_z):
 429             m.next = "put_z"
 430         with m.Else():
 431             m.next = "denormalise"
 432
 433
 434 class FPAddSpecialCasesDeNorm(FPState):
 435     """ special cases: NaNs, infs, zeros, denormalised
 436         NOTE: some of these are unique to add.  see "Special Operations"
 437         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 438     """
 439
 440     def __init__(self, width, id_wid):
 441         FPState.__init__(self, "special_cases")
 442         self.smod = FPAddSpecialCasesMod(width, id_wid)
 443         self.dmod = FPAddDeNormMod(width, id_wid)
 444         self.o = self.ospec()
 445
 446     def ispec(self):
 447         return self.smod.ispec()
 448
 449     def ospec(self):
 450         return self.dmod.ospec()
 451
 452     def setup(self, m, i):
 453         """ links module to inputs and outputs
 454         """
 455         # these only needed for break-out (early-out)
 456         # out_z = self.smod.ospec()
 457         # out_do_z = Signal(reset_less=True)
 458         self.smod.setup(m, i)
 459         self.dmod.setup(m, self.smod.o)
 460         #m.d.comb += out_do_z.eq(self.smod.o.out_do_z)
 461
 462         # out_do_z=True, only needed for early-out (split pipeline)
 463         #m.d.sync += out_z.z.v.eq(self.smod.o.z.v) # only take output
 464         #m.d.sync += out_z.mid.eq(self.smod.o.mid)  # (and mid)
 465
 466         # out_do_z=False
 467         m.d.sync += self.o.eq(self.dmod.o)
 468
 469     def process(self, i):
 470         return self.o
 471
 472     def action(self, m):
 473         #with m.If(self.out_do_z):
 474         #    m.next = "put_z"
 475         #with m.Else():
 476             m.next = "align"
 477
 478
 479 class FPAddDeNormMod(FPState):
 480
 481     def __init__(self, width, id_wid):
 482         self.width = width
 483         self.id_wid = id_wid
 484         self.i = self.ispec()
 485         self.o = self.ospec()
 486
 487     def ispec(self):
 488         return FPSCData(self.width, self.id_wid)
 489
 490     def ospec(self):
 491         return FPSCData(self.width, self.id_wid)
 492
 493     def setup(self, m, i):
 494         """ links module to inputs and outputs
 495         """
 496         m.submodules.denormalise = self
 497         m.d.comb += self.i.eq(i)
 498
 499     def elaborate(self, platform):
 500         m = Module()
 501         m.submodules.denorm_in_a = self.i.a
 502         m.submodules.denorm_in_b = self.i.b
 503         m.submodules.denorm_out_a = self.o.a
 504         m.submodules.denorm_out_b = self.o.b
 505
 506         with m.If(~self.i.out_do_z):
 507             # XXX hmmm, don't like repeating identical code
 508             m.d.comb += self.o.a.eq(self.i.a)
 509             with m.If(self.i.a.exp_n127):
 510                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 511             with m.Else():
 512                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 513
 514             m.d.comb += self.o.b.eq(self.i.b)
 515             with m.If(self.i.b.exp_n127):
 516                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 517             with m.Else():
 518                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 519
 520         m.d.comb += self.o.mid.eq(self.i.mid)
 521         m.d.comb += self.o.z.eq(self.i.z)
 522         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 523         m.d.comb += self.o.oz.eq(self.i.oz)
 524
 525         return m
 526
 527
 528 class FPAddDeNorm(FPState):
 529
 530     def __init__(self, width, id_wid):
 531         FPState.__init__(self, "denormalise")
 532         self.mod = FPAddDeNormMod(width)
 533         self.out_a = FPNumBase(width)
 534         self.out_b = FPNumBase(width)
 535
 536     def setup(self, m, i):
 537         """ links module to inputs and outputs
 538         """
 539         self.mod.setup(m, i)
 540
 541         m.d.sync += self.out_a.eq(self.mod.out_a)
 542         m.d.sync += self.out_b.eq(self.mod.out_b)
 543
 544     def action(self, m):
 545         # Denormalised Number checks
 546         m.next = "align"
 547
 548
 549 class FPAddAlignMultiMod(FPState):
 550
 551     def __init__(self, width):
 552         self.in_a = FPNumBase(width)
 553         self.in_b = FPNumBase(width)
 554         self.out_a = FPNumIn(None, width)
 555         self.out_b = FPNumIn(None, width)
 556         self.exp_eq = Signal(reset_less=True)
 557
 558     def elaborate(self, platform):
 559         # This one however (single-cycle) will do the shift
 560         # in one go.
 561
 562         m = Module()
 563
 564         m.submodules.align_in_a = self.in_a
 565         m.submodules.align_in_b = self.in_b
 566         m.submodules.align_out_a = self.out_a
 567         m.submodules.align_out_b = self.out_b
 568
 569         # NOTE: this does *not* do single-cycle multi-shifting,
 570         #       it *STAYS* in the align state until exponents match
 571
 572         # exponent of a greater than b: shift b down
 573         m.d.comb += self.exp_eq.eq(0)
 574         m.d.comb += self.out_a.eq(self.in_a)
 575         m.d.comb += self.out_b.eq(self.in_b)
 576         agtb = Signal(reset_less=True)
 577         altb = Signal(reset_less=True)
 578         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 579         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 580         with m.If(agtb):
 581             m.d.comb += self.out_b.shift_down(self.in_b)
 582         # exponent of b greater than a: shift a down
 583         with m.Elif(altb):
 584             m.d.comb += self.out_a.shift_down(self.in_a)
 585         # exponents equal: move to next stage.
 586         with m.Else():
 587             m.d.comb += self.exp_eq.eq(1)
 588         return m
 589
 590
 591 class FPAddAlignMulti(FPState):
 592
 593     def __init__(self, width, id_wid):
 594         FPState.__init__(self, "align")
 595         self.mod = FPAddAlignMultiMod(width)
 596         self.out_a = FPNumIn(None, width)
 597         self.out_b = FPNumIn(None, width)
 598         self.exp_eq = Signal(reset_less=True)
 599
 600     def setup(self, m, in_a, in_b):
 601         """ links module to inputs and outputs
 602         """
 603         m.submodules.align = self.mod
 604         m.d.comb += self.mod.in_a.eq(in_a)
 605         m.d.comb += self.mod.in_b.eq(in_b)
 606         #m.d.comb += self.out_a.eq(self.mod.out_a)
 607         #m.d.comb += self.out_b.eq(self.mod.out_b)
 608         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 609         m.d.sync += self.out_a.eq(self.mod.out_a)
 610         m.d.sync += self.out_b.eq(self.mod.out_b)
 611
 612     def action(self, m):
 613         with m.If(self.exp_eq):
 614             m.next = "add_0"
 615
 616
 617 class FPNumIn2Ops:
 618
 619     def __init__(self, width, id_wid):
 620         self.a = FPNumIn(None, width)
 621         self.b = FPNumIn(None, width)
 622         self.z = FPNumOut(width, False)
 623         self.out_do_z = Signal(reset_less=True)
 624         self.oz = Signal(width, reset_less=True)
 625         self.mid = Signal(id_wid, reset_less=True)
 626
 627     def eq(self, i):
 628         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 629                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 630
 631
 632 class FPAddAlignSingleMod:
 633
 634     def __init__(self, width, id_wid):
 635         self.width = width
 636         self.id_wid = id_wid
 637         self.i = self.ispec()
 638         self.o = self.ospec()
 639
 640     def ispec(self):
 641         return FPSCData(self.width, self.id_wid)
 642
 643     def ospec(self):
 644         return FPNumIn2Ops(self.width, self.id_wid)
 645
 646     def process(self, i):
 647         return self.o
 648
 649     def setup(self, m, i):
 650         """ links module to inputs and outputs
 651         """
 652         m.submodules.align = self
 653         m.d.comb += self.i.eq(i)
 654
 655     def elaborate(self, platform):
 656         """ Aligns A against B or B against A, depending on which has the
 657             greater exponent.  This is done in a *single* cycle using
 658             variable-width bit-shift
 659
 660             the shifter used here is quite expensive in terms of gates.
 661             Mux A or B in (and out) into temporaries, as only one of them
 662             needs to be aligned against the other
 663         """
 664         m = Module()
 665
 666         m.submodules.align_in_a = self.i.a
 667         m.submodules.align_in_b = self.i.b
 668         m.submodules.align_out_a = self.o.a
 669         m.submodules.align_out_b = self.o.b
 670
 671         # temporary (muxed) input and output to be shifted
 672         t_inp = FPNumBase(self.width)
 673         t_out = FPNumIn(None, self.width)
 674         espec = (len(self.i.a.e), True)
 675         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 676         m.submodules.align_t_in = t_inp
 677         m.submodules.align_t_out = t_out
 678         m.submodules.multishift_r = msr
 679
 680         ediff = Signal(espec, reset_less=True)
 681         ediffr = Signal(espec, reset_less=True)
 682         tdiff = Signal(espec, reset_less=True)
 683         elz = Signal(reset_less=True)
 684         egz = Signal(reset_less=True)
 685
 686         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 687         m.d.comb += msr.inp.eq(t_inp.m)
 688         m.d.comb += msr.diff.eq(tdiff)
 689         m.d.comb += t_out.m.eq(msr.m)
 690         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 691         m.d.comb += t_out.s.eq(t_inp.s)
 692
 693         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 694         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 695         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 696         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 697
 698         # default: A-exp == B-exp, A and B untouched (fall through)
 699         m.d.comb += self.o.a.eq(self.i.a)
 700         m.d.comb += self.o.b.eq(self.i.b)
 701         # only one shifter (muxed)
 702         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 703         # exponent of a greater than b: shift b down
 704         with m.If(~self.i.out_do_z):
 705             with m.If(egz):
 706                 m.d.comb += [t_inp.eq(self.i.b),
 707                              tdiff.eq(ediff),
 708                              self.o.b.eq(t_out),
 709                              self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 710                             ]
 711             # exponent of b greater than a: shift a down
 712             with m.Elif(elz):
 713                 m.d.comb += [t_inp.eq(self.i.a),
 714                              tdiff.eq(ediffr),
 715                              self.o.a.eq(t_out),
 716                              self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 717                             ]
 718
 719         m.d.comb += self.o.mid.eq(self.i.mid)
 720         m.d.comb += self.o.z.eq(self.i.z)
 721         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 722         m.d.comb += self.o.oz.eq(self.i.oz)
 723
 724         return m
 725
 726
 727 class FPAddAlignSingle(FPState):
 728
 729     def __init__(self, width, id_wid):
 730         FPState.__init__(self, "align")
 731         self.mod = FPAddAlignSingleMod(width, id_wid)
 732         self.out_a = FPNumIn(None, width)
 733         self.out_b = FPNumIn(None, width)
 734
 735     def setup(self, m, i):
 736         """ links module to inputs and outputs
 737         """
 738         self.mod.setup(m, i)
 739
 740         # NOTE: could be done as comb
 741         m.d.sync += self.out_a.eq(self.mod.out_a)
 742         m.d.sync += self.out_b.eq(self.mod.out_b)
 743
 744     def action(self, m):
 745         m.next = "add_0"
 746
 747
 748 class FPAddAlignSingleAdd(FPState):
 749
 750     def __init__(self, width, id_wid):
 751         FPState.__init__(self, "align")
 752         self.width = width
 753         self.id_wid = id_wid
 754         self.a1o = self.ospec()
 755
 756     def ispec(self):
 757         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 758
 759     def ospec(self):
 760         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 761
 762     def setup(self, m, i):
 763         """ links module to inputs and outputs
 764         """
 765
 766         # chain AddAlignSingle, AddStage0 and AddStage1
 767         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 768         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 769         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 770
 771         chain = StageChain([mod, a0mod, a1mod])
 772         chain.setup(m, i)
 773
 774         m.d.sync += self.a1o.eq(a1mod.o)
 775
 776     def process(self, i):
 777         return self.a1o
 778
 779     def action(self, m):
 780         m.next = "normalise_1"
 781
 782
 783 class FPAddStage0Data:
 784
 785     def __init__(self, width, id_wid):
 786         self.z = FPNumBase(width, False)
 787         self.out_do_z = Signal(reset_less=True)
 788         self.oz = Signal(width, reset_less=True)
 789         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 790         self.mid = Signal(id_wid, reset_less=True)
 791
 792     def eq(self, i):
 793         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 794                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 795
 796
 797 class FPAddStage0Mod:
 798
 799     def __init__(self, width, id_wid):
 800         self.width = width
 801         self.id_wid = id_wid
 802         self.i = self.ispec()
 803         self.o = self.ospec()
 804
 805     def ispec(self):
 806         return FPSCData(self.width, self.id_wid)
 807
 808     def ospec(self):
 809         return FPAddStage0Data(self.width, self.id_wid)
 810
 811     def process(self, i):
 812         return self.o
 813
 814     def setup(self, m, i):
 815         """ links module to inputs and outputs
 816         """
 817         m.submodules.add0 = self
 818         m.d.comb += self.i.eq(i)
 819
 820     def elaborate(self, platform):
 821         m = Module()
 822         m.submodules.add0_in_a = self.i.a
 823         m.submodules.add0_in_b = self.i.b
 824         m.submodules.add0_out_z = self.o.z
 825
 826         # store intermediate tests (and zero-extended mantissas)
 827         seq = Signal(reset_less=True)
 828         mge = Signal(reset_less=True)
 829         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 830         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 831         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 832                      mge.eq(self.i.a.m >= self.i.b.m),
 833                      am0.eq(Cat(self.i.a.m, 0)),
 834                      bm0.eq(Cat(self.i.b.m, 0))
 835                     ]
 836         # same-sign (both negative or both positive) add mantissas
 837         with m.If(~self.i.out_do_z):
 838             m.d.comb += self.o.z.e.eq(self.i.a.e)
 839             with m.If(seq):
 840                 m.d.comb += [
 841                     self.o.tot.eq(am0 + bm0),
 842                     self.o.z.s.eq(self.i.a.s)
 843                 ]
 844             # a mantissa greater than b, use a
 845             with m.Elif(mge):
 846                 m.d.comb += [
 847                     self.o.tot.eq(am0 - bm0),
 848                     self.o.z.s.eq(self.i.a.s)
 849                 ]
 850             # b mantissa greater than a, use b
 851             with m.Else():
 852                 m.d.comb += [
 853                     self.o.tot.eq(bm0 - am0),
 854                     self.o.z.s.eq(self.i.b.s)
 855             ]
 856
 857         m.d.comb += self.o.oz.eq(self.i.oz)
 858         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 859         m.d.comb += self.o.mid.eq(self.i.mid)
 860         return m
 861
 862
 863 class FPAddStage0(FPState):
 864     """ First stage of add.  covers same-sign (add) and subtract
 865         special-casing when mantissas are greater or equal, to
 866         give greatest accuracy.
 867     """
 868
 869     def __init__(self, width, id_wid):
 870         FPState.__init__(self, "add_0")
 871         self.mod = FPAddStage0Mod(width)
 872         self.o = self.mod.ospec()
 873
 874     def setup(self, m, i):
 875         """ links module to inputs and outputs
 876         """
 877         self.mod.setup(m, i)
 878
 879         # NOTE: these could be done as combinatorial (merge add0+add1)
 880         m.d.sync += self.o.eq(self.mod.o)
 881
 882     def action(self, m):
 883         m.next = "add_1"
 884
 885
 886 class FPAddStage1Data:
 887
 888     def __init__(self, width, id_wid):
 889         self.z = FPNumBase(width, False)
 890         self.out_do_z = Signal(reset_less=True)
 891         self.oz = Signal(width, reset_less=True)
 892         self.of = Overflow()
 893         self.mid = Signal(id_wid, reset_less=True)
 894
 895     def eq(self, i):
 896         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
 897                 self.of.eq(i.of), self.mid.eq(i.mid)]
 898
 899
 900
 901 class FPAddStage1Mod(FPState):
 902     """ Second stage of add: preparation for normalisation.
 903         detects when tot sum is too big (tot[27] is kinda a carry bit)
 904     """
 905
 906     def __init__(self, width, id_wid):
 907         self.width = width
 908         self.id_wid = id_wid
 909         self.i = self.ispec()
 910         self.o = self.ospec()
 911
 912     def ispec(self):
 913         return FPAddStage0Data(self.width, self.id_wid)
 914
 915     def ospec(self):
 916         return FPAddStage1Data(self.width, self.id_wid)
 917
 918     def process(self, i):
 919         return self.o
 920
 921     def setup(self, m, i):
 922         """ links module to inputs and outputs
 923         """
 924         m.submodules.add1 = self
 925         m.submodules.add1_out_overflow = self.o.of
 926
 927         m.d.comb += self.i.eq(i)
 928
 929     def elaborate(self, platform):
 930         m = Module()
 931         #m.submodules.norm1_in_overflow = self.in_of
 932         #m.submodules.norm1_out_overflow = self.out_of
 933         #m.submodules.norm1_in_z = self.in_z
 934         #m.submodules.norm1_out_z = self.out_z
 935         m.d.comb += self.o.z.eq(self.i.z)
 936         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 937         with m.If(~self.i.out_do_z):
 938             with m.If(self.i.tot[-1]):
 939                 m.d.comb += [
 940                     self.o.z.m.eq(self.i.tot[4:]),
 941                     self.o.of.m0.eq(self.i.tot[4]),
 942                     self.o.of.guard.eq(self.i.tot[3]),
 943                     self.o.of.round_bit.eq(self.i.tot[2]),
 944                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 945                     self.o.z.e.eq(self.i.z.e + 1)
 946             ]
 947             # tot[-1] (MSB) zero case
 948             with m.Else():
 949                 m.d.comb += [
 950                     self.o.z.m.eq(self.i.tot[3:]),
 951                     self.o.of.m0.eq(self.i.tot[3]),
 952                     self.o.of.guard.eq(self.i.tot[2]),
 953                     self.o.of.round_bit.eq(self.i.tot[1]),
 954                     self.o.of.sticky.eq(self.i.tot[0])
 955             ]
 956
 957         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 958         m.d.comb += self.o.oz.eq(self.i.oz)
 959         m.d.comb += self.o.mid.eq(self.i.mid)
 960
 961         return m
 962
 963
 964 class FPAddStage1(FPState):
 965
 966     def __init__(self, width, id_wid):
 967         FPState.__init__(self, "add_1")
 968         self.mod = FPAddStage1Mod(width)
 969         self.out_z = FPNumBase(width, False)
 970         self.out_of = Overflow()
 971         self.norm_stb = Signal()
 972
 973     def setup(self, m, i):
 974         """ links module to inputs and outputs
 975         """
 976         self.mod.setup(m, i)
 977
 978         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 979
 980         m.d.sync += self.out_of.eq(self.mod.out_of)
 981         m.d.sync += self.out_z.eq(self.mod.out_z)
 982         m.d.sync += self.norm_stb.eq(1)
 983
 984     def action(self, m):
 985         m.next = "normalise_1"
 986
 987
 988 class FPNormaliseModSingle:
 989
 990     def __init__(self, width):
 991         self.width = width
 992         self.in_z = self.ispec()
 993         self.out_z = self.ospec()
 994
 995     def ispec(self):
 996         return FPNumBase(self.width, False)
 997
 998     def ospec(self):
 999         return FPNumBase(self.width, False)
1000
1001     def setup(self, m, i):
1002         """ links module to inputs and outputs
1003         """
1004         m.submodules.normalise = self
1005         m.d.comb += self.i.eq(i)
1006
1007     def elaborate(self, platform):
1008         m = Module()
1009
1010         mwid = self.out_z.m_width+2
1011         pe = PriorityEncoder(mwid)
1012         m.submodules.norm_pe = pe
1013
1014         m.submodules.norm1_out_z = self.out_z
1015         m.submodules.norm1_in_z = self.in_z
1016
1017         in_z = FPNumBase(self.width, False)
1018         in_of = Overflow()
1019         m.submodules.norm1_insel_z = in_z
1020         m.submodules.norm1_insel_overflow = in_of
1021
1022         espec = (len(in_z.e), True)
1023         ediff_n126 = Signal(espec, reset_less=True)
1024         msr = MultiShiftRMerge(mwid, espec)
1025         m.submodules.multishift_r = msr
1026
1027         m.d.comb += in_z.eq(self.in_z)
1028         m.d.comb += in_of.eq(self.in_of)
1029         # initialise out from in (overridden below)
1030         m.d.comb += self.out_z.eq(in_z)
1031         m.d.comb += self.out_of.eq(in_of)
1032         # normalisation decrease condition
1033         decrease = Signal(reset_less=True)
1034         m.d.comb += decrease.eq(in_z.m_msbzero)
1035         # decrease exponent
1036         with m.If(decrease):
1037             # *sigh* not entirely obvious: count leading zeros (clz)
1038             # with a PriorityEncoder: to find from the MSB
1039             # we reverse the order of the bits.
1040             temp_m = Signal(mwid, reset_less=True)
1041             temp_s = Signal(mwid+1, reset_less=True)
1042             clz = Signal((len(in_z.e), True), reset_less=True)
1043             m.d.comb += [
1044                 # cat round and guard bits back into the mantissa
1045                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1046                 pe.i.eq(temp_m[::-1]),          # inverted
1047                 clz.eq(pe.o),                   # count zeros from MSB down
1048                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1049                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1050                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1051             ]
1052
1053         return m
1054
1055 class FPNorm1Data:
1056
1057     def __init__(self, width, id_wid):
1058         self.roundz = Signal(reset_less=True)
1059         self.z = FPNumBase(width, False)
1060         self.out_do_z = Signal(reset_less=True)
1061         self.oz = Signal(width, reset_less=True)
1062         self.mid = Signal(id_wid, reset_less=True)
1063
1064     def eq(self, i):
1065         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1066                 self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1067
1068
1069 class FPNorm1ModSingle:
1070
1071     def __init__(self, width, id_wid):
1072         self.width = width
1073         self.id_wid = id_wid
1074         self.i = self.ispec()
1075         self.o = self.ospec()
1076
1077     def ispec(self):
1078         return FPAddStage1Data(self.width, self.id_wid)
1079
1080     def ospec(self):
1081         return FPNorm1Data(self.width, self.id_wid)
1082
1083     def setup(self, m, i):
1084         """ links module to inputs and outputs
1085         """
1086         m.submodules.normalise_1 = self
1087         m.d.comb += self.i.eq(i)
1088
1089     def process(self, i):
1090         return self.o
1091
1092     def elaborate(self, platform):
1093         m = Module()
1094
1095         mwid = self.o.z.m_width+2
1096         pe = PriorityEncoder(mwid)
1097         m.submodules.norm_pe = pe
1098
1099         of = Overflow()
1100         m.d.comb += self.o.roundz.eq(of.roundz)
1101
1102         m.submodules.norm1_out_z = self.o.z
1103         m.submodules.norm1_out_overflow = of
1104         m.submodules.norm1_in_z = self.i.z
1105         m.submodules.norm1_in_overflow = self.i.of
1106
1107         i = self.ispec()
1108         m.submodules.norm1_insel_z = i.z
1109         m.submodules.norm1_insel_overflow = i.of
1110
1111         espec = (len(i.z.e), True)
1112         ediff_n126 = Signal(espec, reset_less=True)
1113         msr = MultiShiftRMerge(mwid, espec)
1114         m.submodules.multishift_r = msr
1115
1116         m.d.comb += i.eq(self.i)
1117         # initialise out from in (overridden below)
1118         m.d.comb += self.o.z.eq(i.z)
1119         m.d.comb += of.eq(i.of)
1120         # normalisation increase/decrease conditions
1121         decrease = Signal(reset_less=True)
1122         increase = Signal(reset_less=True)
1123         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1124         m.d.comb += increase.eq(i.z.exp_lt_n126)
1125         # decrease exponent
1126         with m.If(~self.i.out_do_z):
1127             with m.If(decrease):
1128                 # *sigh* not entirely obvious: count leading zeros (clz)
1129                 # with a PriorityEncoder: to find from the MSB
1130                 # we reverse the order of the bits.
1131                 temp_m = Signal(mwid, reset_less=True)
1132                 temp_s = Signal(mwid+1, reset_less=True)
1133                 clz = Signal((len(i.z.e), True), reset_less=True)
1134                 # make sure that the amount to decrease by does NOT
1135                 # go below the minimum non-INF/NaN exponent
1136                 limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1137                              i.z.exp_sub_n126)
1138                 m.d.comb += [
1139                     # cat round and guard bits back into the mantissa
1140                     temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1141                     pe.i.eq(temp_m[::-1]),          # inverted
1142                     clz.eq(limclz),                 # count zeros from MSB down
1143                     temp_s.eq(temp_m << clz),       # shift mantissa UP
1144                     self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1145                     self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1146                     of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1147                     # overflow in bits 0..1: got shifted too (leave sticky)
1148                     of.guard.eq(temp_s[1]),       # guard
1149                     of.round_bit.eq(temp_s[0]),   # round
1150                 ]
1151             # increase exponent
1152             with m.Elif(increase):
1153                 temp_m = Signal(mwid+1, reset_less=True)
1154                 m.d.comb += [
1155                     temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1156                                   i.z.m)),
1157                     ediff_n126.eq(i.z.N126 - i.z.e),
1158                     # connect multi-shifter to inp/out mantissa (and ediff)
1159                     msr.inp.eq(temp_m),
1160                     msr.diff.eq(ediff_n126),
1161                     self.o.z.m.eq(msr.m[3:]),
1162                     of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1163                     # overflow in bits 0..1: got shifted too (leave sticky)
1164                     of.guard.eq(temp_s[2]),     # guard
1165                     of.round_bit.eq(temp_s[1]), # round
1166                     of.sticky.eq(temp_s[0]),    # sticky
1167                     self.o.z.e.eq(i.z.e + ediff_n126),
1168                 ]
1169
1170         m.d.comb += self.o.mid.eq(self.i.mid)
1171         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
1172         m.d.comb += self.o.oz.eq(self.i.oz)
1173
1174         return m
1175
1176
1177 class FPNorm1ModMulti:
1178
1179     def __init__(self, width, single_cycle=True):
1180         self.width = width
1181         self.in_select = Signal(reset_less=True)
1182         self.in_z = FPNumBase(width, False)
1183         self.in_of = Overflow()
1184         self.temp_z = FPNumBase(width, False)
1185         self.temp_of = Overflow()
1186         self.out_z = FPNumBase(width, False)
1187         self.out_of = Overflow()
1188
1189     def elaborate(self, platform):
1190         m = Module()
1191
1192         m.submodules.norm1_out_z = self.out_z
1193         m.submodules.norm1_out_overflow = self.out_of
1194         m.submodules.norm1_temp_z = self.temp_z
1195         m.submodules.norm1_temp_of = self.temp_of
1196         m.submodules.norm1_in_z = self.in_z
1197         m.submodules.norm1_in_overflow = self.in_of
1198
1199         in_z = FPNumBase(self.width, False)
1200         in_of = Overflow()
1201         m.submodules.norm1_insel_z = in_z
1202         m.submodules.norm1_insel_overflow = in_of
1203
1204         # select which of temp or in z/of to use
1205         with m.If(self.in_select):
1206             m.d.comb += in_z.eq(self.in_z)
1207             m.d.comb += in_of.eq(self.in_of)
1208         with m.Else():
1209             m.d.comb += in_z.eq(self.temp_z)
1210             m.d.comb += in_of.eq(self.temp_of)
1211         # initialise out from in (overridden below)
1212         m.d.comb += self.out_z.eq(in_z)
1213         m.d.comb += self.out_of.eq(in_of)
1214         # normalisation increase/decrease conditions
1215         decrease = Signal(reset_less=True)
1216         increase = Signal(reset_less=True)
1217         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1218         m.d.comb += increase.eq(in_z.exp_lt_n126)
1219         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1220         # decrease exponent
1221         with m.If(decrease):
1222             m.d.comb += [
1223                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1224                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1225                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1226                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1227                 self.out_of.round_bit.eq(0),        # reset round bit
1228                 self.out_of.m0.eq(in_of.guard),
1229             ]
1230         # increase exponent
1231         with m.Elif(increase):
1232             m.d.comb += [
1233                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1234                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1235                 self.out_of.guard.eq(in_z.m[0]),
1236                 self.out_of.m0.eq(in_z.m[1]),
1237                 self.out_of.round_bit.eq(in_of.guard),
1238                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1239             ]
1240
1241         return m
1242
1243
1244 class FPNorm1Single(FPState):
1245
1246     def __init__(self, width, id_wid, single_cycle=True):
1247         FPState.__init__(self, "normalise_1")
1248         self.mod = FPNorm1ModSingle(width)
1249         self.o = self.ospec()
1250         self.out_z = FPNumBase(width, False)
1251         self.out_roundz = Signal(reset_less=True)
1252
1253     def ispec(self):
1254         return self.mod.ispec()
1255
1256     def ospec(self):
1257         return self.mod.ospec()
1258
1259     def setup(self, m, i):
1260         """ links module to inputs and outputs
1261         """
1262         self.mod.setup(m, i)
1263
1264     def action(self, m):
1265         m.next = "round"
1266
1267
1268 class FPNorm1Multi(FPState):
1269
1270     def __init__(self, width, id_wid):
1271         FPState.__init__(self, "normalise_1")
1272         self.mod = FPNorm1ModMulti(width)
1273         self.stb = Signal(reset_less=True)
1274         self.ack = Signal(reset=0, reset_less=True)
1275         self.out_norm = Signal(reset_less=True)
1276         self.in_accept = Signal(reset_less=True)
1277         self.temp_z = FPNumBase(width)
1278         self.temp_of = Overflow()
1279         self.out_z = FPNumBase(width)
1280         self.out_roundz = Signal(reset_less=True)
1281
1282     def setup(self, m, in_z, in_of, norm_stb):
1283         """ links module to inputs and outputs
1284         """
1285         self.mod.setup(m, in_z, in_of, norm_stb,
1286                        self.in_accept, self.temp_z, self.temp_of,
1287                        self.out_z, self.out_norm)
1288
1289         m.d.comb += self.stb.eq(norm_stb)
1290         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1291
1292     def action(self, m):
1293         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1294         m.d.sync += self.temp_of.eq(self.mod.out_of)
1295         m.d.sync += self.temp_z.eq(self.out_z)
1296         with m.If(self.out_norm):
1297             with m.If(self.in_accept):
1298                 m.d.sync += [
1299                     self.ack.eq(1),
1300                 ]
1301             with m.Else():
1302                 m.d.sync += self.ack.eq(0)
1303         with m.Else():
1304             # normalisation not required (or done).
1305             m.next = "round"
1306             m.d.sync += self.ack.eq(1)
1307             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1308
1309
1310 class FPNormToPack(FPState):
1311
1312     def __init__(self, width, id_wid):
1313         FPState.__init__(self, "normalise_1")
1314         self.id_wid = id_wid
1315         self.width = width
1316
1317     def ispec(self):
1318         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1319
1320     def ospec(self):
1321         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1322
1323     def setup(self, m, i):
1324         """ links module to inputs and outputs
1325         """
1326
1327         # Normalisation, Rounding Corrections, Pack - in a chain
1328         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1329         rmod = FPRoundMod(self.width, self.id_wid)
1330         cmod = FPCorrectionsMod(self.width, self.id_wid)
1331         pmod = FPPackMod(self.width, self.id_wid)
1332         chain = StageChain([nmod, rmod, cmod, pmod])
1333         chain.setup(m, i)
1334         self.out_z = pmod.ospec()
1335
1336         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1337         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1338
1339     def process(self, i):
1340         return self.out_z
1341
1342     def action(self, m):
1343         m.next = "pack_put_z"
1344
1345
1346 class FPRoundData:
1347
1348     def __init__(self, width, id_wid):
1349         self.z = FPNumBase(width, False)
1350         self.out_do_z = Signal(reset_less=True)
1351         self.oz = Signal(width, reset_less=True)
1352         self.mid = Signal(id_wid, reset_less=True)
1353
1354     def eq(self, i):
1355         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
1356                 self.mid.eq(i.mid)]
1357
1358
1359 class FPRoundMod:
1360
1361     def __init__(self, width, id_wid):
1362         self.width = width
1363         self.id_wid = id_wid
1364         self.i = self.ispec()
1365         self.out_z = self.ospec()
1366
1367     def ispec(self):
1368         return FPNorm1Data(self.width, self.id_wid)
1369
1370     def ospec(self):
1371         return FPRoundData(self.width, self.id_wid)
1372
1373     def process(self, i):
1374         return self.out_z
1375
1376     def setup(self, m, i):
1377         m.submodules.roundz = self
1378         m.d.comb += self.i.eq(i)
1379
1380     def elaborate(self, platform):
1381         m = Module()
1382         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1383         with m.If(~self.i.out_do_z):
1384             with m.If(self.i.roundz):
1385                 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
1386                 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1387                     m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1388
1389         return m
1390
1391
1392 class FPRound(FPState):
1393
1394     def __init__(self, width, id_wid):
1395         FPState.__init__(self, "round")
1396         self.mod = FPRoundMod(width)
1397         self.out_z = self.ospec()
1398
1399     def ispec(self):
1400         return self.mod.ispec()
1401
1402     def ospec(self):
1403         return self.mod.ospec()
1404
1405     def setup(self, m, i):
1406         """ links module to inputs and outputs
1407         """
1408         self.mod.setup(m, i)
1409
1410         self.idsync(m)
1411         m.d.sync += self.out_z.eq(self.mod.out_z)
1412         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1413
1414     def action(self, m):
1415         m.next = "corrections"
1416
1417
1418 class FPCorrectionsMod:
1419
1420     def __init__(self, width, id_wid):
1421         self.width = width
1422         self.id_wid = id_wid
1423         self.i = self.ispec()
1424         self.out_z = self.ospec()
1425
1426     def ispec(self):
1427         return FPRoundData(self.width, self.id_wid)
1428
1429     def ospec(self):
1430         return FPRoundData(self.width, self.id_wid)
1431
1432     def process(self, i):
1433         return self.out_z
1434
1435     def setup(self, m, i):
1436         """ links module to inputs and outputs
1437         """
1438         m.submodules.corrections = self
1439         m.d.comb += self.i.eq(i)
1440
1441     def elaborate(self, platform):
1442         m = Module()
1443         m.submodules.corr_in_z = self.i.z
1444         m.submodules.corr_out_z = self.out_z.z
1445         m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
1446         with m.If(~self.i.out_do_z):
1447             with m.If(self.i.z.is_denormalised):
1448                 m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1449         return m
1450
1451
1452 class FPCorrections(FPState):
1453
1454     def __init__(self, width, id_wid):
1455         FPState.__init__(self, "corrections")
1456         self.mod = FPCorrectionsMod(width)
1457         self.out_z = self.ospec()
1458
1459     def ispec(self):
1460         return self.mod.ispec()
1461
1462     def ospec(self):
1463         return self.mod.ospec()
1464
1465     def setup(self, m, in_z):
1466         """ links module to inputs and outputs
1467         """
1468         self.mod.setup(m, in_z)
1469
1470         m.d.sync += self.out_z.eq(self.mod.out_z)
1471         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1472
1473     def action(self, m):
1474         m.next = "pack"
1475
1476
1477 class FPPackData:
1478
1479     def __init__(self, width, id_wid):
1480         self.z = FPNumOut(width, False)
1481         self.mid = Signal(id_wid, reset_less=True)
1482
1483     def eq(self, i):
1484         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1485
1486
1487 class FPPackMod:
1488
1489     def __init__(self, width, id_wid):
1490         self.width = width
1491         self.id_wid = id_wid
1492         self.i = self.ispec()
1493         self.o = self.ospec()
1494
1495     def ispec(self):
1496         return FPRoundData(self.width, self.id_wid)
1497
1498     def ospec(self):
1499         return FPPackData(self.width, self.id_wid)
1500
1501     def process(self, i):
1502         return self.o
1503
1504     def setup(self, m, in_z):
1505         """ links module to inputs and outputs
1506         """
1507         m.submodules.pack = self
1508         m.d.comb += self.i.eq(in_z)
1509
1510     def elaborate(self, platform):
1511         m = Module()
1512         m.submodules.pack_in_z = self.i.z
1513         m.d.comb += self.o.mid.eq(self.i.mid)
1514         with m.If(~self.i.out_do_z):
1515             with m.If(self.i.z.is_overflowed):
1516                 m.d.comb += self.o.z.inf(self.i.z.s)
1517             with m.Else():
1518                 m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1519         with m.Else():
1520             m.d.comb += self.o.z.v.eq(self.i.oz)
1521         return m
1522
1523
1524 class FPPack(FPState):
1525
1526     def __init__(self, width, id_wid):
1527         FPState.__init__(self, "pack")
1528         self.mod = FPPackMod(width)
1529         self.out_z = self.ospec()
1530
1531     def ispec(self):
1532         return self.mod.ispec()
1533
1534     def ospec(self):
1535         return self.mod.ospec()
1536
1537     def setup(self, m, in_z):
1538         """ links module to inputs and outputs
1539         """
1540         self.mod.setup(m, in_z)
1541
1542         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1543         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1544
1545     def action(self, m):
1546         m.next = "pack_put_z"
1547
1548
1549 class FPPutZ(FPState):
1550
1551     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1552         FPState.__init__(self, state)
1553         if to_state is None:
1554             to_state = "get_ops"
1555         self.to_state = to_state
1556         self.in_z = in_z
1557         self.out_z = out_z
1558         self.in_mid = in_mid
1559         self.out_mid = out_mid
1560
1561     def action(self, m):
1562         if self.in_mid is not None:
1563             m.d.sync += self.out_mid.eq(self.in_mid)
1564         m.d.sync += [
1565           self.out_z.z.v.eq(self.in_z.v)
1566         ]
1567         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1568             m.d.sync += self.out_z.z.stb.eq(0)
1569             m.next = self.to_state
1570         with m.Else():
1571             m.d.sync += self.out_z.z.stb.eq(1)
1572
1573
1574 class FPPutZIdx(FPState):
1575
1576     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1577         FPState.__init__(self, state)
1578         if to_state is None:
1579             to_state = "get_ops"
1580         self.to_state = to_state
1581         self.in_z = in_z
1582         self.out_zs = out_zs
1583         self.in_mid = in_mid
1584
1585     def action(self, m):
1586         outz_stb = Signal(reset_less=True)
1587         outz_ack = Signal(reset_less=True)
1588         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1589                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1590                     ]
1591         m.d.sync += [
1592           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1593         ]
1594         with m.If(outz_stb & outz_ack):
1595             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1596             m.next = self.to_state
1597         with m.Else():
1598             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1599
1600 class FPADDBaseData:
1601
1602     def __init__(self, width, id_wid):
1603         self.width = width
1604         self.id_wid = id_wid
1605         self.a  = Signal(width)
1606         self.b  = Signal(width)
1607         self.mid = Signal(id_wid, reset_less=True)
1608
1609     def eq(self, i):
1610         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1611
1612
1613 class FPOpData:
1614     def __init__(self, width, id_wid):
1615         self.z = FPOp(width)
1616         self.mid = Signal(id_wid, reset_less=True)
1617
1618     def eq(self, i):
1619         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1620
1621
1622 class FPADDBaseMod:
1623
1624     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1625         """ IEEE754 FP Add
1626
1627             * width: bit-width of IEEE754.  supported: 16, 32, 64
1628             * id_wid: an identifier that is sync-connected to the input
1629             * single_cycle: True indicates each stage to complete in 1 clock
1630             * compact: True indicates a reduced number of stages
1631         """
1632         self.width = width
1633         self.id_wid = id_wid
1634         self.single_cycle = single_cycle
1635         self.compact = compact
1636
1637         self.in_t = Trigger()
1638         self.i = self.ispec()
1639         self.o = self.ospec()
1640
1641         self.states = []
1642
1643     def ispec(self):
1644         return FPADDBaseData(self.width, self.id_wid)
1645
1646     def ospec(self):
1647         return FPOpData(self.width, self.id_wid)
1648
1649     def add_state(self, state):
1650         self.states.append(state)
1651         return state
1652
1653     def get_fragment(self, platform=None):
1654         """ creates the HDL code-fragment for FPAdd
1655         """
1656         m = Module()
1657         m.submodules.out_z = self.o.z
1658         m.submodules.in_t = self.in_t
1659         if self.compact:
1660             self.get_compact_fragment(m, platform)
1661         else:
1662             self.get_longer_fragment(m, platform)
1663
1664         with m.FSM() as fsm:
1665
1666             for state in self.states:
1667                 with m.State(state.state_from):
1668                     state.action(m)
1669
1670         return m
1671
1672     def get_longer_fragment(self, m, platform=None):
1673
1674         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1675                                       self.width))
1676         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1677         a = get.out_op1
1678         b = get.out_op2
1679
1680         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1681         sc.setup(m, a, b, self.in_mid)
1682
1683         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1684         dn.setup(m, a, b, sc.in_mid)
1685
1686         if self.single_cycle:
1687             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1688             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1689         else:
1690             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1691             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1692
1693         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1694         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1695
1696         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1697         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1698
1699         if self.single_cycle:
1700             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1701             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1702         else:
1703             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1704             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1705
1706         rn = self.add_state(FPRound(self.width, self.id_wid))
1707         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1708
1709         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1710         cor.setup(m, rn.out_z, rn.in_mid)
1711
1712         pa = self.add_state(FPPack(self.width, self.id_wid))
1713         pa.setup(m, cor.out_z, rn.in_mid)
1714
1715         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1716                                     pa.in_mid, self.out_mid))
1717
1718         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1719                                     pa.in_mid, self.out_mid))
1720
1721     def get_compact_fragment(self, m, platform=None):
1722
1723         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1724                                       self.width, self.id_wid))
1725         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1726
1727         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1728         sc.setup(m, get.o)
1729
1730         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1731         alm.setup(m, sc.o)
1732
1733         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1734         n1.setup(m, alm.a1o)
1735
1736         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1737                                     n1.out_z.mid, self.o.mid))
1738
1739         #pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1740         #                            sc.o.mid, self.o.mid))
1741
1742
1743 class FPADDBase(FPState):
1744
1745     def __init__(self, width, id_wid=None, single_cycle=False):
1746         """ IEEE754 FP Add
1747
1748             * width: bit-width of IEEE754.  supported: 16, 32, 64
1749             * id_wid: an identifier that is sync-connected to the input
1750             * single_cycle: True indicates each stage to complete in 1 clock
1751         """
1752         FPState.__init__(self, "fpadd")
1753         self.width = width
1754         self.single_cycle = single_cycle
1755         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1756         self.o = self.ospec()
1757
1758         self.in_t = Trigger()
1759         self.i = self.ispec()
1760
1761         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1762         self.in_accept = Signal(reset_less=True)
1763         self.add_stb = Signal(reset_less=True)
1764         self.add_ack = Signal(reset=0, reset_less=True)
1765
1766     def ispec(self):
1767         return self.mod.ispec()
1768
1769     def ospec(self):
1770         return self.mod.ospec()
1771
1772     def setup(self, m, i, add_stb, in_mid):
1773         m.d.comb += [self.i.eq(i),
1774                      self.mod.i.eq(self.i),
1775                      self.z_done.eq(self.mod.o.z.trigger),
1776                      #self.add_stb.eq(add_stb),
1777                      self.mod.in_t.stb.eq(self.in_t.stb),
1778                      self.in_t.ack.eq(self.mod.in_t.ack),
1779                      self.o.mid.eq(self.mod.o.mid),
1780                      self.o.z.v.eq(self.mod.o.z.v),
1781                      self.o.z.stb.eq(self.mod.o.z.stb),
1782                      self.mod.o.z.ack.eq(self.o.z.ack),
1783                     ]
1784
1785         m.d.sync += self.add_stb.eq(add_stb)
1786         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1787         m.d.sync += self.o.z.ack.eq(0) # likewise
1788         #m.d.sync += self.in_t.stb.eq(0)
1789
1790         m.submodules.fpadd = self.mod
1791
1792     def action(self, m):
1793
1794         # in_accept is set on incoming strobe HIGH and ack LOW.
1795         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1796
1797         #with m.If(self.in_t.ack):
1798         #    m.d.sync += self.in_t.stb.eq(0)
1799         with m.If(~self.z_done):
1800             # not done: test for accepting an incoming operand pair
1801             with m.If(self.in_accept):
1802                 m.d.sync += [
1803                     self.add_ack.eq(1), # acknowledge receipt...
1804                     self.in_t.stb.eq(1), # initiate add
1805                 ]
1806             with m.Else():
1807                 m.d.sync += [self.add_ack.eq(0),
1808                              self.in_t.stb.eq(0),
1809                              self.o.z.ack.eq(1),
1810                             ]
1811         with m.Else():
1812             # done: acknowledge, and write out id and value
1813             m.d.sync += [self.add_ack.eq(1),
1814                          self.in_t.stb.eq(0)
1815                         ]
1816             m.next = "put_z"
1817
1818             return
1819
1820             if self.in_mid is not None:
1821                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1822
1823             m.d.sync += [
1824               self.out_z.v.eq(self.mod.out_z.v)
1825             ]
1826             # move to output state on detecting z ack
1827             with m.If(self.out_z.trigger):
1828                 m.d.sync += self.out_z.stb.eq(0)
1829                 m.next = "put_z"
1830             with m.Else():
1831                 m.d.sync += self.out_z.stb.eq(1)
1832
1833 class FPADDStageIn:
1834     def __init__(self, width, id_wid):
1835         self.a = Signal(width)
1836         self.b = Signal(width)
1837         self.mid = Signal(id_wid, reset_less=True)
1838
1839     def eq(self, i):
1840         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1841
1842
1843 class FPADDStageOut:
1844     def __init__(self, width, id_wid):
1845         self.z = Signal(width)
1846         self.mid = Signal(id_wid, reset_less=True)
1847
1848     def eq(self, i):
1849         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1850
1851
1852 # matches the format of FPADDStageOut, allows eq function to do assignments
1853 class PlaceHolder: pass
1854
1855
1856 class FPAddBaseStage:
1857     def __init__(self, width, id_wid):
1858         self.width = width
1859         self.id_wid = id_wid
1860
1861     def ispec(self):
1862         return FPADDStageIn(self.width, self.id_wid)
1863
1864     def ospec(self):
1865         return FPADDStageOut(self.width, self.id_wid)
1866
1867     def process(self, i):
1868         o = PlaceHolder()
1869         o.z = i.a + i.b
1870         o.mid = i.mid
1871         return o
1872
1873
1874 class FPADDBasePipe:
1875     def __init__(self, width, id_wid):
1876         stage1 = FPAddBaseStage(width, id_wid)
1877         self.pipe = UnbufferedPipeline(stage1)
1878
1879     def elaborate(self, platform):
1880         return self.pipe.elaborate(platform)
1881
1882     def ports(self):
1883         return self.pipe.ports()
1884
1885 class ResArray:
1886     def __init__(self, width, id_wid):
1887         self.width = width
1888         self.id_wid = id_wid
1889         res = []
1890         for i in range(rs_sz):
1891             out_z = FPOp(width)
1892             out_z.name = "out_z_%d" % i
1893             res.append(out_z)
1894         self.res = Array(res)
1895         self.in_z = FPOp(width)
1896         self.in_mid = Signal(self.id_wid, reset_less=True)
1897
1898     def setup(self, m, in_z, in_mid):
1899         m.d.comb += [self.in_z.eq(in_z),
1900                      self.in_mid.eq(in_mid)]
1901
1902     def get_fragment(self, platform=None):
1903         """ creates the HDL code-fragment for FPAdd
1904         """
1905         m = Module()
1906         m.submodules.res_in_z = self.in_z
1907         m.submodules += self.res
1908
1909         return m
1910
1911     def ports(self):
1912         res = []
1913         for z in self.res:
1914             res += z.ports()
1915         return res
1916
1917
1918 class FPADD(FPID):
1919     """ FPADD: stages as follows:
1920
1921         FPGetOp (a)
1922            |
1923         FPGetOp (b)
1924            |
1925         FPAddBase---> FPAddBaseMod
1926            |            |
1927         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1928
1929         FPAddBase is tricky: it is both a stage and *has* stages.
1930         Connection to FPAddBaseMod therefore requires an in stb/ack
1931         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1932         needs to be the thing that raises the incoming stb.
1933     """
1934
1935     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1936         """ IEEE754 FP Add
1937
1938             * width: bit-width of IEEE754.  supported: 16, 32, 64
1939             * id_wid: an identifier that is sync-connected to the input
1940             * single_cycle: True indicates each stage to complete in 1 clock
1941         """
1942         self.width = width
1943         self.id_wid = id_wid
1944         self.single_cycle = single_cycle
1945
1946         #self.out_z = FPOp(width)
1947         self.ids = FPID(id_wid)
1948
1949         rs = []
1950         for i in range(rs_sz):
1951             in_a  = FPOp(width)
1952             in_b  = FPOp(width)
1953             in_a.name = "in_a_%d" % i
1954             in_b.name = "in_b_%d" % i
1955             rs.append((in_a, in_b))
1956         self.rs = Array(rs)
1957
1958         res = []
1959         for i in range(rs_sz):
1960             out_z = FPOp(width)
1961             out_z.name = "out_z_%d" % i
1962             res.append(out_z)
1963         self.res = Array(res)
1964
1965         self.states = []
1966
1967     def add_state(self, state):
1968         self.states.append(state)
1969         return state
1970
1971     def get_fragment(self, platform=None):
1972         """ creates the HDL code-fragment for FPAdd
1973         """
1974         m = Module()
1975         m.submodules += self.rs
1976
1977         in_a = self.rs[0][0]
1978         in_b = self.rs[0][1]
1979
1980         geta = self.add_state(FPGetOp("get_a", "get_b",
1981                                       in_a, self.width))
1982         geta.setup(m, in_a)
1983         a = geta.out_op
1984
1985         getb = self.add_state(FPGetOp("get_b", "fpadd",
1986                                       in_b, self.width))
1987         getb.setup(m, in_b)
1988         b = getb.out_op
1989
1990         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1991         ab = self.add_state(ab)
1992         abd = ab.ispec() # create an input spec object for FPADDBase
1993         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1994         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1995         o = ab.o
1996
1997         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1998                                     o.mid, "get_a"))
1999
2000         with m.FSM() as fsm:
2001
2002             for state in self.states:
2003                 with m.State(state.state_from):
2004                     state.action(m)
2005
2006         return m
2007
2008
2009 if __name__ == "__main__":
2010     if True:
2011         alu = FPADD(width=32, id_wid=5, single_cycle=True)
2012         main(alu, ports=alu.rs[0][0].ports() + \
2013                         alu.rs[0][1].ports() + \
2014                         alu.res[0].ports() + \
2015                         [alu.ids.in_mid, alu.ids.out_mid])
2016     else:
2017         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
2018         main(alu, ports=[alu.in_a, alu.in_b] + \
2019                         alu.in_t.ports() + \
2020                         alu.out_z.ports() + \
2021                         [alu.in_mid, alu.out_mid])
2022
2023
2024     # works... but don't use, just do "python fname.py convert -t v"
2025     #print (verilog.convert(alu, ports=[
2026     #                        ports=alu.in_a.ports() + \
2027     #                              alu.in_b.ports() + \
2028     #                              alu.out_z.ports())