src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10
  11
  12 class FPState(FPBase):
  13     def __init__(self, state_from):
  14         self.state_from = state_from
  15
  16     def set_inputs(self, inputs):
  17         self.inputs = inputs
  18         for k,v in inputs.items():
  19             setattr(self, k, v)
  20
  21     def set_outputs(self, outputs):
  22         self.outputs = outputs
  23         for k,v in outputs.items():
  24             setattr(self, k, v)
  25
  26
  27 class FPGetOpMod:
  28     def __init__(self, width):
  29         self.in_op = FPOp(width)
  30         self.out_op = FPNumIn(self.in_op, width)
  31         self.out_decode = Signal(reset_less=True)
  32
  33     def setup(self, m, in_op, out_op, out_decode):
  34         """ links module to inputs and outputs
  35         """
  36         m.d.comb += self.in_op.copy(in_op)
  37         m.d.comb += out_op.v.eq(self.out_op.v)
  38         m.d.comb += out_decode.eq(self.out_decode)
  39
  40     def elaborate(self, platform):
  41         m = Module()
  42         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  43         #m.submodules.get_op_in = self.in_op
  44         m.submodules.get_op_out = self.out_op
  45         with m.If(self.out_decode):
  46             m.d.comb += [
  47                 self.out_op.decode(self.in_op.v),
  48             ]
  49         return m
  50
  51
  52 class FPGetOp(FPState):
  53     """ gets operand
  54     """
  55
  56     def __init__(self, in_state, out_state, in_op, width):
  57         FPState.__init__(self, in_state)
  58         self.out_state = out_state
  59         self.mod = FPGetOpMod(width)
  60         self.in_op = in_op
  61         self.out_op = FPNumIn(in_op, width)
  62         self.out_decode = Signal(reset_less=True)
  63
  64     def action(self, m):
  65         with m.If(self.out_decode):
  66             m.next = self.out_state
  67             m.d.sync += [
  68                 self.in_op.ack.eq(0),
  69                 self.out_op.copy(self.mod.out_op)
  70             ]
  71         with m.Else():
  72             m.d.sync += self.in_op.ack.eq(1)
  73
  74
  75 class FPGetOpB(FPState):
  76     """ gets operand b
  77     """
  78
  79     def __init__(self, in_b, width):
  80         FPState.__init__(self, "get_b")
  81         self.in_b = in_b
  82         self.b = FPNumIn(self.in_b, width)
  83
  84     def action(self, m):
  85         self.get_op(m, self.in_b, self.b, "special_cases")
  86
  87
  88 class FPAddSpecialCasesMod:
  89     """ special cases: NaNs, infs, zeros, denormalised
  90         NOTE: some of these are unique to add.  see "Special Operations"
  91         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  92     """
  93
  94     def __init__(self, width):
  95         self.in_a = FPNumBase(width)
  96         self.in_b = FPNumBase(width)
  97         self.out_z = FPNumOut(width, False)
  98         self.out_do_z = Signal(reset_less=True)
  99
 100     def setup(self, m, in_a, in_b, out_z, out_do_z):
 101         """ links module to inputs and outputs
 102         """
 103         m.d.comb += self.in_a.copy(in_a)
 104         m.d.comb += self.in_b.copy(in_b)
 105         #m.d.comb += out_z.v.eq(self.out_z.v)
 106         m.d.comb += out_do_z.eq(self.out_do_z)
 107
 108     def elaborate(self, platform):
 109         m = Module()
 110
 111         m.submodules.sc_in_a = self.in_a
 112         m.submodules.sc_in_b = self.in_b
 113         m.submodules.sc_out_z = self.out_z
 114
 115         s_nomatch = Signal()
 116         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
 117
 118         m_match = Signal()
 119         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 120
 121         # if a is NaN or b is NaN return NaN
 122         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 123             m.d.comb += self.out_do_z.eq(1)
 124             m.d.comb += self.out_z.nan(0)
 125
 126         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 127         # under review
 128
 129         ## if a is zero and b is NaN return -b
 130         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 131         #    m.d.comb += self.out_do_z.eq(1)
 132         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 133
 134         ## if b is zero and a is NaN return -a
 135         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 136         #    m.d.comb += self.out_do_z.eq(1)
 137         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 138
 139         ## if a is -zero and b is NaN return -b
 140         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 141         #    m.d.comb += self.out_do_z.eq(1)
 142         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 143
 144         ## if b is -zero and a is NaN return -a
 145         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 146         #    m.d.comb += self.out_do_z.eq(1)
 147         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 148
 149         # if a is inf return inf (or NaN)
 150         with m.Elif(self.in_a.is_inf):
 151             m.d.comb += self.out_do_z.eq(1)
 152             m.d.comb += self.out_z.inf(self.in_a.s)
 153             # if a is inf and signs don't match return NaN
 154             with m.If(self.in_b.exp_128 & s_nomatch):
 155                 m.d.comb += self.out_z.nan(0)
 156
 157         # if b is inf return inf
 158         with m.Elif(self.in_b.is_inf):
 159             m.d.comb += self.out_do_z.eq(1)
 160             m.d.comb += self.out_z.inf(self.in_b.s)
 161
 162         # if a is zero and b zero return signed-a/b
 163         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 164             m.d.comb += self.out_do_z.eq(1)
 165             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 166                                           self.in_b.e,
 167                                           self.in_b.m[3:-1])
 168
 169         # if a is zero return b
 170         with m.Elif(self.in_a.is_zero):
 171             m.d.comb += self.out_do_z.eq(1)
 172             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 173                                       self.in_b.m[3:-1])
 174
 175         # if b is zero return a
 176         with m.Elif(self.in_b.is_zero):
 177             m.d.comb += self.out_do_z.eq(1)
 178             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 179                                       self.in_a.m[3:-1])
 180
 181         # if a equal to -b return zero (+ve zero)
 182         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 183             m.d.comb += self.out_do_z.eq(1)
 184             m.d.comb += self.out_z.zero(0)
 185
 186         # Denormalised Number checks
 187         with m.Else():
 188             m.d.comb += self.out_do_z.eq(0)
 189
 190         return m
 191
 192
 193 class FPAddSpecialCases(FPState):
 194     """ special cases: NaNs, infs, zeros, denormalised
 195         NOTE: some of these are unique to add.  see "Special Operations"
 196         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 197     """
 198
 199     def __init__(self, width):
 200         FPState.__init__(self, "special_cases")
 201         self.mod = FPAddSpecialCasesMod(width)
 202         self.out_z = FPNumOut(width, False)
 203         self.out_do_z = Signal(reset_less=True)
 204
 205     def action(self, m):
 206         with m.If(self.out_do_z):
 207             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 208             m.next = "put_z"
 209         with m.Else():
 210             m.next = "denormalise"
 211
 212
 213 class FPAddDeNormMod(FPState):
 214
 215     def __init__(self, width):
 216         self.in_a = FPNumBase(width)
 217         self.in_b = FPNumBase(width)
 218         self.out_a = FPNumBase(width)
 219         self.out_b = FPNumBase(width)
 220
 221     def setup(self, m, in_a, in_b, out_a, out_b):
 222         """ links module to inputs and outputs
 223         """
 224         m.d.comb += self.in_a.copy(in_a)
 225         m.d.comb += self.in_b.copy(in_b)
 226         m.d.comb += out_a.copy(self.out_a)
 227         m.d.comb += out_b.copy(self.out_b)
 228
 229     def elaborate(self, platform):
 230         m = Module()
 231         m.submodules.denorm_in_a = self.in_a
 232         m.submodules.denorm_in_b = self.in_b
 233         m.submodules.denorm_out_a = self.out_a
 234         m.submodules.denorm_out_b = self.out_b
 235         # hmmm, don't like repeating identical code
 236         m.d.comb += self.out_a.copy(self.in_a)
 237         with m.If(self.in_a.exp_n127):
 238             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 239         with m.Else():
 240             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 241
 242         m.d.comb += self.out_b.copy(self.in_b)
 243         with m.If(self.in_b.exp_n127):
 244             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 245         with m.Else():
 246             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 247
 248         return m
 249
 250
 251 class FPAddDeNorm(FPState):
 252
 253     def __init__(self, width):
 254         FPState.__init__(self, "denormalise")
 255         self.mod = FPAddDeNormMod(width)
 256         self.out_a = FPNumBase(width)
 257         self.out_b = FPNumBase(width)
 258
 259     def action(self, m):
 260         # Denormalised Number checks
 261         m.next = "align"
 262         m.d.sync += self.a.copy(self.out_a)
 263         m.d.sync += self.b.copy(self.out_b)
 264
 265
 266 class FPAddAlignMultiMod(FPState):
 267
 268     def __init__(self, width):
 269         self.in_a = FPNumBase(width)
 270         self.in_b = FPNumBase(width)
 271         self.out_a = FPNumIn(None, width)
 272         self.out_b = FPNumIn(None, width)
 273         self.exp_eq = Signal(reset_less=True)
 274
 275     def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
 276         """ links module to inputs and outputs
 277         """
 278         m.d.comb += self.in_a.copy(in_a)
 279         m.d.comb += self.in_b.copy(in_b)
 280         m.d.comb += out_a.copy(self.out_a)
 281         m.d.comb += out_b.copy(self.out_b)
 282         m.d.comb += exp_eq.eq(self.exp_eq)
 283
 284     def elaborate(self, platform):
 285         # This one however (single-cycle) will do the shift
 286         # in one go.
 287
 288         m = Module()
 289
 290         #m.submodules.align_in_a = self.in_a
 291         #m.submodules.align_in_b = self.in_b
 292         m.submodules.align_out_a = self.out_a
 293         m.submodules.align_out_b = self.out_b
 294
 295         # NOTE: this does *not* do single-cycle multi-shifting,
 296         #       it *STAYS* in the align state until exponents match
 297
 298         # exponent of a greater than b: shift b down
 299         m.d.comb += self.exp_eq.eq(0)
 300         m.d.comb += self.out_a.copy(self.in_a)
 301         m.d.comb += self.out_b.copy(self.in_b)
 302         agtb = Signal(reset_less=True)
 303         altb = Signal(reset_less=True)
 304         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 305         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 306         with m.If(agtb):
 307             m.d.comb += self.out_b.shift_down(self.in_b)
 308         # exponent of b greater than a: shift a down
 309         with m.Elif(altb):
 310             m.d.comb += self.out_a.shift_down(self.in_a)
 311         # exponents equal: move to next stage.
 312         with m.Else():
 313             m.d.comb += self.exp_eq.eq(1)
 314         return m
 315
 316
 317 class FPAddAlignMulti(FPState):
 318
 319     def __init__(self, width):
 320         FPState.__init__(self, "align")
 321         self.mod = FPAddAlignMultiMod(width)
 322         self.out_a = FPNumIn(None, width)
 323         self.out_b = FPNumIn(None, width)
 324         self.exp_eq = Signal(reset_less=True)
 325
 326     def action(self, m):
 327         m.d.sync += self.a.copy(self.out_a)
 328         m.d.sync += self.b.copy(self.out_b)
 329         with m.If(self.exp_eq):
 330             m.next = "add_0"
 331
 332
 333 class FPAddAlignSingleMod:
 334
 335     def __init__(self, width):
 336         self.in_a = FPNumBase(width)
 337         self.in_b = FPNumBase(width)
 338         self.out_a = FPNumIn(None, width)
 339         self.out_b = FPNumIn(None, width)
 340         #self.out_a = FPNumBase(width)
 341         #self.out_b = FPNumBase(width)
 342
 343     def setup(self, m, in_a, in_b, out_a, out_b):
 344         """ links module to inputs and outputs
 345         """
 346         m.d.comb += self.in_a.copy(in_a)
 347         m.d.comb += self.in_b.copy(in_b)
 348         m.d.comb += out_a.copy(self.out_a)
 349         m.d.comb += out_b.copy(self.out_b)
 350
 351     def elaborate(self, platform):
 352         # This one however (single-cycle) will do the shift
 353         # in one go.
 354
 355         m = Module()
 356
 357         m.submodules.align_in_a = self.in_a
 358         m.submodules.align_in_b = self.in_b
 359         m.submodules.align_out_a = self.out_a
 360         m.submodules.align_out_b = self.out_b
 361
 362         # XXX TODO: the shifter used here is quite expensive
 363         # having only one would be better
 364
 365         ediff = Signal((len(self.in_a.e), True), reset_less=True)
 366         ediffr = Signal((len(self.in_a.e), True), reset_less=True)
 367
 368         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 369         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 370         m.d.comb += self.out_a.copy(self.in_a)
 371         m.d.comb += self.out_b.copy(self.in_b)
 372         with m.If(ediff > 0):
 373             m.d.comb += self.out_b.shift_down_multi(ediff, self.in_b)
 374         # exponent of b greater than a: shift a down
 375         with m.Elif(ediff < 0):
 376             m.d.comb += self.out_a.shift_down_multi(ediffr, self.in_a)
 377         return m
 378
 379
 380 class FPAddAlignSingle(FPState):
 381
 382     def __init__(self, width):
 383         FPState.__init__(self, "align")
 384         self.mod = FPAddAlignSingleMod(width)
 385         self.out_a = FPNumIn(None, width)
 386         self.out_b = FPNumIn(None, width)
 387
 388     def action(self, m):
 389         m.d.sync += self.a.copy(self.out_a)
 390         m.d.sync += self.b.copy(self.out_b)
 391         m.next = "add_0"
 392
 393
 394 class FPAddStage0Mod:
 395
 396     def __init__(self, width):
 397         self.in_a = FPNumBase(width)
 398         self.in_b = FPNumBase(width)
 399         self.in_z = FPNumBase(width, False)
 400         self.out_z = FPNumBase(width, False)
 401         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 402
 403     def elaborate(self, platform):
 404         m = Module()
 405         m.submodules.add0_in_a = self.in_a
 406         m.submodules.add0_in_b = self.in_b
 407         m.submodules.add0_out_z = self.out_z
 408
 409         m.d.comb += self.out_z.e.eq(self.in_a.e)
 410
 411         # store intermediate tests (and zero-extended mantissas)
 412         seq = Signal(reset_less=True)
 413         mge = Signal(reset_less=True)
 414         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 415         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 416         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 417                      mge.eq(self.in_a.m >= self.in_b.m),
 418                      am0.eq(Cat(self.in_a.m, 0)),
 419                      bm0.eq(Cat(self.in_b.m, 0))
 420                     ]
 421         # same-sign (both negative or both positive) add mantissas
 422         with m.If(seq):
 423             m.d.comb += [
 424                 self.out_tot.eq(am0 + bm0),
 425                 self.out_z.s.eq(self.in_a.s)
 426             ]
 427         # a mantissa greater than b, use a
 428         with m.Elif(mge):
 429             m.d.comb += [
 430                 self.out_tot.eq(am0 - bm0),
 431                 self.out_z.s.eq(self.in_a.s)
 432             ]
 433         # b mantissa greater than a, use b
 434         with m.Else():
 435             m.d.comb += [
 436                 self.out_tot.eq(bm0 - am0),
 437                 self.out_z.s.eq(self.in_b.s)
 438         ]
 439         return m
 440
 441
 442 class FPAddStage0(FPState):
 443     """ First stage of add.  covers same-sign (add) and subtract
 444         special-casing when mantissas are greater or equal, to
 445         give greatest accuracy.
 446     """
 447
 448     def __init__(self, width):
 449         FPState.__init__(self, "add_0")
 450         self.mod = FPAddStage0Mod(width)
 451         self.out_z = FPNumBase(width, False)
 452         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 453
 454     def setup(self, m, in_a, in_b):
 455         """ links module to inputs and outputs
 456         """
 457         m.submodules.add0 = self.mod
 458
 459         m.d.comb += self.mod.in_a.copy(in_a)
 460         m.d.comb += self.mod.in_b.copy(in_b)
 461
 462     def action(self, m):
 463         m.next = "add_1"
 464         # NOTE: these could be done as combinatorial (merge add0+add1)
 465         m.d.sync += self.out_z.copy(self.mod.out_z)
 466         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 467
 468
 469 class FPAddStage1Mod(FPState):
 470     """ Second stage of add: preparation for normalisation.
 471         detects when tot sum is too big (tot[27] is kinda a carry bit)
 472     """
 473
 474     def __init__(self, width):
 475         self.out_norm = Signal(reset_less=True)
 476         self.in_z = FPNumBase(width, False)
 477         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 478         self.out_z = FPNumBase(width, False)
 479         self.out_of = Overflow()
 480
 481     def elaborate(self, platform):
 482         m = Module()
 483         #m.submodules.norm1_in_overflow = self.in_of
 484         #m.submodules.norm1_out_overflow = self.out_of
 485         #m.submodules.norm1_in_z = self.in_z
 486         #m.submodules.norm1_out_z = self.out_z
 487         m.d.comb += self.out_z.copy(self.in_z)
 488         # tot[27] gets set when the sum overflows. shift result down
 489         with m.If(self.in_tot[-1]):
 490             m.d.comb += [
 491                 self.out_z.m.eq(self.in_tot[4:]),
 492                 self.out_of.m0.eq(self.in_tot[4]),
 493                 self.out_of.guard.eq(self.in_tot[3]),
 494                 self.out_of.round_bit.eq(self.in_tot[2]),
 495                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 496                 self.out_z.e.eq(self.in_z.e + 1)
 497         ]
 498         # tot[27] zero case
 499         with m.Else():
 500             m.d.comb += [
 501                 self.out_z.m.eq(self.in_tot[3:]),
 502                 self.out_of.m0.eq(self.in_tot[3]),
 503                 self.out_of.guard.eq(self.in_tot[2]),
 504                 self.out_of.round_bit.eq(self.in_tot[1]),
 505                 self.out_of.sticky.eq(self.in_tot[0])
 506         ]
 507         return m
 508
 509
 510 class FPAddStage1(FPState):
 511
 512     def __init__(self, width):
 513         FPState.__init__(self, "add_1")
 514         self.mod = FPAddStage1Mod(width)
 515         self.out_z = FPNumBase(width, False)
 516         self.out_of = Overflow()
 517         self.norm_stb = Signal()
 518
 519     def setup(self, m, in_tot, in_z):
 520         """ links module to inputs and outputs
 521         """
 522         m.submodules.add1 = self.mod
 523
 524         m.d.comb += self.mod.in_z.copy(in_z)
 525         m.d.comb += self.mod.in_tot.eq(in_tot)
 526
 527         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 528
 529     def action(self, m):
 530         m.submodules.add1_out_overflow = self.out_of
 531         m.d.sync += self.out_of.copy(self.mod.out_of)
 532         m.d.sync += self.out_z.copy(self.mod.out_z)
 533         m.d.sync += self.norm_stb.eq(1)
 534         m.next = "normalise_1"
 535
 536
 537 class FPNorm1Mod:
 538
 539     def __init__(self, width, single_cycle=True):
 540         self.single_cycle = single_cycle
 541         self.width = width
 542         self.in_select = Signal(reset_less=True)
 543         self.out_norm = Signal(reset_less=True)
 544         self.in_z = FPNumBase(width, False)
 545         self.in_of = Overflow()
 546         self.temp_z = FPNumBase(width, False)
 547         self.temp_of = Overflow()
 548         self.out_z = FPNumBase(width, False)
 549         self.out_of = Overflow()
 550
 551     def elaborate(self, platform):
 552         m = Module()
 553         mwid = self.out_z.m_width+2
 554         pe = PriorityEncoder(mwid)
 555         m.submodules.norm_pe = pe
 556         m.submodules.norm1_out_z = self.out_z
 557         m.submodules.norm1_out_overflow = self.out_of
 558         m.submodules.norm1_temp_z = self.temp_z
 559         m.submodules.norm1_temp_of = self.temp_of
 560         m.submodules.norm1_in_z = self.in_z
 561         m.submodules.norm1_in_overflow = self.in_of
 562         in_z = FPNumBase(self.width, False)
 563         in_of = Overflow()
 564         m.submodules.norm1_insel_z = in_z
 565         m.submodules.norm1_insel_overflow = in_of
 566         # select which of temp or in z/of to use
 567         with m.If(self.in_select):
 568             m.d.comb += in_z.copy(self.in_z)
 569             m.d.comb += in_of.copy(self.in_of)
 570         with m.Else():
 571             m.d.comb += in_z.copy(self.temp_z)
 572             m.d.comb += in_of.copy(self.temp_of)
 573         # initialise out from in (overridden below)
 574         m.d.comb += self.out_z.copy(in_z)
 575         m.d.comb += self.out_of.copy(in_of)
 576         # normalisation increase/decrease conditions
 577         decrease = Signal(reset_less=True)
 578         increase = Signal(reset_less=True)
 579         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 580         m.d.comb += increase.eq(in_z.exp_lt_n126)
 581         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
 582         # decrease exponent
 583         with m.If(decrease):
 584             if not self.single_cycle:
 585                 m.d.comb += [
 586                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 587                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 588                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 589                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 590                 self.out_of.round_bit.eq(0),        # reset round bit
 591                 self.out_of.m0.eq(in_of.guard),
 592                 ]
 593             else:
 594                 # *sigh* not entirely obvious: count leading zeros (clz)
 595                 # with a PriorityEncoder: to find from the MSB
 596                 # we reverse the order of the bits.
 597                 temp_m = Signal(mwid, reset_less=True)
 598                 temp_s = Signal(mwid+1, reset_less=True)
 599                 clz = Signal((len(in_z.e), True), reset_less=True)
 600                 m.d.comb += [
 601                     # cat round and guard bits back into the mantissa
 602                     temp_m.eq(Cat(in_of.round_bit,
 603                                   in_of.guard,
 604                                   in_z.m)),
 605                     pe.i.eq(temp_m[::-1]),          # inverted
 606                     clz.eq(pe.o),                   # count zeros from MSB down
 607                     temp_s.eq(temp_m << clz),       # shift mantissa UP
 608                     self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 609                     self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 610                     self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 611                     # overflow in bits 0..1: got shifted too (leave sticky)
 612                     self.out_of.guard.eq(temp_s[1]),     # guard
 613                     self.out_of.round_bit.eq(temp_s[0]), # round
 614                 ]
 615         # increase exponent
 616         with m.If(increase):
 617             m.d.comb += [
 618                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 619                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 620                 self.out_of.guard.eq(in_z.m[0]),
 621                 self.out_of.m0.eq(in_z.m[1]),
 622                 self.out_of.round_bit.eq(in_of.guard),
 623                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 624             ]
 625
 626         return m
 627
 628
 629 class FPNorm1(FPState):
 630
 631     def __init__(self, width):
 632         FPState.__init__(self, "normalise_1")
 633         self.mod = FPNorm1Mod(width)
 634         self.stb = Signal(reset_less=True)
 635         self.ack = Signal(reset=0, reset_less=True)
 636         self.out_norm = Signal(reset_less=True)
 637         self.in_accept = Signal(reset_less=True)
 638         self.temp_z = FPNumBase(width)
 639         self.temp_of = Overflow()
 640         self.out_z = FPNumBase(width)
 641         self.out_roundz = Signal(reset_less=True)
 642
 643     def setup(self, m, in_z, in_of, norm_stb):
 644         """ links module to inputs and outputs
 645         """
 646         m.submodules.normalise_1 = self.mod
 647
 648         m.d.comb += self.mod.in_z.copy(in_z)
 649         m.d.comb += self.mod.in_of.copy(in_of)
 650
 651         m.d.comb += self.mod.in_select.eq(self.in_accept)
 652         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 653         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 654
 655         m.d.comb += self.out_z.copy(self.mod.out_z)
 656         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 657
 658         m.d.comb += self.stb.eq(norm_stb)
 659         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 660
 661     def action(self, m):
 662
 663         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 664         m.d.sync += self.temp_of.copy(self.mod.out_of)
 665         m.d.sync += self.temp_z.copy(self.out_z)
 666         with m.If(self.out_norm):
 667             with m.If(self.in_accept):
 668                 m.d.sync += [
 669                     self.ack.eq(1),
 670                 ]
 671             with m.Else():
 672                 m.d.sync += self.ack.eq(0)
 673         with m.Else():
 674             # normalisation not required (or done).
 675             m.next = "round"
 676             m.d.sync += self.ack.eq(1)
 677             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 678
 679
 680 class FPRoundMod:
 681
 682     def __init__(self, width):
 683         self.in_roundz = Signal(reset_less=True)
 684         self.in_z = FPNumBase(width, False)
 685         self.out_z = FPNumBase(width, False)
 686
 687     def elaborate(self, platform):
 688         m = Module()
 689         m.d.comb += self.out_z.copy(self.in_z)
 690         with m.If(self.in_roundz):
 691             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 692             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 693                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 694         return m
 695
 696
 697 class FPRound(FPState):
 698
 699     def __init__(self, width):
 700         FPState.__init__(self, "round")
 701         self.mod = FPRoundMod(width)
 702         self.out_z = FPNumBase(width)
 703
 704     def setup(self, m, in_z, roundz):
 705         """ links module to inputs and outputs
 706         """
 707         m.submodules.roundz = self.mod
 708
 709         m.d.comb += self.mod.in_z.copy(in_z)
 710         m.d.comb += self.mod.in_roundz.eq(roundz)
 711
 712     def action(self, m):
 713         m.d.sync += self.out_z.copy(self.mod.out_z)
 714         m.next = "corrections"
 715
 716
 717 class FPCorrectionsMod:
 718
 719     def __init__(self, width):
 720         self.in_z = FPNumOut(width, False)
 721         self.out_z = FPNumOut(width, False)
 722
 723     def elaborate(self, platform):
 724         m = Module()
 725         m.submodules.corr_in_z = self.in_z
 726         m.submodules.corr_out_z = self.out_z
 727         m.d.comb += self.out_z.copy(self.in_z)
 728         with m.If(self.in_z.is_denormalised):
 729             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 730
 731         #        with m.If(self.in_z.is_overflowed):
 732         #            m.d.comb += self.out_z.inf(self.in_z.s)
 733         #        with m.Else():
 734         #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 735         return m
 736
 737
 738 class FPCorrections(FPState):
 739
 740     def __init__(self, width):
 741         FPState.__init__(self, "corrections")
 742         self.mod = FPCorrectionsMod(width)
 743         self.out_z = FPNumBase(width)
 744
 745     def setup(self, m, in_z):
 746         """ links module to inputs and outputs
 747         """
 748         m.submodules.corrections = self.mod
 749         m.d.comb += self.mod.in_z.copy(in_z)
 750
 751     def action(self, m):
 752         m.d.sync += self.out_z.copy(self.mod.out_z)
 753         m.next = "pack"
 754
 755
 756 class FPPackMod:
 757
 758     def __init__(self, width):
 759         self.in_z = FPNumOut(width, False)
 760         self.out_z = FPNumOut(width, False)
 761
 762     def elaborate(self, platform):
 763         m = Module()
 764         m.submodules.pack_in_z = self.in_z
 765         with m.If(self.in_z.is_overflowed):
 766             m.d.comb += self.out_z.inf(self.in_z.s)
 767         with m.Else():
 768             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 769         return m
 770
 771
 772 class FPPack(FPState):
 773
 774     def __init__(self, width):
 775         FPState.__init__(self, "pack")
 776         self.mod = FPPackMod(width)
 777         self.out_z = FPNumOut(width, False)
 778
 779     def setup(self, m, in_z):
 780         """ links module to inputs and outputs
 781         """
 782         m.submodules.pack = self.mod
 783         m.d.comb += self.mod.in_z.copy(in_z)
 784
 785     def action(self, m):
 786         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 787         m.next = "pack_put_z"
 788
 789
 790 class FPPutZ(FPState):
 791
 792     def __init__(self, state, in_z, out_z):
 793         FPState.__init__(self, state)
 794         self.in_z = in_z
 795         self.out_z = out_z
 796
 797     def action(self, m):
 798         m.d.sync += [
 799           self.out_z.v.eq(self.in_z.v)
 800         ]
 801         with m.If(self.out_z.stb & self.out_z.ack):
 802             m.d.sync += self.out_z.stb.eq(0)
 803             m.next = "get_a"
 804         with m.Else():
 805             m.d.sync += self.out_z.stb.eq(1)
 806
 807
 808 class FPADD:
 809
 810     def __init__(self, width, single_cycle=False):
 811         self.width = width
 812         self.single_cycle = single_cycle
 813
 814         self.in_a  = FPOp(width)
 815         self.in_b  = FPOp(width)
 816         self.out_z = FPOp(width)
 817
 818         self.states = []
 819
 820     def add_state(self, state):
 821         self.states.append(state)
 822         return state
 823
 824     def get_fragment(self, platform=None):
 825         """ creates the HDL code-fragment for FPAdd
 826         """
 827         m = Module()
 828         m.submodules.in_a = self.in_a
 829         m.submodules.in_b = self.in_b
 830         m.submodules.out_z = self.out_z
 831
 832         geta = self.add_state(FPGetOp("get_a", "get_b",
 833                                       self.in_a, self.width))
 834         a = geta.out_op
 835         geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
 836         m.submodules.get_a = geta.mod
 837
 838         getb = self.add_state(FPGetOp("get_b", "special_cases",
 839                                       self.in_b, self.width))
 840         b = getb.out_op
 841         getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
 842         m.submodules.get_b = getb.mod
 843
 844         sc = self.add_state(FPAddSpecialCases(self.width))
 845         sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
 846         m.submodules.specialcases = sc.mod
 847
 848         dn = self.add_state(FPAddDeNorm(self.width))
 849         dn.set_inputs({"a": a, "b": b})
 850         #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 851         dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
 852         m.submodules.denormalise = dn.mod
 853
 854         if self.single_cycle:
 855             alm = self.add_state(FPAddAlignSingle(self.width))
 856             alm.set_inputs({"a": a, "b": b})
 857             alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 858             alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
 859         else:
 860             alm = self.add_state(FPAddAlignMulti(self.width))
 861             alm.set_inputs({"a": a, "b": b})
 862             #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 863             alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
 864         m.submodules.align = alm.mod
 865
 866         add0 = self.add_state(FPAddStage0(self.width))
 867         add0.setup(m, alm.out_a, alm.out_b)
 868
 869         add1 = self.add_state(FPAddStage1(self.width))
 870         add1.setup(m, add0.out_tot, add0.out_z)
 871
 872         n1 = self.add_state(FPNorm1(self.width))
 873         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 874
 875         rn = self.add_state(FPRound(self.width))
 876         rn.setup(m, n1.out_z, n1.out_roundz)
 877
 878         cor = self.add_state(FPCorrections(self.width))
 879         cor.setup(m, rn.out_z)
 880
 881         pa = self.add_state(FPPack(self.width))
 882         pa.setup(m, cor.out_z)
 883
 884         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
 885
 886         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
 887
 888         with m.FSM() as fsm:
 889
 890             for state in self.states:
 891                 with m.State(state.state_from):
 892                     state.action(m)
 893
 894         return m
 895
 896
 897 if __name__ == "__main__":
 898     alu = FPADD(width=32, single_cycle=True)
 899     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 900
 901
 902     # works... but don't use, just do "python fname.py convert -t v"
 903     #print (verilog.convert(alu, ports=[
 904     #                        ports=alu.in_a.ports() + \
 905     #                              alu.in_b.ports() + \
 906     #                              alu.out_z.ports())