src/add/nmigen_div_experiment.py

   1 # IEEE Floating Point Divider (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Const, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
   9
  10 class Div:
  11     def __init__(self, width):
  12         self.width = width
  13         self.quot = Signal(width)  # quotient
  14         self.dor = Signal(width)   # divisor
  15         self.dend = Signal(width)  # dividend
  16         self.rem = Signal(width)   # remainder
  17         self.count = Signal(7)     # loop count
  18
  19         self.czero = Const(0, width)
  20
  21     def reset(self, m):
  22         m.d.sync += [
  23             self.quot.eq(self.czero),
  24             self.rem.eq(self.czero),
  25             self.count.eq(Const(0, 7))
  26         ]
  27
  28
  29 class FPDIV(FPBase):
  30
  31     def __init__(self, width):
  32         FPBase.__init__(self)
  33         self.width = width
  34
  35         self.in_a  = FPOp(width)
  36         self.in_b  = FPOp(width)
  37         self.out_z = FPOp(width)
  38
  39     def get_fragment(self, platform=None):
  40         """ creates the HDL code-fragment for FPDiv
  41         """
  42         m = Module()
  43
  44         # Latches
  45         a = FPNumIn(None, self.width, False)
  46         b = FPNumIn(None, self.width, False)
  47         z = FPNumOut(self.width, False)
  48
  49         div = Div(a.m_width*2 + 3) # double the mantissa width plus g/r/sticky
  50
  51         of = Overflow()
  52         m.submodules.in_a = a
  53         m.submodules.in_b = b
  54         m.submodules.z = z
  55         m.submodules.of = of
  56
  57         with m.FSM() as fsm:
  58
  59             # ******
  60             # gets operand a
  61
  62             with m.State("get_a"):
  63                 self.get_op(m, self.in_a, a, "get_b")
  64
  65             # ******
  66             # gets operand b
  67
  68             with m.State("get_b"):
  69                 self.get_op(m, self.in_b, b, "special_cases")
  70
  71             # ******
  72             # special cases: NaNs, infs, zeros, denormalised
  73             # NOTE: some of these are unique to div.  see "Special Operations"
  74             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  75
  76             with m.State("special_cases"):
  77
  78                 # if a is NaN or b is NaN return NaN
  79                 with m.If(a.is_nan | b.is_nan):
  80                     m.next = "put_z"
  81                     m.d.sync += z.nan(1)
  82
  83                 # if a is Inf and b is Inf return NaN
  84                 with m.Elif(a.is_inf & b.is_inf):
  85                     m.next = "put_z"
  86                     m.d.sync += z.nan(1)
  87
  88                 # if a is inf return inf (or NaN if b is zero)
  89                 with m.Elif(a.is_inf):
  90                     m.next = "put_z"
  91                     m.d.sync += z.inf(a.s ^ b.s)
  92
  93                 # if b is inf return zero
  94                 with m.Elif(b.is_inf):
  95                     m.next = "put_z"
  96                     m.d.sync += z.zero(a.s ^ b.s)
  97
  98                 # if a is zero return zero (or NaN if b is zero)
  99                 with m.Elif(a.is_zero):
 100                     m.next = "put_z"
 101                     # if b is zero return NaN
 102                     with m.If(b.is_zero):
 103                         m.d.sync += z.nan(1)
 104                     with m.Else():
 105                         m.d.sync += z.zero(a.s ^ b.s)
 106
 107                 # if b is zero return Inf
 108                 with m.Elif(b.is_zero):
 109                     m.next = "put_z"
 110                     m.d.sync += z.inf(a.s ^ b.s)
 111
 112                 # Denormalised Number checks
 113                 with m.Else():
 114                     m.next = "normalise_a"
 115                     self.denormalise(m, a)
 116                     self.denormalise(m, b)
 117
 118             # ******
 119             # normalise_a
 120
 121             with m.State("normalise_a"):
 122                 self.op_normalise(m, a, "normalise_b")
 123
 124             # ******
 125             # normalise_b
 126
 127             with m.State("normalise_b"):
 128                 self.op_normalise(m, b, "divide_0")
 129
 130             # ******
 131             # First stage of divide.  initialise state
 132
 133             with m.State("divide_0"):
 134                 m.next = "divide_1"
 135                 m.d.sync += [
 136                     z.s.eq(a.s ^ b.s), # sign
 137                     z.e.eq(a.e - b.e), # exponent
 138                     div.dend.eq(a.m<<(a.m_width+3)), # 3 bits for g/r/sticky
 139                     div.dor.eq(b.m),
 140                 ]
 141                 div.reset(m)
 142
 143             # ******
 144             # Second stage of divide.
 145
 146             with m.State("divide_1"):
 147                 m.next = "divide_2"
 148                 m.d.sync += [
 149                     div.quot.eq(div.quot << 1),
 150                     div.rem.eq(Cat(div.dend[-1], div.rem[0:])),
 151                     div.dend.eq(div.dend << 1),
 152                 ]
 153
 154             # ******
 155             # Third stage of divide.
 156             # This stage ends by jumping out to divide_3
 157             # However it defaults to jumping to divide_1 (which comes back here)
 158
 159             with m.State("divide_2"):
 160                 with m.If(div.rem >= div.dor):
 161                     m.d.sync += [
 162                         div.quot[0].eq(1),
 163                         div.rem.eq(div.rem - div.dor),
 164                     ]
 165                 with m.If(div.count == div.width-2):
 166                     m.next = "divide_3"
 167                 with m.Else():
 168                     m.next = "divide_1"
 169                     m.d.sync += [
 170                         div.count.eq(div.count + 1),
 171                     ]
 172
 173             # ******
 174             # Fourth stage of divide.
 175
 176             with m.State("divide_3"):
 177                 m.next = "normalise_1"
 178                 m.d.sync += [
 179                     z.m.eq(div.quot[3:]),
 180                     of.guard.eq(div.quot[2]),
 181                     of.round_bit.eq(div.quot[1]),
 182                     of.sticky.eq(div.quot[0] | (div.rem != 0))
 183                 ]
 184
 185             # ******
 186             # First stage of normalisation.
 187
 188             with m.State("normalise_1"):
 189                 self.normalise_1(m, z, of, "normalise_2")
 190
 191             # ******
 192             # Second stage of normalisation.
 193
 194             with m.State("normalise_2"):
 195                 self.normalise_2(m, z, of, "round")
 196
 197             # ******
 198             # rounding stage
 199
 200             with m.State("round"):
 201                 self.roundz(m, z, of.roundz)
 202                 m.next = "corrections"
 203
 204             # ******
 205             # correction stage
 206
 207             with m.State("corrections"):
 208                 self.corrections(m, z, "pack")
 209
 210             # ******
 211             # pack stage
 212
 213             with m.State("pack"):
 214                 self.pack(m, z, "put_z")
 215
 216             # ******
 217             # put_z stage
 218
 219             with m.State("put_z"):
 220                 self.put_z(m, z, self.out_z, "get_a")
 221
 222         return m
 223
 224
 225 if __name__ == "__main__":
 226     alu = FPDIV(width=32)
 227     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 228
 229
 230     # works... but don't use, just do "python fname.py convert -t v"
 231     #print (verilog.convert(alu, ports=[
 232     #                        ports=alu.in_a.ports() + \
 233     #                              alu.in_b.ports() + \
 234     #                              alu.out_z.ports())