more experimentation on pipeline ObjectProxy
[ieee754fpu.git] / src / add / pipeline_example.py
1 """ Example 5: Making use of PyRTL and Introspection. """
2
3 from nmigen import Module, Signal, Const
4 from nmigen.cli import main, verilog, rtlil
5
6
7 from pipeline import SimplePipeline, ObjectProxy, PipeManager
8
9
10 class SimplePipelineExample(SimplePipeline):
11 """ A very simple pipeline to show how registers are inferred. """
12
13 def __init__(self, pipe):
14 SimplePipeline.__init__(self, pipe)
15 self._loopback = Signal(4)
16 self._setup()
17
18 def stage0(self):
19 self.n = ~self._loopback
20
21 def stage1(self):
22 self.n = self.n + 2
23
24 def stage2(self):
25 localv = Signal(4)
26 self._pipe.comb += localv.eq(2)
27 self.n = self.n << localv
28
29 def stage3(self):
30 self.n = ~self.n
31
32 def stage4(self):
33 self._pipe.sync += self._loopback.eq(self.n + 3)
34
35
36 class ObjectBasedPipelineExample(SimplePipeline):
37 """ A very simple pipeline to show how registers are inferred. """
38
39 def __init__(self, m):
40 SimplePipeline.__init__(self, m)
41 self._loopback = Signal(4)
42 o = ObjectProxy(m)
43 o.a = Signal(4)
44 o.b = Signal(4)
45 self._obj = o
46 self._setup()
47
48 def stage0(self):
49 self.n = ~self._loopback
50 self.o = self._obj
51
52 def stage1(self):
53 self.n = self.n + self.o.a
54 o = ObjectProxy(self._m)
55 o.a = self.n
56 o.b = self.o.b + self.n + Const(5)
57 self.o = o
58
59 def stage2(self):
60 localv = Signal(4)
61 self._m.d.comb += localv.eq(2)
62 self.n = self.n << localv
63 o = ObjectProxy(self._m)
64 o.b = self.n + self.o.a + self.o.b
65 self.o = o
66
67 def stage3(self):
68 self.n = ~self.n
69 self.o = self.o
70 self.o.b = self.o.b + self.n
71
72 def stage4(self):
73 self._m.d.sync += self._loopback.eq(self.n + 3 + self.o.b)
74
75
76 class PipeModule:
77
78 def __init__(self):
79 self.m = Module()
80 self.p = ObjectBasedPipelineExample(self.m)
81
82 def get_fragment(self, platform=None):
83 return self.m
84
85
86 class PipelineStageExample:
87
88 def __init__(self):
89 self._loopback = Signal(4)
90
91 def get_fragment(self, platform=None):
92
93 m = Module()
94
95 with PipeManager(m, pipemode=True) as pipe:
96
97 with pipe.Stage("first", ispec=[self._loopback]) as (p, m):
98 p.n = ~self._loopback
99 with pipe.Stage("second", p) as (p, m):
100 #p.n = ~self._loopback + 2
101 p.n = p.n + 2
102 with pipe.Stage("third", p) as (p, m):
103 #p.n = ~self._loopback + 5
104 localv = Signal(4)
105 m.d.comb += localv.eq(2)
106 p.n = p.n << localv + 1
107 #p.m = p.n + 2
108
109 print (pipe.stages)
110
111 return m
112
113 class PipelineStageObjectExample:
114
115 def __init__(self):
116 self._loopback = Signal(4)
117
118 def get_fragment(self, platform=None):
119
120 m = Module()
121
122 o = ObjectProxy(m, pipemode=False)
123 o.a = Signal(4)
124 o.b = Signal(4)
125 self.obj = o
126
127 localv2 = Signal(4)
128 m.d.sync += localv2.eq(localv2 + 3)
129
130 #m.d.comb += self.obj.a.eq(localv2 + 1)
131 #m.d.sync += self._loopback.eq(localv2)
132
133 with PipeManager(m, pipemode=True) as pipe:
134
135 with pipe.Stage("first",
136 ispec=[self._loopback, self.obj]) as (p, m):
137 p.n = ~self._loopback
138 p.o = self.obj
139 with pipe.Stage("second", p) as (p, m):
140 #p.n = ~self._loopback + 2
141 p.n = p.n + Const(2)
142 o = ObjectProxy(m, pipemode=False)
143 o.a = p.n
144 o.b = p.o.b + p.n + Const(5)
145 p.o = o
146 with pipe.Stage("third", p) as (p, m):
147 #p.n = ~self._loopback + 5
148 localv = Signal(4)
149 m.d.comb += localv.eq(2)
150 p.n = p.n << localv
151 o = ObjectProxy(m, pipemode=False)
152 o.b = p.n + p.o.b + p.o.a
153 p.o = o
154
155 print ("stages", pipe.stages)
156
157 return m
158
159
160
161 if __name__ == "__main__":
162 example = PipeModule()
163 with open("pipe_module.il", "w") as f:
164 f.write(rtlil.convert(example, ports=[
165 example.p._loopback,
166 ]))
167 example = PipelineStageExample()
168 with open("pipe_stage_module.il", "w") as f:
169 f.write(rtlil.convert(example, ports=[
170 example._loopback,
171 ]))
172 example = PipelineStageObjectExample()
173 with open("pipe_stage_object_module.il", "w") as f:
174 f.write(rtlil.convert(example, ports=[
175 example._loopback,
176 ]))