src/add/pipeline_example.py

   1 """ Example 5: Making use of PyRTL and Introspection. """
   2
   3 from copy import deepcopy
   4 from nmigen import Module, Signal
   5 from nmigen.cli import main, verilog
   6
   7
   8 from pipeline import SimplePipeline
   9
  10
  11 class SimplePipelineExample(SimplePipeline):
  12     """ A very simple pipeline to show how registers are inferred. """
  13
  14     def __init__(self, pipe):
  15         SimplePipeline.__init__(self, pipe)
  16         self._loopback = Signal(4)
  17         self._setup()
  18
  19     def stage0(self):
  20         self.n = ~self._loopback
  21
  22     def stage1(self):
  23         self.n = self.n + 1
  24
  25     def stage2(self):
  26         self.n = self.n << 1
  27
  28     def stage3(self):
  29         self.n = ~self.n
  30
  31     def stage4(self):
  32         self._pipe.sync += self._loopback.eq(self.n + 3)
  33
  34 class PipeModule:
  35
  36     def __init__(self):
  37         self.m = Module()
  38         self.p = SimplePipelineExample(self.m.d)
  39
  40     def get_fragment(self, platform=None):
  41         return self.m
  42
  43 if __name__ == "__main__":
  44     example = PipeModule()
  45     main(example, ports=[
  46                     example.p._loopback,
  47         ])
  48
  49     print(verilog.convert(example, ports=[
  50                example.p._loopback,
  51              ]))