src/add/pipeline_example.py

   1 """ Example 5: Making use of PyRTL and Introspection. """
   2
   3 from nmigen import Module, Signal
   4 from nmigen.cli import main, verilog
   5
   6
   7 from pipeline import SimplePipeline, ObjectProxy
   8
   9
  10 class SimplePipelineExample(SimplePipeline):
  11     """ A very simple pipeline to show how registers are inferred. """
  12
  13     def __init__(self, pipe):
  14         SimplePipeline.__init__(self, pipe)
  15         self._loopback = Signal(4)
  16         self._obj = ObjectProxy(pipe)
  17         self._obj.a = Signal(4)
  18         self._obj.b = Signal(4)
  19         self._setup()
  20
  21     def stage0(self):
  22         self.n = ~self._loopback
  23         self.o = self._obj
  24
  25     def stage1(self):
  26         self.n = self.n + self.o.a
  27         self.o = self.o
  28         self.o.a = self.n
  29         self.o.b = self.o.b
  30
  31     def stage2(self):
  32         localv = Signal(4)
  33         self._pipe.comb += localv.eq(2)
  34         self.n = self.n << localv
  35         self.o = self.o
  36         self.o.b = self.n + self.o.a + self.o.b
  37
  38     def stage3(self):
  39         self.n = ~self.n
  40         self.o = self.o
  41         self.o.b = self.o.b + self.n
  42
  43     def stage4(self):
  44         self.o.b = self.o.b
  45         self._pipe.sync += self._loopback.eq(self.n + 3 + self.o.b)
  46
  47 class PipeModule:
  48
  49     def __init__(self):
  50         self.m = Module()
  51         self.p = SimplePipelineExample(self.m.d)
  52
  53     def get_fragment(self, platform=None):
  54         return self.m
  55
  56 if __name__ == "__main__":
  57     example = PipeModule()
  58     main(example, ports=[
  59                     example.p._loopback,
  60         ])
  61
  62     #print(verilog.convert(example, ports=[
  63     #           example.p._loopback,
  64     #         ]))