src/add/queue.py

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  25
  26 from nmigen import Module, Signal, Memory, Mux
  27 from nmigen.tools import bits_for
  28 from nmigen.cli import main
  29 from nmigen.lib.fifo import FIFOInterface
  30
  31 # translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185   # noqa
  32
  33
  34 class Queue(FIFOInterface):
  35     def __init__(self, width, depth, fwft=True, pipe=False):
  36         """ Queue (FIFO) with pipe mode and first-write fall-through capability
  37
  38             * width: width of Queue data in/out
  39             * depth: queue depth.  NOTE: may be set to 0 (this is ok)
  40             * fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
  41             * pipe : pipe mode.  NOTE: this mode can cause unanticipated
  42                      problems.  when read is enabled, so is writeable.
  43                      therefore if read is enabled, the data ABSOLUTELY MUST
  44                      be read.
  45
  46             din  = enq_data, writable  = enq_ready, we = enq_valid
  47             dout = deq_data, re = deq_ready, readable = deq_valid
  48         """
  49         FIFOInterface.__init__(self, width, depth, fwft)
  50         self.pipe = pipe
  51         self.depth = depth
  52         self.count = Signal(bits_for(depth))
  53
  54     def elaborate(self, platform):
  55         m = Module()
  56
  57         # set up an SRAM.  XXX bug in Memory: cannot create SRAM of depth 1
  58         ram = Memory(self.width, self.depth if self.depth > 1 else 2)
  59         m.submodules.ram_read = ram_read = ram.read_port(synchronous=False)
  60         m.submodules.ram_write = ram_write = ram.write_port()
  61
  62         # convenience names
  63         p_o_ready = self.writable
  64         p_i_valid = self.we
  65         enq_data = self.din
  66
  67         n_o_valid = self.readable
  68         n_i_ready = self.re
  69         deq_data = self.dout
  70
  71         # intermediaries
  72         ptr_width = bits_for(self.depth - 1) if self.depth > 1 else 0
  73         enq_ptr = Signal(ptr_width) # cyclic pointer to "insert" point (wrport)
  74         deq_ptr = Signal(ptr_width) # cyclic pointer to "remove" point (rdport)
  75         maybe_full = Signal() # not reset_less (set by sync)
  76
  77         # temporaries
  78         do_enq = Signal(reset_less=True)
  79         do_deq = Signal(reset_less=True)
  80         ptr_diff = Signal(ptr_width)
  81         ptr_match = Signal(reset_less=True)
  82         empty = Signal(reset_less=True)
  83         full = Signal(reset_less=True)
  84         enq_max = Signal(reset_less=True)
  85         deq_max = Signal(reset_less=True)
  86
  87         m.d.comb += [ptr_match.eq(enq_ptr == deq_ptr), # read-ptr = write-ptr
  88                      ptr_diff.eq(enq_ptr - deq_ptr),
  89                      enq_max.eq(enq_ptr == self.depth - 1),
  90                      deq_max.eq(deq_ptr == self.depth - 1),
  91                      empty.eq(ptr_match & ~maybe_full),
  92                      full.eq(ptr_match & maybe_full),
  93                      do_enq.eq(p_o_ready & p_i_valid), # write conditions ok
  94                      do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
  95
  96                      # set readable and writable (NOTE: see pipe mode below)
  97                      n_o_valid.eq(~empty), # cannot read if empty!
  98                      p_o_ready.eq(~full),  # cannot write if full!
  99
 100                      # set up memory and connect to input and output
 101                      ram_write.addr.eq(enq_ptr),
 102                      ram_write.data.eq(enq_data),
 103                      ram_write.en.eq(do_enq),
 104                      ram_read.addr.eq(deq_ptr),
 105                      deq_data.eq(ram_read.data) # NOTE: overridden in fwft mode
 106                     ]
 107
 108         # under write conditions, SRAM write-pointer moves on next clock
 109         with m.If(do_enq):
 110             m.d.sync += enq_ptr.eq(Mux(enq_max, 0, enq_ptr+1))
 111
 112         # under read conditions, SRAM read-pointer moves on next clock
 113         with m.If(do_deq):
 114             m.d.sync += deq_ptr.eq(Mux(deq_max, 0, deq_ptr+1))
 115
 116         # if read-but-not-write or write-but-not-read, maybe_full set
 117         with m.If(do_enq != do_deq):
 118             m.d.sync += maybe_full.eq(do_enq)
 119
 120         # first-word fall-through: same as "flow" parameter in Chisel3 Queue
 121         # basically instead of relying on the Memory characteristics (which
 122         # in FPGAs do not have write-through), then when the queue is empty
 123         # take the output directly from the input, i.e. *bypass* the SRAM.
 124         # this done combinatorially to give the exact same characteristics
 125         # as Memory "write-through"... without relying on a changing API
 126         if self.fwft:
 127             with m.If(p_i_valid):
 128                 m.d.comb += n_o_valid.eq(1)
 129             with m.If(empty):
 130                 m.d.comb += deq_data.eq(enq_data)
 131                 m.d.comb += do_deq.eq(0)
 132                 with m.If(n_i_ready):
 133                     m.d.comb += do_enq.eq(0)
 134
 135         # pipe mode: read-enabled requires writability.
 136         if self.pipe:
 137             with m.If(n_i_ready):
 138                 m.d.comb += p_o_ready.eq(1)
 139
 140         if self.depth == 1 << len(self.count):  # is depth a power of 2
 141             m.d.comb += self.count.eq(
 142                 Mux(self.maybe_full & ptr_match, self.depth, 0)
 143                 | self.ptr_diff)
 144         else:
 145             m.d.comb += self.count.eq(Mux(ptr_match,
 146                                           Mux(maybe_full, self.depth, 0),
 147                                           Mux(deq_ptr > enq_ptr,
 148                                               self.depth + ptr_diff,
 149                                               ptr_diff)))
 150
 151         return m
 152
 153
 154 if __name__ == "__main__":
 155     reg_stage = Queue(1, 1, pipe=True)
 156     break_ready_chain_stage = Queue(1, 1, pipe=True, fwft=True)
 157     m = Module()
 158     ports = []
 159
 160     def queue_ports(queue, name_prefix):
 161         retval = []
 162         for name in ["count",
 163                      "dout",
 164                      "readable",
 165                      "writable"]:
 166             port = getattr(queue, name)
 167             signal = Signal(port.shape(), name=name_prefix+name)
 168             m.d.comb += signal.eq(port)
 169             retval.append(signal)
 170         for name in ["re",
 171                      "din",
 172                      "we"]:
 173             port = getattr(queue, name)
 174             signal = Signal(port.shape(), name=name_prefix+name)
 175             m.d.comb += port.eq(signal)
 176             retval.append(signal)
 177         return retval
 178     m.submodules.reg_stage = reg_stage
 179     ports += queue_ports(reg_stage, "reg_stage_")
 180     m.submodules.break_ready_chain_stage = break_ready_chain_stage
 181     ports += queue_ports(break_ready_chain_stage, "break_ready_chain_stage_")
 182     main(m, ports=ports)