src/add/record_experiment.py

   1 from nmigen import Module, Signal, Mux, Const
   2 from nmigen.hdl.rec import Record, Layout, DIR_NONE
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen.compat.fhdl.bitcontainer import value_bits_sign
   6 from singlepipe import flatten
   7
   8
   9 class RecordObject(Record):
  10     def __init__(self, name=None):
  11         Record.__init__(self, layout=[], name=None)
  12
  13     def __setattr__(self, k, v):
  14         if k in dir(Record) or "fields" not in self.__dict__:
  15             return object.__setattr__(self, k, v)
  16         self.__dict__["fields"][k] = v
  17         if isinstance(v, Record):
  18             newlayout = {k: (k, v.layout)}
  19         else:
  20             newlayout = {k: (k, v.shape())}
  21         self.__dict__["layout"].fields.update(newlayout)
  22
  23
  24 class RecordTest:
  25
  26     def __init__(self):
  27         self.r1 = RecordObject()
  28         self.r1.sig1 = Signal(32)
  29         self.r1.r2 = RecordObject()
  30         self.r1.r2.sig2 = Signal(32)
  31         self.r1.r3 = RecordObject()
  32         self.r1.r3.sig3 = Signal(32)
  33         self.sig123 = Signal(96)
  34
  35     def elaborate(self, platform):
  36         m = Module()
  37
  38         sig1 = Signal(32)
  39         m.d.comb += sig1.eq(self.r1.sig1)
  40         sig2 = Signal(32)
  41         m.d.comb += sig2.eq(self.r1.r2.sig2)
  42
  43         print (self.r1.fields)
  44         print (self.r1.shape())
  45         print (len(self.r1))
  46         m.d.comb += self.sig123.eq(flatten(self.r1))
  47
  48         return m
  49
  50
  51 def testbench(dut):
  52     yield dut.r1.sig1.eq(5)
  53     yield dut.r1.r2.sig2.eq(10)
  54
  55     sig1 = yield dut.r1.sig1
  56     assert sig1 == 5
  57     sig2 = yield dut.r1.r2.sig2
  58     assert sig2 == 10
  59
  60
  61
  62 ######################################################################
  63 # Unit Tests
  64 ######################################################################
  65
  66 if __name__ == '__main__':
  67     print ("test 1")
  68     dut = RecordTest()
  69     run_simulation(dut, testbench(dut), vcd_name="test_record1.vcd")
  70     vl = rtlil.convert(dut, ports=[dut.sig123, dut.r1.sig1, dut.r1.r2.sig2])
  71     with open("test_record1.il", "w") as f:
  72         f.write(vl)
  73