src/add/rstation_row.py

   1 from nmigen import Signal, Cat, Const, Mux, Module
   2
   3 from nmigen.cli import main, verilog
   4
   5 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
   6 from fpbase import MultiShiftRMerge
   7
   8 class ReservationStationRow:
   9
  10     def __init__(self, width, id_wid):
  11         """ Reservation Station row
  12
  13             * width: bit-width of IEEE754.  supported: 16, 32, 64
  14             * id_wid: an identifier to be passed through to the FunctionUnit
  15         """
  16         self.width = width
  17
  18         self.in_a  = Signal(width)
  19         self.in_b  = Signal(width)
  20         self.id_wid = id_wid
  21         self.out_z = Signal(width)
  22
  23     def elaborate(self, platform=None):
  24         """ creates the HDL code-fragment for ReservationStationRow
  25         """
  26         m = Module()
  27
  28         return m
  29
  30
  31 if __name__ == "__main__":
  32     rs = ReservationStationRow(width=32, id_wid=Const(1,4))
  33     main(alu, ports=[rs.in_a, rs.in_b, rs.out_z]
  34
  35     # works... but don't use, just do "python fname.py convert -t v"
  36     #print (verilog.convert(alu, ports=[
  37     #                        ports=alu.in_a.ports() + \
  38     #                              alu.in_b.ports() + \
  39     #                              alu.out_z.ports())