src/add/singlepipe.py

   1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
   2     For multi-input and multi-output variants, see multipipe.
   3
   4     Associated development bugs:
   5     * http://bugs.libre-riscv.org/show_bug.cgi?id=64
   6     * http://bugs.libre-riscv.org/show_bug.cgi?id=57
   7
   8     eq:
   9     --
  10
  11     a strategically very important function that is identical in function
  12     to nmigen's Signal.eq function, except it may take objects, or a list
  13     of objects, or a tuple of objects, and where objects may also be
  14     Records.
  15
  16     Stage API:
  17     ---------
  18
  19     stage requires compliance with a strict API that may be
  20     implemented in several means, including as a static class.
  21     the methods of a stage instance must be as follows:
  22
  23     * ispec() - Input data format specification
  24                 returns an object or a list or tuple of objects, or
  25                 a Record, each object having an "eq" function which
  26                 takes responsibility for copying by assignment all
  27                 sub-objects
  28     * ospec() - Output data format specification
  29                 requirements as for ospec
  30     * process(m, i) - Processes an ispec-formatted object
  31                 returns a combinatorial block of a result that
  32                 may be assigned to the output, by way of the "eq"
  33                 function
  34     * setup(m, i) - Optional function for setting up submodules
  35                 may be used for more complex stages, to link
  36                 the input (i) to submodules.  must take responsibility
  37                 for adding those submodules to the module (m).
  38                 the submodules must be combinatorial blocks and
  39                 must have their inputs and output linked combinatorially.
  40
  41     Both StageCls (for use with non-static classes) and Stage (for use
  42     by static classes) are abstract classes from which, for convenience
  43     and as a courtesy to other developers, anything conforming to the
  44     Stage API may *choose* to derive.
  45
  46     StageChain:
  47     ----------
  48
  49     A useful combinatorial wrapper around stages that chains them together
  50     and then presents a Stage-API-conformant interface.  By presenting
  51     the same API as the stages it wraps, it can clearly be used recursively.
  52
  53     RecordBasedStage:
  54     ----------------
  55
  56     A convenience class that takes an input shape, output shape, a
  57     "processing" function and an optional "setup" function.  Honestly
  58     though, there's not much more effort to just... create a class
  59     that returns a couple of Records (see ExampleAddRecordStage in
  60     examples).
  61
  62     PassThroughStage:
  63     ----------------
  64
  65     A convenience class that takes a single function as a parameter,
  66     that is chain-called to create the exact same input and output spec.
  67     It has a process() function that simply returns its input.
  68
  69     Instances of this class are completely redundant if handed to
  70     StageChain, however when passed to UnbufferedPipeline they
  71     can be used to introduce a single clock delay.
  72
  73     ControlBase:
  74     -----------
  75
  76     The base class for pipelines.  Contains previous and next ready/valid/data.
  77     Also has an extremely useful "connect" function that can be used to
  78     connect a chain of pipelines and present the exact same prev/next
  79     ready/valid/data API.
  80
  81     UnbufferedPipeline:
  82     ------------------
  83
  84     A simple stalling clock-synchronised pipeline that has no buffering
  85     (unlike BufferedHandshake).  Data flows on *every* clock cycle when
  86     the conditions are right (this is nominally when the input is valid
  87     and the output is ready).
  88
  89     A stall anywhere along the line will result in a stall back-propagating
  90     down the entire chain.  The BufferedHandshake by contrast will buffer
  91     incoming data, allowing previous stages one clock cycle's grace before
  92     also having to stall.
  93
  94     An advantage of the UnbufferedPipeline over the Buffered one is
  95     that the amount of logic needed (number of gates) is greatly
  96     reduced (no second set of buffers basically)
  97
  98     The disadvantage of the UnbufferedPipeline is that the valid/ready
  99     logic, if chained together, is *combinatorial*, resulting in
 100     progressively larger gate delay.
 101
 102     PassThroughHandshake:
 103     ------------------
 104
 105     A Control class that introduces a single clock delay, passing its
 106     data through unaltered.  Unlike RegisterPipeline (which relies
 107     on UnbufferedPipeline and PassThroughStage) it handles ready/valid
 108     itself.
 109
 110     RegisterPipeline:
 111     ----------------
 112
 113     A convenience class that, because UnbufferedPipeline introduces a single
 114     clock delay, when its stage is a PassThroughStage, it results in a Pipeline
 115     stage that, duh, delays its (unmodified) input by one clock cycle.
 116
 117     BufferedHandshake:
 118     ----------------
 119
 120     nmigen implementation of buffered pipeline stage, based on zipcpu:
 121     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
 122
 123     this module requires quite a bit of thought to understand how it works
 124     (and why it is needed in the first place).  reading the above is
 125     *strongly* recommended.
 126
 127     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
 128     the STB / ACK signals to raise and lower (on separate clocks) before
 129     data may proceeed (thus only allowing one piece of data to proceed
 130     on *ALTERNATE* cycles), the signalling here is a true pipeline
 131     where data will flow on *every* clock when the conditions are right.
 132
 133     input acceptance conditions are when:
 134         * incoming previous-stage strobe (p.i_valid) is HIGH
 135         * outgoing previous-stage ready   (p.o_ready) is LOW
 136
 137     output transmission conditions are when:
 138         * outgoing next-stage strobe (n.o_valid) is HIGH
 139         * outgoing next-stage ready   (n.i_ready) is LOW
 140
 141     the tricky bit is when the input has valid data and the output is not
 142     ready to accept it.  if it wasn't for the clock synchronisation, it
 143     would be possible to tell the input "hey don't send that data, we're
 144     not ready".  unfortunately, it's not possible to "change the past":
 145     the previous stage *has no choice* but to pass on its data.
 146
 147     therefore, the incoming data *must* be accepted - and stored: that
 148     is the responsibility / contract that this stage *must* accept.
 149     on the same clock, it's possible to tell the input that it must
 150     not send any more data.  this is the "stall" condition.
 151
 152     we now effectively have *two* possible pieces of data to "choose" from:
 153     the buffered data, and the incoming data.  the decision as to which
 154     to process and output is based on whether we are in "stall" or not.
 155     i.e. when the next stage is no longer ready, the output comes from
 156     the buffer if a stall had previously occurred, otherwise it comes
 157     direct from processing the input.
 158
 159     this allows us to respect a synchronous "travelling STB" with what
 160     dan calls a "buffered handshake".
 161
 162     it's quite a complex state machine!
 163
 164     SimpleHandshake
 165     ---------------
 166
 167     Synchronised pipeline, Based on:
 168     https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
 169 """
 170
 171 from nmigen import Signal, Cat, Const, Mux, Module, Value
 172 from nmigen.cli import verilog, rtlil
 173 from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
 174 from nmigen.hdl.ast import ArrayProxy
 175 from nmigen.hdl.rec import Record, Layout
 176
 177 from abc import ABCMeta, abstractmethod
 178 from collections.abc import Sequence
 179 from queue import Queue
 180
 181
 182 class RecordObject(Record):
 183     def __init__(self, layout=None, name=None):
 184         Record.__init__(self, layout=layout or [], name=None)
 185
 186     def __setattr__(self, k, v):
 187         if k in dir(Record) or "fields" not in self.__dict__:
 188             return object.__setattr__(self, k, v)
 189         self.fields[k] = v
 190         if isinstance(v, Record):
 191             newlayout = {k: (k, v.layout)}
 192         else:
 193             newlayout = {k: (k, v.shape())}
 194         self.layout.fields.update(newlayout)
 195
 196     def __iter__(self):
 197         for x in self.fields.values():
 198             yield x
 199
 200     def ports(self):
 201         return list(self)
 202
 203
 204 class PrevControl:
 205     """ contains signals that come *from* the previous stage (both in and out)
 206         * i_valid: previous stage indicating all incoming data is valid.
 207                    may be a multi-bit signal, where all bits are required
 208                    to be asserted to indicate "valid".
 209         * o_ready: output to next stage indicating readiness to accept data
 210         * i_data : an input - added by the user of this class
 211     """
 212
 213     def __init__(self, i_width=1, stage_ctl=False):
 214         self.stage_ctl = stage_ctl
 215         self.i_valid = Signal(i_width, name="p_i_valid") # prev   >>in  self
 216         self._o_ready = Signal(name="p_o_ready") # prev   <<out self
 217         self.i_data = None # XXX MUST BE ADDED BY USER
 218         if stage_ctl:
 219             self.s_o_ready = Signal(name="p_s_o_rdy") # prev   <<out self
 220         self.trigger = Signal(reset_less=True)
 221
 222     @property
 223     def o_ready(self):
 224         """ public-facing API: indicates (externally) that stage is ready
 225         """
 226         if self.stage_ctl:
 227             return self.s_o_ready # set dynamically by stage
 228         return self._o_ready      # return this when not under dynamic control
 229
 230     def _connect_in(self, prev, direct=False, fn=None):
 231         """ internal helper function to connect stage to an input source.
 232             do not use to connect stage-to-stage!
 233         """
 234         i_valid = prev.i_valid if direct else prev.i_valid_test
 235         i_data = fn(prev.i_data) if fn is not None else prev.i_data
 236         return [self.i_valid.eq(i_valid),
 237                 prev.o_ready.eq(self.o_ready),
 238                 eq(self.i_data, i_data),
 239                ]
 240
 241     @property
 242     def i_valid_test(self):
 243         vlen = len(self.i_valid)
 244         if vlen > 1:
 245             # multi-bit case: valid only when i_valid is all 1s
 246             all1s = Const(-1, (len(self.i_valid), False))
 247             i_valid = (self.i_valid == all1s)
 248         else:
 249             # single-bit i_valid case
 250             i_valid = self.i_valid
 251
 252         # when stage indicates not ready, incoming data
 253         # must "appear" to be not ready too
 254         if self.stage_ctl:
 255             i_valid = i_valid & self.s_o_ready
 256
 257         return i_valid
 258
 259     def elaborate(self, platform):
 260         m = Module()
 261         m.d.comb += self.trigger.eq(self.i_valid_test & self.o_ready)
 262         return m
 263
 264     def eq(self, i):
 265         return [self.i_data.eq(i.i_data),
 266                 self.o_ready.eq(i.o_ready),
 267                 self.i_valid.eq(i.i_valid)]
 268
 269     def __iter__(self):
 270         yield self.i_valid
 271         yield self.o_ready
 272         if hasattr(self.i_data, "ports"):
 273             yield from self.i_data.ports()
 274         elif isinstance(self.i_data, Sequence):
 275             yield from self.i_data
 276         else:
 277             yield self.i_data
 278
 279     def ports(self):
 280         return list(self)
 281
 282
 283 class NextControl:
 284     """ contains the signals that go *to* the next stage (both in and out)
 285         * o_valid: output indicating to next stage that data is valid
 286         * i_ready: input from next stage indicating that it can accept data
 287         * o_data : an output - added by the user of this class
 288     """
 289     def __init__(self, stage_ctl=False):
 290         self.stage_ctl = stage_ctl
 291         self.o_valid = Signal(name="n_o_valid") # self out>>  next
 292         self.i_ready = Signal(name="n_i_ready") # self <<in   next
 293         self.o_data = None # XXX MUST BE ADDED BY USER
 294         #if self.stage_ctl:
 295         self.d_valid = Signal(reset=1) # INTERNAL (data valid)
 296         self.trigger = Signal(reset_less=True)
 297
 298     @property
 299     def i_ready_test(self):
 300         if self.stage_ctl:
 301             return self.i_ready & self.d_valid
 302         return self.i_ready
 303
 304     def connect_to_next(self, nxt):
 305         """ helper function to connect to the next stage data/valid/ready.
 306             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
 307             use this when connecting stage-to-stage
 308         """
 309         return [nxt.i_valid.eq(self.o_valid),
 310                 self.i_ready.eq(nxt.o_ready),
 311                 eq(nxt.i_data, self.o_data),
 312                ]
 313
 314     def _connect_out(self, nxt, direct=False, fn=None):
 315         """ internal helper function to connect stage to an output source.
 316             do not use to connect stage-to-stage!
 317         """
 318         i_ready = nxt.i_ready if direct else nxt.i_ready_test
 319         o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
 320         return [nxt.o_valid.eq(self.o_valid),
 321                 self.i_ready.eq(i_ready),
 322                 eq(o_data, self.o_data),
 323                ]
 324
 325     def elaborate(self, platform):
 326         m = Module()
 327         m.d.comb += self.trigger.eq(self.i_ready_test & self.o_valid)
 328         return m
 329
 330     def __iter__(self):
 331         yield self.i_ready
 332         yield self.o_valid
 333         if hasattr(self.o_data, "ports"):
 334             yield from self.o_data.ports()
 335         elif isinstance(self.o_data, Sequence):
 336             yield from self.o_data
 337         else:
 338             yield self.o_data
 339
 340     def ports(self):
 341         return list(self)
 342
 343
 344 class Visitor2:
 345     """ a helper class for iterating twin-argument compound data structures.
 346
 347         Record is a special (unusual, recursive) case, where the input may be
 348         specified as a dictionary (which may contain further dictionaries,
 349         recursively), where the field names of the dictionary must match
 350         the Record's field spec.  Alternatively, an object with the same
 351         member names as the Record may be assigned: it does not have to
 352         *be* a Record.
 353
 354         ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
 355         has an eq function, the object being assigned to it (e.g. a python
 356         object) might not.  despite the *input* having an eq function,
 357         that doesn't help us, because it's the *ArrayProxy* that's being
 358         assigned to.  so.... we cheat.  use the ports() function of the
 359         python object, enumerate them, find out the list of Signals that way,
 360         and assign them.
 361     """
 362     def iterator2(self, o, i):
 363         if isinstance(o, dict):
 364             yield from self.dict_iter2(o, i)
 365
 366         if not isinstance(o, Sequence):
 367             o, i = [o], [i]
 368         for (ao, ai) in zip(o, i):
 369             #print ("visit", fn, ao, ai)
 370             if isinstance(ao, Record):
 371                 yield from self.record_iter2(ao, ai)
 372             elif isinstance(ao, ArrayProxy) and not isinstance(ai, Value):
 373                 yield from self.arrayproxy_iter2(ao, ai)
 374             else:
 375                 yield (ao, ai)
 376
 377     def dict_iter2(self, o, i):
 378         for (k, v) in o.items():
 379             print ("d-iter", v, i[k])
 380             yield (v, i[k])
 381         return res
 382
 383     def _not_quite_working_with_all_unit_tests_record_iter2(self, ao, ai):
 384         print ("record_iter2", ao, ai, type(ao), type(ai))
 385         if isinstance(ai, Value):
 386             if isinstance(ao, Sequence):
 387                 ao, ai = [ao], [ai]
 388             for o, i in zip(ao, ai):
 389                 yield (o, i)
 390             return
 391         for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 392             if isinstance(field_shape, Layout):
 393                 val = ai.fields
 394             else:
 395                 val = ai
 396             if hasattr(val, field_name): # check for attribute
 397                 val = getattr(val, field_name)
 398             else:
 399                 val = val[field_name] # dictionary-style specification
 400             yield from self.iterator2(ao.fields[field_name], val)
 401
 402     def record_iter2(self, ao, ai):
 403         for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 404             if isinstance(field_shape, Layout):
 405                 val = ai.fields
 406             else:
 407                 val = ai
 408             if hasattr(val, field_name): # check for attribute
 409                 val = getattr(val, field_name)
 410             else:
 411                 val = val[field_name] # dictionary-style specification
 412             yield from self.iterator2(ao.fields[field_name], val)
 413
 414     def arrayproxy_iter2(self, ao, ai):
 415         for p in ai.ports():
 416             op = getattr(ao, p.name)
 417             print ("arrayproxy - p", p, p.name)
 418             yield from self.iterator2(op, p)
 419
 420
 421 class Visitor:
 422     """ a helper class for iterating single-argument compound data structures.
 423         similar to Visitor2.
 424     """
 425     def iterate(self, i):
 426         """ iterate a compound structure recursively using yield
 427         """
 428         if not isinstance(i, Sequence):
 429             i = [i]
 430         for ai in i:
 431             print ("iterate", ai)
 432             if isinstance(ai, Record):
 433                 print ("record", list(ai.layout))
 434                 yield from self.record_iter(ai)
 435             elif isinstance(ai, ArrayProxy) and not isinstance(ai, Value):
 436                 yield from self.array_iter(ai)
 437             else:
 438                 yield ai
 439
 440     def record_iter(self, ai):
 441         for idx, (field_name, field_shape, _) in enumerate(ai.layout):
 442             if isinstance(field_shape, Layout):
 443                 val = ai.fields
 444             else:
 445                 val = ai
 446             if hasattr(val, field_name): # check for attribute
 447                 val = getattr(val, field_name)
 448             else:
 449                 val = val[field_name] # dictionary-style specification
 450             print ("recidx", idx, field_name, field_shape, val)
 451             yield from self.iterate(val)
 452
 453     def array_iter(self, ai):
 454         for p in ai.ports():
 455             yield from self.iterate(p)
 456
 457
 458 def eq(o, i):
 459     """ makes signals equal: a helper routine which identifies if it is being
 460         passed a list (or tuple) of objects, or signals, or Records, and calls
 461         the objects' eq function.
 462     """
 463     res = []
 464     for (ao, ai) in Visitor2().iterator2(o, i):
 465         rres = ao.eq(ai)
 466         if not isinstance(rres, Sequence):
 467             rres = [rres]
 468         res += rres
 469     return res
 470
 471
 472 def shape(i):
 473     print ("shape", i)
 474     r = 0
 475     for part in list(i):
 476         print ("shape?", part)
 477         s, _ = part.shape()
 478         r += s
 479     return r, False
 480
 481
 482 def cat(i):
 483     """ flattens a compound structure recursively using Cat
 484     """
 485     from nmigen.tools import flatten
 486     #res = list(flatten(i)) # works (as of nmigen commit f22106e5) HOWEVER...
 487     res = list(Visitor().iterate(i)) # needed because input may be a sequence
 488     return Cat(*res)
 489
 490
 491 class StageCls(metaclass=ABCMeta):
 492     """ Class-based "Stage" API.  requires instantiation (after derivation)
 493
 494         see "Stage API" above..  Note: python does *not* require derivation
 495         from this class.  All that is required is that the pipelines *have*
 496         the functions listed in this class.  Derivation from this class
 497         is therefore merely a "courtesy" to maintainers.
 498     """
 499     @abstractmethod
 500     def ispec(self): pass       # REQUIRED
 501     @abstractmethod
 502     def ospec(self): pass       # REQUIRED
 503     #@abstractmethod
 504     #def setup(self, m, i): pass # OPTIONAL
 505     @abstractmethod
 506     def process(self, i): pass  # REQUIRED
 507
 508
 509 class Stage(metaclass=ABCMeta):
 510     """ Static "Stage" API.  does not require instantiation (after derivation)
 511
 512         see "Stage API" above.  Note: python does *not* require derivation
 513         from this class.  All that is required is that the pipelines *have*
 514         the functions listed in this class.  Derivation from this class
 515         is therefore merely a "courtesy" to maintainers.
 516     """
 517     @staticmethod
 518     @abstractmethod
 519     def ispec(): pass
 520
 521     @staticmethod
 522     @abstractmethod
 523     def ospec(): pass
 524
 525     #@staticmethod
 526     #@abstractmethod
 527     #def setup(m, i): pass
 528
 529     @staticmethod
 530     @abstractmethod
 531     def process(i): pass
 532
 533
 534 class RecordBasedStage(Stage):
 535     """ convenience class which provides a Records-based layout.
 536         honestly it's a lot easier just to create a direct Records-based
 537         class (see ExampleAddRecordStage)
 538     """
 539     def __init__(self, in_shape, out_shape, processfn, setupfn=None):
 540         self.in_shape = in_shape
 541         self.out_shape = out_shape
 542         self.__process = processfn
 543         self.__setup = setupfn
 544     def ispec(self): return Record(self.in_shape)
 545     def ospec(self): return Record(self.out_shape)
 546     def process(seif, i): return self.__process(i)
 547     def setup(seif, m, i): return self.__setup(m, i)
 548
 549
 550 class StageChain(StageCls):
 551     """ pass in a list of stages, and they will automatically be
 552         chained together via their input and output specs into a
 553         combinatorial chain.
 554
 555         the end result basically conforms to the exact same Stage API.
 556
 557         * input to this class will be the input of the first stage
 558         * output of first stage goes into input of second
 559         * output of second goes into input into third (etc. etc.)
 560         * the output of this class will be the output of the last stage
 561     """
 562     def __init__(self, chain, specallocate=False):
 563         self.chain = chain
 564         self.specallocate = specallocate
 565
 566     def ispec(self):
 567         return self.chain[0].ispec()
 568
 569     def ospec(self):
 570         return self.chain[-1].ospec()
 571
 572     def _specallocate_setup(self, m, i):
 573         for (idx, c) in enumerate(self.chain):
 574             if hasattr(c, "setup"):
 575                 c.setup(m, i)               # stage may have some module stuff
 576             o = self.chain[idx].ospec()     # last assignment survives
 577             m.d.comb += eq(o, c.process(i)) # process input into "o"
 578             if idx == len(self.chain)-1:
 579                 break
 580             i = self.chain[idx+1].ispec()   # new input on next loop
 581             m.d.comb += eq(i, o)            # assign to next input
 582         return o                            # last loop is the output
 583
 584     def _noallocate_setup(self, m, i):
 585         for (idx, c) in enumerate(self.chain):
 586             if hasattr(c, "setup"):
 587                 c.setup(m, i)               # stage may have some module stuff
 588             i = o = c.process(i)            # store input into "o"
 589         return o                            # last loop is the output
 590
 591     def setup(self, m, i):
 592         if self.specallocate:
 593             self.o = self._specallocate_setup(m, i)
 594         else:
 595             self.o = self._noallocate_setup(m, i)
 596
 597     def process(self, i):
 598         return self.o # conform to Stage API: return last-loop output
 599
 600
 601 class ControlBase:
 602     """ Common functions for Pipeline API
 603     """
 604     def __init__(self, stage=None, in_multi=None, stage_ctl=False):
 605         """ Base class containing ready/valid/data to previous and next stages
 606
 607             * p: contains ready/valid to the previous stage
 608             * n: contains ready/valid to the next stage
 609
 610             Except when calling Controlbase.connect(), user must also:
 611             * add i_data member to PrevControl (p) and
 612             * add o_data member to NextControl (n)
 613         """
 614         self.stage = stage
 615
 616         # set up input and output IO ACK (prev/next ready/valid)
 617         self.p = PrevControl(in_multi, stage_ctl)
 618         self.n = NextControl(stage_ctl)
 619
 620         # set up the input and output data
 621         if stage is not None:
 622             self.p.i_data = stage.ispec() # input type
 623             self.n.o_data = stage.ospec()
 624
 625     def connect_to_next(self, nxt):
 626         """ helper function to connect to the next stage data/valid/ready.
 627         """
 628         return self.n.connect_to_next(nxt.p)
 629
 630     def _connect_in(self, prev):
 631         """ internal helper function to connect stage to an input source.
 632             do not use to connect stage-to-stage!
 633         """
 634         return self.p._connect_in(prev.p)
 635
 636     def _connect_out(self, nxt):
 637         """ internal helper function to connect stage to an output source.
 638             do not use to connect stage-to-stage!
 639         """
 640         return self.n._connect_out(nxt.n)
 641
 642     def connect(self, pipechain):
 643         """ connects a chain (list) of Pipeline instances together and
 644             links them to this ControlBase instance:
 645
 646                       in <----> self <---> out
 647                        |                   ^
 648                        v                   |
 649                     [pipe1, pipe2, pipe3, pipe4]
 650                        |    ^  |    ^  |     ^
 651                        v    |  v    |  v     |
 652                      out---in out--in out---in
 653
 654             Also takes care of allocating i_data/o_data, by looking up
 655             the data spec for each end of the pipechain.  i.e It is NOT
 656             necessary to allocate self.p.i_data or self.n.o_data manually:
 657             this is handled AUTOMATICALLY, here.
 658
 659             Basically this function is the direct equivalent of StageChain,
 660             except that unlike StageChain, the Pipeline logic is followed.
 661
 662             Just as StageChain presents an object that conforms to the
 663             Stage API from a list of objects that also conform to the
 664             Stage API, an object that calls this Pipeline connect function
 665             has the exact same pipeline API as the list of pipline objects
 666             it is called with.
 667
 668             Thus it becomes possible to build up larger chains recursively.
 669             More complex chains (multi-input, multi-output) will have to be
 670             done manually.
 671         """
 672         eqs = [] # collated list of assignment statements
 673
 674         # connect inter-chain
 675         for i in range(len(pipechain)-1):
 676             pipe1 = pipechain[i]
 677             pipe2 = pipechain[i+1]
 678             eqs += pipe1.connect_to_next(pipe2)
 679
 680         # connect front of chain to ourselves
 681         front = pipechain[0]
 682         self.p.i_data = front.stage.ispec()
 683         eqs += front._connect_in(self)
 684
 685         # connect end of chain to ourselves
 686         end = pipechain[-1]
 687         self.n.o_data = end.stage.ospec()
 688         eqs += end._connect_out(self)
 689
 690         return eqs
 691
 692     def _postprocess(self, i): # XXX DISABLED
 693         return i # RETURNS INPUT
 694         if hasattr(self.stage, "postprocess"):
 695             return self.stage.postprocess(i)
 696         return i
 697
 698     def set_input(self, i):
 699         """ helper function to set the input data
 700         """
 701         return eq(self.p.i_data, i)
 702
 703     def __iter__(self):
 704         yield from self.p
 705         yield from self.n
 706
 707     def ports(self):
 708         return list(self)
 709
 710     def _elaborate(self, platform):
 711         """ handles case where stage has dynamic ready/valid functions
 712         """
 713         m = Module()
 714         m.submodules.p = self.p
 715         m.submodules.n = self.n
 716
 717         if self.stage is not None and hasattr(self.stage, "setup"):
 718             self.stage.setup(m, self.p.i_data)
 719
 720         if not self.p.stage_ctl:
 721             return m
 722
 723         # intercept the previous (outgoing) "ready", combine with stage ready
 724         m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.d_ready)
 725
 726         # intercept the next (incoming) "ready" and combine it with data valid
 727         sdv = self.stage.d_valid(self.n.i_ready)
 728         m.d.comb += self.n.d_valid.eq(self.n.i_ready & sdv)
 729
 730         return m
 731
 732
 733 class BufferedHandshake(ControlBase):
 734     """ buffered pipeline stage.  data and strobe signals travel in sync.
 735         if ever the input is ready and the output is not, processed data
 736         is shunted in a temporary register.
 737
 738         Argument: stage.  see Stage API above
 739
 740         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 741         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 742         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 743                               |             |
 744                             process --->----^
 745                               |             |
 746                               +-- r_data ->-+
 747
 748         input data p.i_data is read (only), is processed and goes into an
 749         intermediate result store [process()].  this is updated combinatorially.
 750
 751         in a non-stall condition, the intermediate result will go into the
 752         output (update_output).  however if ever there is a stall, it goes
 753         into r_data instead [update_buffer()].
 754
 755         when the non-stall condition is released, r_data is the first
 756         to be transferred to the output [flush_buffer()], and the stall
 757         condition cleared.
 758
 759         on the next cycle (as long as stall is not raised again) the
 760         input may begin to be processed and transferred directly to output.
 761     """
 762
 763     def elaborate(self, platform):
 764         self.m = ControlBase._elaborate(self, platform)
 765
 766         result = self.stage.ospec()
 767         r_data = self.stage.ospec()
 768
 769         # establish some combinatorial temporaries
 770         o_n_validn = Signal(reset_less=True)
 771         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
 772         nir_por = Signal(reset_less=True)
 773         nir_por_n = Signal(reset_less=True)
 774         p_i_valid = Signal(reset_less=True)
 775         nir_novn = Signal(reset_less=True)
 776         nirn_novn = Signal(reset_less=True)
 777         por_pivn = Signal(reset_less=True)
 778         npnn = Signal(reset_less=True)
 779         self.m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
 780                      o_n_validn.eq(~self.n.o_valid),
 781                      n_i_ready.eq(self.n.i_ready_test),
 782                      nir_por.eq(n_i_ready & self.p._o_ready),
 783                      nir_por_n.eq(n_i_ready & ~self.p._o_ready),
 784                      nir_novn.eq(n_i_ready | o_n_validn),
 785                      nirn_novn.eq(~n_i_ready & o_n_validn),
 786                      npnn.eq(nir_por | nirn_novn),
 787                      por_pivn.eq(self.p._o_ready & ~p_i_valid)
 788         ]
 789
 790         # store result of processing in combinatorial temporary
 791         self.m.d.comb += eq(result, self.stage.process(self.p.i_data))
 792
 793         # if not in stall condition, update the temporary register
 794         with self.m.If(self.p.o_ready): # not stalled
 795             self.m.d.sync += eq(r_data, result) # update buffer
 796
 797         # data pass-through conditions
 798         with self.m.If(npnn):
 799             o_data = self._postprocess(result)
 800             self.m.d.sync += [self.n.o_valid.eq(p_i_valid), # valid if p_valid
 801                               eq(self.n.o_data, o_data),    # update output
 802                              ]
 803         # buffer flush conditions (NOTE: can override data passthru conditions)
 804         with self.m.If(nir_por_n): # not stalled
 805             # Flush the [already processed] buffer to the output port.
 806             o_data = self._postprocess(r_data)
 807             self.m.d.sync += [self.n.o_valid.eq(1),  # reg empty
 808                               eq(self.n.o_data, o_data), # flush buffer
 809                              ]
 810         # output ready conditions
 811         self.m.d.sync += self.p._o_ready.eq(nir_novn | por_pivn)
 812
 813         return self.m
 814
 815
 816 class SimpleHandshake(ControlBase):
 817     """ simple handshake control.  data and strobe signals travel in sync.
 818         implements the protocol used by Wishbone and AXI4.
 819
 820         Argument: stage.  see Stage API above
 821
 822         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 823         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 824         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 825                               |             |
 826                               +--process->--^
 827         Truth Table
 828
 829         Inputs   Temporary  Output Data
 830         -------  ---------- -----  ----
 831         P P N N  PiV& ~NiR&  N P
 832         i o i o  PoR  NoV    o o
 833         V R R V              V R
 834
 835         -------   -    -     - -
 836         0 0 0 0   0    0    >0 0    reg
 837         0 0 0 1   0    1    >1 0    reg
 838         0 0 1 0   0    0     0 1    process(i_data)
 839         0 0 1 1   0    0     0 1    process(i_data)
 840         -------   -    -     - -
 841         0 1 0 0   0    0    >0 0    reg
 842         0 1 0 1   0    1    >1 0    reg
 843         0 1 1 0   0    0     0 1    process(i_data)
 844         0 1 1 1   0    0     0 1    process(i_data)
 845         -------   -    -     - -
 846         1 0 0 0   0    0    >0 0    reg
 847         1 0 0 1   0    1    >1 0    reg
 848         1 0 1 0   0    0     0 1    process(i_data)
 849         1 0 1 1   0    0     0 1    process(i_data)
 850         -------   -    -     - -
 851         1 1 0 0   1    0     1 0    process(i_data)
 852         1 1 0 1   1    1     1 0    process(i_data)
 853         1 1 1 0   1    0     1 1    process(i_data)
 854         1 1 1 1   1    0     1 1    process(i_data)
 855         -------   -    -     - -
 856     """
 857
 858     def elaborate(self, platform):
 859         self.m = m = ControlBase._elaborate(self, platform)
 860
 861         r_busy = Signal()
 862         result = self.stage.ospec()
 863
 864         # establish some combinatorial temporaries
 865         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
 866         p_i_valid_p_o_ready = Signal(reset_less=True)
 867         p_i_valid = Signal(reset_less=True)
 868         m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
 869                      n_i_ready.eq(self.n.i_ready_test),
 870                      p_i_valid_p_o_ready.eq(p_i_valid & self.p.o_ready),
 871         ]
 872
 873         # store result of processing in combinatorial temporary
 874         m.d.comb += eq(result, self.stage.process(self.p.i_data))
 875
 876         # previous valid and ready
 877         with m.If(p_i_valid_p_o_ready):
 878             o_data = self._postprocess(result)
 879             m.d.sync += [r_busy.eq(1),      # output valid
 880                          eq(self.n.o_data, o_data), # update output
 881                         ]
 882         # previous invalid or not ready, however next is accepting
 883         with m.Elif(n_i_ready):
 884             o_data = self._postprocess(result)
 885             m.d.sync += [eq(self.n.o_data, o_data)]
 886             # TODO: could still send data here (if there was any)
 887             #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
 888             m.d.sync += r_busy.eq(0) # ...so set output invalid
 889
 890         m.d.comb += self.n.o_valid.eq(r_busy)
 891         # if next is ready, so is previous
 892         m.d.comb += self.p._o_ready.eq(n_i_ready)
 893
 894         return self.m
 895
 896
 897 class UnbufferedPipeline(ControlBase):
 898     """ A simple pipeline stage with single-clock synchronisation
 899         and two-way valid/ready synchronised signalling.
 900
 901         Note that a stall in one stage will result in the entire pipeline
 902         chain stalling.
 903
 904         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 905         travel synchronously with the data: the valid/ready signalling
 906         combines in a *combinatorial* fashion.  Therefore, a long pipeline
 907         chain will lengthen propagation delays.
 908
 909         Argument: stage.  see Stage API, above
 910
 911         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 912         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 913         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 914                               |             |
 915                             r_data        result
 916                               |             |
 917                               +--process ->-+
 918
 919         Attributes:
 920         -----------
 921         p.i_data : StageInput, shaped according to ispec
 922             The pipeline input
 923         p.o_data : StageOutput, shaped according to ospec
 924             The pipeline output
 925         r_data : input_shape according to ispec
 926             A temporary (buffered) copy of a prior (valid) input.
 927             This is HELD if the output is not ready.  It is updated
 928             SYNCHRONOUSLY.
 929         result: output_shape according to ospec
 930             The output of the combinatorial logic.  it is updated
 931             COMBINATORIALLY (no clock dependence).
 932
 933         Truth Table
 934
 935         Inputs  Temp  Output  Data
 936         -------   -   -----   ----
 937         P P N N ~NiR&  N P
 938         i o i o  NoV   o o
 939         V R R V        V R
 940
 941         -------   -    - -
 942         0 0 0 0   0    0 1    reg
 943         0 0 0 1   1    1 0    reg
 944         0 0 1 0   0    0 1    reg
 945         0 0 1 1   0    0 1    reg
 946         -------   -    - -
 947         0 1 0 0   0    0 1    reg
 948         0 1 0 1   1    1 0    reg
 949         0 1 1 0   0    0 1    reg
 950         0 1 1 1   0    0 1    reg
 951         -------   -    - -
 952         1 0 0 0   0    1 1    reg
 953         1 0 0 1   1    1 0    reg
 954         1 0 1 0   0    1 1    reg
 955         1 0 1 1   0    1 1    reg
 956         -------   -    - -
 957         1 1 0 0   0    1 1    process(i_data)
 958         1 1 0 1   1    1 0    process(i_data)
 959         1 1 1 0   0    1 1    process(i_data)
 960         1 1 1 1   0    1 1    process(i_data)
 961         -------   -    - -
 962
 963         Note: PoR is *NOT* involved in the above decision-making.
 964     """
 965
 966     def elaborate(self, platform):
 967         self.m = m = ControlBase._elaborate(self, platform)
 968
 969         data_valid = Signal() # is data valid or not
 970         r_data = self.stage.ospec() # output type
 971
 972         # some temporaries
 973         p_i_valid = Signal(reset_less=True)
 974         pv = Signal(reset_less=True)
 975         buf_full = Signal(reset_less=True)
 976         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
 977         m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
 978         m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
 979
 980         m.d.comb += self.n.o_valid.eq(data_valid)
 981         m.d.comb += self.p._o_ready.eq(~data_valid | self.n.i_ready_test)
 982         m.d.sync += data_valid.eq(p_i_valid | buf_full)
 983
 984         with m.If(pv):
 985             m.d.sync += eq(r_data, self.stage.process(self.p.i_data))
 986         o_data = self._postprocess(r_data)
 987         m.d.comb += eq(self.n.o_data, o_data)
 988
 989         return self.m
 990
 991 class UnbufferedPipeline2(ControlBase):
 992     """ A simple pipeline stage with single-clock synchronisation
 993         and two-way valid/ready synchronised signalling.
 994
 995         Note that a stall in one stage will result in the entire pipeline
 996         chain stalling.
 997
 998         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 999         travel synchronously with the data: the valid/ready signalling
1000         combines in a *combinatorial* fashion.  Therefore, a long pipeline
1001         chain will lengthen propagation delays.
1002
1003         Argument: stage.  see Stage API, above
1004
1005         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
1006         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
1007         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
1008                               |             |    |
1009                               +- process-> buf <-+
1010         Attributes:
1011         -----------
1012         p.i_data : StageInput, shaped according to ispec
1013             The pipeline input
1014         p.o_data : StageOutput, shaped according to ospec
1015             The pipeline output
1016         buf : output_shape according to ospec
1017             A temporary (buffered) copy of a valid output
1018             This is HELD if the output is not ready.  It is updated
1019             SYNCHRONOUSLY.
1020
1021         Inputs  Temp  Output Data
1022         -------   -   -----
1023         P P N N ~NiR&  N P   (buf_full)
1024         i o i o  NoV   o o
1025         V R R V        V R
1026
1027         -------   -    - -
1028         0 0 0 0   0    0 1   process(i_data)
1029         0 0 0 1   1    1 0   reg (odata, unchanged)
1030         0 0 1 0   0    0 1   process(i_data)
1031         0 0 1 1   0    0 1   process(i_data)
1032         -------   -    - -
1033         0 1 0 0   0    0 1   process(i_data)
1034         0 1 0 1   1    1 0   reg (odata, unchanged)
1035         0 1 1 0   0    0 1   process(i_data)
1036         0 1 1 1   0    0 1   process(i_data)
1037         -------   -    - -
1038         1 0 0 0   0    1 1   process(i_data)
1039         1 0 0 1   1    1 0   reg (odata, unchanged)
1040         1 0 1 0   0    1 1   process(i_data)
1041         1 0 1 1   0    1 1   process(i_data)
1042         -------   -    - -
1043         1 1 0 0   0    1 1   process(i_data)
1044         1 1 0 1   1    1 0   reg (odata, unchanged)
1045         1 1 1 0   0    1 1   process(i_data)
1046         1 1 1 1   0    1 1   process(i_data)
1047         -------   -    - -
1048
1049         Note: PoR is *NOT* involved in the above decision-making.
1050     """
1051
1052     def elaborate(self, platform):
1053         self.m = m = ControlBase._elaborate(self, platform)
1054
1055         buf_full = Signal() # is data valid or not
1056         buf = self.stage.ospec() # output type
1057
1058         # some temporaries
1059         p_i_valid = Signal(reset_less=True)
1060         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
1061
1062         m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
1063         m.d.comb += self.p._o_ready.eq(~buf_full)
1064         m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
1065
1066         o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
1067         o_data = self._postprocess(o_data)
1068         m.d.comb += eq(self.n.o_data, o_data)
1069         m.d.sync += eq(buf, self.n.o_data)
1070
1071         return self.m
1072
1073
1074 class PassThroughStage(StageCls):
1075     """ a pass-through stage which has its input data spec equal to its output,
1076         and "passes through" its data from input to output.
1077     """
1078     def __init__(self, iospecfn):
1079         self.iospecfn = iospecfn
1080     def ispec(self): return self.iospecfn()
1081     def ospec(self): return self.iospecfn()
1082     def process(self, i): return i
1083
1084
1085 class PassThroughHandshake(ControlBase):
1086     """ A control block that delays by one clock cycle.
1087
1088         Inputs   Temporary          Output Data
1089         -------  ------------------  ----- ----
1090         P P N N  PiV& PiV| NiR| pvr   N P  (pvr)
1091         i o i o  PoR  ~PoR ~NoV       o o
1092         V R R V                       V R
1093
1094         -------   -    -    -   -     - -
1095         0 0 0 0   0    1    1   0     1 1   odata (unchanged)
1096         0 0 0 1   0    1    0   0     1 0   odata (unchanged)
1097         0 0 1 0   0    1    1   0     1 1   odata (unchanged)
1098         0 0 1 1   0    1    1   0     1 1   odata (unchanged)
1099         -------   -    -    -   -     - -
1100         0 1 0 0   0    0    1   0     0 1   odata (unchanged)
1101         0 1 0 1   0    0    0   0     0 0   odata (unchanged)
1102         0 1 1 0   0    0    1   0     0 1   odata (unchanged)
1103         0 1 1 1   0    0    1   0     0 1   odata (unchanged)
1104         -------   -    -    -   -     - -
1105         1 0 0 0   0    1    1   1     1 1   process(in)
1106         1 0 0 1   0    1    0   0     1 0   odata (unchanged)
1107         1 0 1 0   0    1    1   1     1 1   process(in)
1108         1 0 1 1   0    1    1   1     1 1   process(in)
1109         -------   -    -    -   -     - -
1110         1 1 0 0   1    1    1   1     1 1   process(in)
1111         1 1 0 1   1    1    0   0     1 0   odata (unchanged)
1112         1 1 1 0   1    1    1   1     1 1   process(in)
1113         1 1 1 1   1    1    1   1     1 1   process(in)
1114         -------   -    -    -   -     - -
1115
1116     """
1117
1118     def elaborate(self, platform):
1119         self.m = m = ControlBase._elaborate(self, platform)
1120
1121         r_data = self.stage.ospec() # output type
1122
1123         # temporaries
1124         p_i_valid = Signal(reset_less=True)
1125         pvr = Signal(reset_less=True)
1126         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
1127         m.d.comb += pvr.eq(p_i_valid & self.p.o_ready)
1128
1129         m.d.comb += self.p.o_ready.eq(~self.n.o_valid |  self.n.i_ready_test)
1130         m.d.sync += self.n.o_valid.eq(p_i_valid       | ~self.p.o_ready)
1131
1132         odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
1133         m.d.sync += eq(r_data, odata)
1134         r_data = self._postprocess(r_data)
1135         m.d.comb += eq(self.n.o_data, r_data)
1136
1137         return m
1138
1139
1140 class RegisterPipeline(UnbufferedPipeline):
1141     """ A pipeline stage that delays by one clock cycle, creating a
1142         sync'd latch out of o_data and o_valid as an indirect byproduct
1143         of using PassThroughStage
1144     """
1145     def __init__(self, iospecfn):
1146         UnbufferedPipeline.__init__(self, PassThroughStage(iospecfn))
1147
1148
1149 class FIFOControl(ControlBase):
1150     """ FIFO Control.  Uses SyncFIFO to store data, coincidentally
1151         happens to have same valid/ready signalling as Stage API.
1152
1153         i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
1154     """
1155
1156     def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
1157                                      fwft=True, buffered=False, pipe=False):
1158         """ FIFO Control
1159
1160             * depth: number of entries in the FIFO
1161             * stage: data processing block
1162             * fwft : first word fall-thru mode (non-fwft introduces delay)
1163             * buffered: use buffered FIFO (introduces extra cycle delay)
1164
1165             NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
1166                     (fwft=True, buffered=False)
1167
1168             NOTE 2: i_data *must* have a shape function.  it can therefore
1169                     be a Signal, or a Record, or a RecordObject.
1170
1171             data is processed (and located) as follows:
1172
1173             self.p  self.stage temp    fn temp  fn  temp  fp   self.n
1174             i_data->process()->result->cat->din.FIFO.dout->cat(o_data)
1175
1176             yes, really: cat produces a Cat() which can be assigned to.
1177             this is how the FIFO gets de-catted without needing a de-cat
1178             function
1179         """
1180
1181         assert not (fwft and buffered), "buffered cannot do fwft"
1182         if buffered:
1183             depth += 1
1184         self.fwft = fwft
1185         self.buffered = buffered
1186         self.pipe = pipe
1187         self.fdepth = depth
1188         ControlBase.__init__(self, stage, in_multi, stage_ctl)
1189
1190     def elaborate(self, platform):
1191         self.m = m = ControlBase._elaborate(self, platform)
1192
1193         # make a FIFO with a signal of equal width to the o_data.
1194         (fwidth, _) = shape(self.n.o_data)
1195         if self.buffered:
1196             fifo = SyncFIFOBuffered(fwidth, self.fdepth)
1197         else:
1198             fifo = Queue(fwidth, self.fdepth, fwft=self.fwft, pipe=self.pipe)
1199         m.submodules.fifo = fifo
1200
1201         # store result of processing in combinatorial temporary
1202         result = self.stage.ospec()
1203         m.d.comb += eq(result, self.stage.process(self.p.i_data))
1204
1205         # connect previous rdy/valid/data - do cat on i_data
1206         # NOTE: cannot do the PrevControl-looking trick because
1207         # of need to process the data.  shaaaame....
1208         m.d.comb += [fifo.we.eq(self.p.i_valid_test),
1209                      self.p.o_ready.eq(fifo.writable),
1210                      eq(fifo.din, cat(result)),
1211                    ]
1212
1213         # connect next rdy/valid/data - do cat on o_data
1214         connections = [self.n.o_valid.eq(fifo.readable),
1215                      fifo.re.eq(self.n.i_ready_test),
1216                    ]
1217         if self.fwft or self.buffered:
1218             m.d.comb += connections
1219         else:
1220             m.d.sync += connections # unbuffered fwft mode needs sync
1221         o_data = cat(self.n.o_data).eq(fifo.dout)
1222         o_data = self._postprocess(o_data)
1223         m.d.comb += o_data
1224
1225         return m
1226
1227
1228 # aka "RegStage".
1229 class UnbufferedPipeline(FIFOControl):
1230     def __init__(self, stage, in_multi=None, stage_ctl=False):
1231         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
1232                                    fwft=True, pipe=False)
1233
1234 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
1235 class PassThroughHandshake(FIFOControl):
1236     def __init__(self, stage, in_multi=None, stage_ctl=False):
1237         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
1238                                    fwft=True, pipe=True)
1239
1240 # this is *probably* BufferedHandshake, although test #997 now succeeds.
1241 class BufferedHandshake(FIFOControl):
1242     def __init__(self, stage, in_multi=None, stage_ctl=False):
1243         FIFOControl.__init__(self, 2, stage, in_multi, stage_ctl,
1244                                    fwft=True, pipe=False)
1245
1246
1247 # this is *probably* SimpleHandshake (note: memory cell size=0)
1248 class SimpleHandshake(FIFOControl):
1249     def __init__(self, stage, in_multi=None, stage_ctl=False):
1250         FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
1251                                    fwft=True, pipe=False)