1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedHandshake). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedHandshake by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A Control class that introduces a single clock delay, passing its
102 data through unaltered. Unlike RegisterPipeline (which relies
103 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
109 A convenience class that, because UnbufferedPipeline introduces a single
110 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
111 stage that, duh, delays its (unmodified) input by one clock cycle.
116 nmigen implementation of buffered pipeline stage, based on zipcpu:
117 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
119 this module requires quite a bit of thought to understand how it works
120 (and why it is needed in the first place). reading the above is
121 *strongly* recommended.
123 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
124 the STB / ACK signals to raise and lower (on separate clocks) before
125 data may proceeed (thus only allowing one piece of data to proceed
126 on *ALTERNATE* cycles), the signalling here is a true pipeline
127 where data will flow on *every* clock when the conditions are right.
129 input acceptance conditions are when:
130 * incoming previous-stage strobe (p.i_valid) is HIGH
131 * outgoing previous-stage ready (p.o_ready) is LOW
133 output transmission conditions are when:
134 * outgoing next-stage strobe (n.o_valid) is HIGH
135 * outgoing next-stage ready (n.i_ready) is LOW
137 the tricky bit is when the input has valid data and the output is not
138 ready to accept it. if it wasn't for the clock synchronisation, it
139 would be possible to tell the input "hey don't send that data, we're
140 not ready". unfortunately, it's not possible to "change the past":
141 the previous stage *has no choice* but to pass on its data.
143 therefore, the incoming data *must* be accepted - and stored: that
144 is the responsibility / contract that this stage *must* accept.
145 on the same clock, it's possible to tell the input that it must
146 not send any more data. this is the "stall" condition.
148 we now effectively have *two* possible pieces of data to "choose" from:
149 the buffered data, and the incoming data. the decision as to which
150 to process and output is based on whether we are in "stall" or not.
151 i.e. when the next stage is no longer ready, the output comes from
152 the buffer if a stall had previously occurred, otherwise it comes
153 direct from processing the input.
155 this allows us to respect a synchronous "travelling STB" with what
156 dan calls a "buffered handshake".
158 it's quite a complex state machine!
163 Synchronised pipeline, Based on:
164 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
167 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
168 from nmigen
.cli
import verilog
, rtlil
169 from nmigen
.lib
.fifo
import SyncFIFO
170 from nmigen
.hdl
.ast
import ArrayProxy
171 from nmigen
.hdl
.rec
import Record
, Layout
173 from abc
import ABCMeta
, abstractmethod
174 from collections
.abc
import Sequence
178 """ contains signals that come *from* the previous stage (both in and out)
179 * i_valid: previous stage indicating all incoming data is valid.
180 may be a multi-bit signal, where all bits are required
181 to be asserted to indicate "valid".
182 * o_ready: output to next stage indicating readiness to accept data
183 * i_data : an input - added by the user of this class
186 def __init__(self
, i_width
=1, stage_ctl
=False):
187 self
.stage_ctl
= stage_ctl
188 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
189 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
190 self
.i_data
= None # XXX MUST BE ADDED BY USER
192 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
196 """ public-facing API: indicates (externally) that stage is ready
199 return self
.s_o_ready
# set dynamically by stage
200 return self
._o
_ready
# return this when not under dynamic control
202 def _connect_in(self
, prev
, direct
=False):
203 """ internal helper function to connect stage to an input source.
204 do not use to connect stage-to-stage!
207 i_valid
= prev
.i_valid
209 i_valid
= prev
.i_valid_test
210 return [self
.i_valid
.eq(i_valid
),
211 prev
.o_ready
.eq(self
.o_ready
),
212 eq(self
.i_data
, prev
.i_data
),
216 def i_valid_test(self
):
217 vlen
= len(self
.i_valid
)
219 # multi-bit case: valid only when i_valid is all 1s
220 all1s
= Const(-1, (len(self
.i_valid
), False))
221 i_valid
= (self
.i_valid
== all1s
)
223 # single-bit i_valid case
224 i_valid
= self
.i_valid
226 # when stage indicates not ready, incoming data
227 # must "appear" to be not ready too
229 i_valid
= i_valid
& self
.s_o_ready
235 """ contains the signals that go *to* the next stage (both in and out)
236 * o_valid: output indicating to next stage that data is valid
237 * i_ready: input from next stage indicating that it can accept data
238 * o_data : an output - added by the user of this class
240 def __init__(self
, stage_ctl
=False):
241 self
.stage_ctl
= stage_ctl
242 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
243 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
244 self
.o_data
= None # XXX MUST BE ADDED BY USER
246 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
249 def i_ready_test(self
):
251 return self
.i_ready
& self
.d_valid
254 def connect_to_next(self
, nxt
):
255 """ helper function to connect to the next stage data/valid/ready.
256 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
257 use this when connecting stage-to-stage
259 return [nxt
.i_valid
.eq(self
.o_valid
),
260 self
.i_ready
.eq(nxt
.o_ready
),
261 eq(nxt
.i_data
, self
.o_data
),
264 def _connect_out(self
, nxt
, direct
=False):
265 """ internal helper function to connect stage to an output source.
266 do not use to connect stage-to-stage!
269 i_ready
= nxt
.i_ready
271 i_ready
= nxt
.i_ready_test
272 return [nxt
.o_valid
.eq(self
.o_valid
),
273 self
.i_ready
.eq(i_ready
),
274 eq(nxt
.o_data
, self
.o_data
),
279 """ makes signals equal: a helper routine which identifies if it is being
280 passed a list (or tuple) of objects, or signals, or Records, and calls
281 the objects' eq function.
283 complex objects (classes) can be used: they must follow the
284 convention of having an eq member function, which takes the
285 responsibility of further calling eq and returning a list of
288 Record is a special (unusual, recursive) case, where the input may be
289 specified as a dictionary (which may contain further dictionaries,
290 recursively), where the field names of the dictionary must match
291 the Record's field spec. Alternatively, an object with the same
292 member names as the Record may be assigned: it does not have to
295 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
296 has an eq function, the object being assigned to it (e.g. a python
297 object) might not. despite the *input* having an eq function,
298 that doesn't help us, because it's the *ArrayProxy* that's being
299 assigned to. so.... we cheat. use the ports() function of the
300 python object, enumerate them, find out the list of Signals that way,
304 if isinstance(o
, dict):
305 for (k
, v
) in o
.items():
306 print ("d-eq", v
, i
[k
])
307 res
.append(v
.eq(i
[k
]))
310 if not isinstance(o
, Sequence
):
312 for (ao
, ai
) in zip(o
, i
):
313 #print ("eq", ao, ai)
314 if isinstance(ao
, Record
):
316 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
317 if isinstance(field_shape
, Layout
):
321 if hasattr(val
, field_name
): # check for attribute
322 val
= getattr(val
, field_name
)
324 val
= val
[field_name
] # dictionary-style specification
325 rres
+= eq(ao
.fields
[field_name
], val
)
326 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
329 op
= getattr(ao
, p
.name
)
330 #print (op, p, p.name)
331 rres
.append(op
.eq(p
))
334 if not isinstance(rres
, Sequence
):
340 class StageCls(metaclass
=ABCMeta
):
341 """ Class-based "Stage" API. requires instantiation (after derivation)
343 see "Stage API" above.. Note: python does *not* require derivation
344 from this class. All that is required is that the pipelines *have*
345 the functions listed in this class. Derivation from this class
346 is therefore merely a "courtesy" to maintainers.
349 def ispec(self
): pass # REQUIRED
351 def ospec(self
): pass # REQUIRED
353 #def setup(self, m, i): pass # OPTIONAL
355 def process(self
, i
): pass # REQUIRED
358 class Stage(metaclass
=ABCMeta
):
359 """ Static "Stage" API. does not require instantiation (after derivation)
361 see "Stage API" above. Note: python does *not* require derivation
362 from this class. All that is required is that the pipelines *have*
363 the functions listed in this class. Derivation from this class
364 is therefore merely a "courtesy" to maintainers.
376 #def setup(m, i): pass
383 class RecordBasedStage(Stage
):
384 """ convenience class which provides a Records-based layout.
385 honestly it's a lot easier just to create a direct Records-based
386 class (see ExampleAddRecordStage)
388 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
389 self
.in_shape
= in_shape
390 self
.out_shape
= out_shape
391 self
.__process
= processfn
392 self
.__setup
= setupfn
393 def ispec(self
): return Record(self
.in_shape
)
394 def ospec(self
): return Record(self
.out_shape
)
395 def process(seif
, i
): return self
.__process
(i
)
396 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
399 class StageChain(StageCls
):
400 """ pass in a list of stages, and they will automatically be
401 chained together via their input and output specs into a
404 the end result basically conforms to the exact same Stage API.
406 * input to this class will be the input of the first stage
407 * output of first stage goes into input of second
408 * output of second goes into input into third (etc. etc.)
409 * the output of this class will be the output of the last stage
411 def __init__(self
, chain
, specallocate
=False):
413 self
.specallocate
= specallocate
416 return self
.chain
[0].ispec()
419 return self
.chain
[-1].ospec()
421 def _specallocate_setup(self
, m
, i
):
422 for (idx
, c
) in enumerate(self
.chain
):
423 if hasattr(c
, "setup"):
424 c
.setup(m
, i
) # stage may have some module stuff
425 o
= self
.chain
[idx
].ospec() # last assignment survives
426 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
427 if idx
== len(self
.chain
)-1:
429 i
= self
.chain
[idx
+1].ispec() # new input on next loop
430 m
.d
.comb
+= eq(i
, o
) # assign to next input
431 return o
# last loop is the output
433 def _noallocate_setup(self
, m
, i
):
434 for (idx
, c
) in enumerate(self
.chain
):
435 if hasattr(c
, "setup"):
436 c
.setup(m
, i
) # stage may have some module stuff
437 i
= o
= c
.process(i
) # store input into "o"
438 return o
# last loop is the output
440 def setup(self
, m
, i
):
441 if self
.specallocate
:
442 self
.o
= self
._specallocate
_setup
(m
, i
)
444 self
.o
= self
._noallocate
_setup
(m
, i
)
446 def process(self
, i
):
447 return self
.o
# conform to Stage API: return last-loop output
451 """ Common functions for Pipeline API
453 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
454 """ Base class containing ready/valid/data to previous and next stages
456 * p: contains ready/valid to the previous stage
457 * n: contains ready/valid to the next stage
459 Except when calling Controlbase.connect(), user must also:
460 * add i_data member to PrevControl (p) and
461 * add o_data member to NextControl (n)
465 # set up input and output IO ACK (prev/next ready/valid)
466 self
.p
= PrevControl(in_multi
, stage_ctl
)
467 self
.n
= NextControl(stage_ctl
)
469 # set up the input and output data
470 if stage
is not None:
471 self
.p
.i_data
= stage
.ispec() # input type
472 self
.n
.o_data
= stage
.ospec()
474 def connect_to_next(self
, nxt
):
475 """ helper function to connect to the next stage data/valid/ready.
477 return self
.n
.connect_to_next(nxt
.p
)
479 def _connect_in(self
, prev
):
480 """ internal helper function to connect stage to an input source.
481 do not use to connect stage-to-stage!
483 return self
.p
._connect
_in
(prev
.p
)
485 def _connect_out(self
, nxt
):
486 """ internal helper function to connect stage to an output source.
487 do not use to connect stage-to-stage!
489 return self
.n
._connect
_out
(nxt
.n
)
491 def connect(self
, pipechain
):
492 """ connects a chain (list) of Pipeline instances together and
493 links them to this ControlBase instance:
495 in <----> self <---> out
498 [pipe1, pipe2, pipe3, pipe4]
501 out---in out--in out---in
503 Also takes care of allocating i_data/o_data, by looking up
504 the data spec for each end of the pipechain. i.e It is NOT
505 necessary to allocate self.p.i_data or self.n.o_data manually:
506 this is handled AUTOMATICALLY, here.
508 Basically this function is the direct equivalent of StageChain,
509 except that unlike StageChain, the Pipeline logic is followed.
511 Just as StageChain presents an object that conforms to the
512 Stage API from a list of objects that also conform to the
513 Stage API, an object that calls this Pipeline connect function
514 has the exact same pipeline API as the list of pipline objects
517 Thus it becomes possible to build up larger chains recursively.
518 More complex chains (multi-input, multi-output) will have to be
521 eqs
= [] # collated list of assignment statements
523 # connect inter-chain
524 for i
in range(len(pipechain
)-1):
526 pipe2
= pipechain
[i
+1]
527 eqs
+= pipe1
.connect_to_next(pipe2
)
529 # connect front of chain to ourselves
531 self
.p
.i_data
= front
.stage
.ispec()
532 eqs
+= front
._connect
_in
(self
)
534 # connect end of chain to ourselves
536 self
.n
.o_data
= end
.stage
.ospec()
537 eqs
+= end
._connect
_out
(self
)
541 def set_input(self
, i
):
542 """ helper function to set the input data
544 return eq(self
.p
.i_data
, i
)
547 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
548 self
.n
.o_valid
, self
.p
.o_ready
,
550 if hasattr(self
.p
.i_data
, "ports"):
551 res
+= self
.p
.i_data
.ports()
554 if hasattr(self
.n
.o_data
, "ports"):
555 res
+= self
.n
.o_data
.ports()
560 def _elaborate(self
, platform
):
561 """ handles case where stage has dynamic ready/valid functions
565 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
566 self
.stage
.setup(m
, self
.p
.i_data
)
568 if not self
.p
.stage_ctl
:
571 # intercept the previous (outgoing) "ready", combine with stage ready
572 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
574 # intercept the next (incoming) "ready" and combine it with data valid
575 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
576 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
581 class BufferedHandshake(ControlBase
):
582 """ buffered pipeline stage. data and strobe signals travel in sync.
583 if ever the input is ready and the output is not, processed data
584 is shunted in a temporary register.
586 Argument: stage. see Stage API above
588 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
589 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
590 stage-1 p.i_data >>in stage n.o_data out>> stage+1
596 input data p.i_data is read (only), is processed and goes into an
597 intermediate result store [process()]. this is updated combinatorially.
599 in a non-stall condition, the intermediate result will go into the
600 output (update_output). however if ever there is a stall, it goes
601 into r_data instead [update_buffer()].
603 when the non-stall condition is released, r_data is the first
604 to be transferred to the output [flush_buffer()], and the stall
607 on the next cycle (as long as stall is not raised again) the
608 input may begin to be processed and transferred directly to output.
611 def elaborate(self
, platform
):
612 self
.m
= ControlBase
._elaborate
(self
, platform
)
614 result
= self
.stage
.ospec()
615 r_data
= self
.stage
.ospec()
617 # establish some combinatorial temporaries
618 o_n_validn
= Signal(reset_less
=True)
619 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
620 nir_por
= Signal(reset_less
=True)
621 nir_por_n
= Signal(reset_less
=True)
622 p_i_valid
= Signal(reset_less
=True)
623 nir_novn
= Signal(reset_less
=True)
624 nirn_novn
= Signal(reset_less
=True)
625 por_pivn
= Signal(reset_less
=True)
626 npnn
= Signal(reset_less
=True)
627 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
628 o_n_validn
.eq(~self
.n
.o_valid
),
629 n_i_ready
.eq(self
.n
.i_ready_test
),
630 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
631 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
632 nir_novn
.eq(n_i_ready | o_n_validn
),
633 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
634 npnn
.eq(nir_por | nirn_novn
),
635 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
638 # store result of processing in combinatorial temporary
639 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
641 # if not in stall condition, update the temporary register
642 with self
.m
.If(self
.p
.o_ready
): # not stalled
643 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
645 # data pass-through conditions
646 with self
.m
.If(npnn
):
647 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
648 eq(self
.n
.o_data
, result
), # update output
650 # buffer flush conditions (NOTE: can override data passthru conditions)
651 with self
.m
.If(nir_por_n
): # not stalled
652 # Flush the [already processed] buffer to the output port.
653 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
654 eq(self
.n
.o_data
, r_data
), # flush buffer
656 # output ready conditions
657 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
662 class SimpleHandshake(ControlBase
):
663 """ simple handshake control. data and strobe signals travel in sync.
664 implements the protocol used by Wishbone and AXI4.
666 Argument: stage. see Stage API above
668 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
669 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
670 stage-1 p.i_data >>in stage n.o_data out>> stage+1
675 Inputs Temporary Output
676 ------- ---------- -----
677 P P N N PiV& ~NiV& N P
704 def elaborate(self
, platform
):
705 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
708 result
= self
.stage
.ospec()
710 # establish some combinatorial temporaries
711 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
712 p_i_valid_p_o_ready
= Signal(reset_less
=True)
713 p_i_valid
= Signal(reset_less
=True)
714 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
715 n_i_ready
.eq(self
.n
.i_ready_test
),
716 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
719 # store result of processing in combinatorial temporary
720 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
722 # previous valid and ready
723 with m
.If(p_i_valid_p_o_ready
):
724 m
.d
.sync
+= [r_busy
.eq(1), # output valid
725 eq(self
.n
.o_data
, result
), # update output
727 # previous invalid or not ready, however next is accepting
728 with m
.Elif(n_i_ready
):
729 m
.d
.sync
+= [eq(self
.n
.o_data
, result
)]
730 # TODO: could still send data here (if there was any)
731 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
732 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
734 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
735 # if next is ready, so is previous
736 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
741 class UnbufferedPipeline(ControlBase
):
742 """ A simple pipeline stage with single-clock synchronisation
743 and two-way valid/ready synchronised signalling.
745 Note that a stall in one stage will result in the entire pipeline
748 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
749 travel synchronously with the data: the valid/ready signalling
750 combines in a *combinatorial* fashion. Therefore, a long pipeline
751 chain will lengthen propagation delays.
753 Argument: stage. see Stage API, above
755 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
756 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
757 stage-1 p.i_data >>in stage n.o_data out>> stage+1
765 p.i_data : StageInput, shaped according to ispec
767 p.o_data : StageOutput, shaped according to ospec
769 r_data : input_shape according to ispec
770 A temporary (buffered) copy of a prior (valid) input.
771 This is HELD if the output is not ready. It is updated
773 result: output_shape according to ospec
774 The output of the combinatorial logic. it is updated
775 COMBINATORIALLY (no clock dependence).
807 Note: PoR is *NOT* involved in the above decision-making.
810 def elaborate(self
, platform
):
811 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
813 data_valid
= Signal() # is data valid or not
814 r_data
= self
.stage
.ospec() # output type
817 p_i_valid
= Signal(reset_less
=True)
818 pv
= Signal(reset_less
=True)
819 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
820 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
822 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
823 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
824 m
.d
.sync
+= data_valid
.eq(p_i_valid | \
825 (~self
.n
.i_ready_test
& data_valid
))
827 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
828 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
833 class UnbufferedPipeline2(ControlBase
):
834 """ A simple pipeline stage with single-clock synchronisation
835 and two-way valid/ready synchronised signalling.
837 Note that a stall in one stage will result in the entire pipeline
840 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
841 travel synchronously with the data: the valid/ready signalling
842 combines in a *combinatorial* fashion. Therefore, a long pipeline
843 chain will lengthen propagation delays.
845 Argument: stage. see Stage API, above
847 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
848 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
849 stage-1 p.i_data >>in stage n.o_data out>> stage+1
854 p.i_data : StageInput, shaped according to ispec
856 p.o_data : StageOutput, shaped according to ospec
858 buf : output_shape according to ospec
859 A temporary (buffered) copy of a valid output
860 This is HELD if the output is not ready. It is updated
864 def elaborate(self
, platform
):
865 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
867 buf_full
= Signal() # is data valid or not
868 buf
= self
.stage
.ospec() # output type
871 p_i_valid
= Signal(reset_less
=True)
872 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
874 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
875 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
876 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
878 odata
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
879 m
.d
.comb
+= eq(self
.n
.o_data
, odata
)
880 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
885 class PassThroughStage(StageCls
):
886 """ a pass-through stage which has its input data spec equal to its output,
887 and "passes through" its data from input to output.
889 def __init__(self
, iospecfn
):
890 self
.iospecfn
= iospecfn
891 def ispec(self
): return self
.iospecfn()
892 def ospec(self
): return self
.iospecfn()
893 def process(self
, i
): return i
896 class PassThroughHandshake(ControlBase
):
897 """ A control block that delays by one clock cycle.
900 def elaborate(self
, platform
):
901 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
904 p_i_valid
= Signal(reset_less
=True)
905 pvr
= Signal(reset_less
=True)
906 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
907 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
909 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
910 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
912 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), self
.n
.o_data
)
913 m
.d
.sync
+= eq(self
.n
.o_data
, odata
)
918 class RegisterPipeline(UnbufferedPipeline
):
919 """ A pipeline stage that delays by one clock cycle, creating a
920 sync'd latch out of o_data and o_valid as an indirect byproduct
921 of using PassThroughStage
923 def __init__(self
, iospecfn
):
924 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
927 class FIFOtest(ControlBase
):
928 """ A test of using a SyncFIFO to see if it will work.
929 Note: the only things it will accept is a Signal of width "width".
932 def __init__(self
, width
, depth
):
937 return Signal(width
, name
="data")
938 stage
= PassThroughStage(iospecfn
)
939 ControlBase
.__init
__(self
, stage
=stage
)
941 def elaborate(self
, platform
):
942 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
944 fifo
= SyncFIFO(self
.fwidth
, self
.fdepth
)
945 m
.submodules
.fifo
= fifo
947 # prev: make the FIFO "look" like a PrevControl...
950 fp
._o
_ready
= fifo
.writable
952 # ... so we can do this!
953 m
.d
.comb
+= fp
._connect
_in
(self
.p
, True)
955 # next: make the FIFO "look" like a NextControl...
957 fn
.o_valid
= fifo
.readable
959 fn
.o_data
= fifo
.dout
960 # ... so we can do this!
961 m
.d
.comb
+= fn
._connect
_out
(self
.n
)
963 # err... that should be all!