src/add/singlepipe.py

   1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
   2     For multi-input and multi-output variants, see multipipe.
   3
   4     Associated development bugs:
   5     * http://bugs.libre-riscv.org/show_bug.cgi?id=64
   6     * http://bugs.libre-riscv.org/show_bug.cgi?id=57
   7
   8     eq:
   9     --
  10
  11     a strategically very important function that is identical in function
  12     to nmigen's Signal.eq function, except it may take objects, or a list
  13     of objects, or a tuple of objects, and where objects may also be
  14     Records.
  15
  16     Stage API:
  17     ---------
  18
  19     stage requires compliance with a strict API that may be
  20     implemented in several means, including as a static class.
  21     the methods of a stage instance must be as follows:
  22
  23     * ispec() - Input data format specification
  24                 returns an object or a list or tuple of objects, or
  25                 a Record, each object having an "eq" function which
  26                 takes responsibility for copying by assignment all
  27                 sub-objects
  28     * ospec() - Output data format specification
  29                 requirements as for ospec
  30     * process(m, i) - Processes an ispec-formatted object
  31                 returns a combinatorial block of a result that
  32                 may be assigned to the output, by way of the "eq"
  33                 function
  34     * setup(m, i) - Optional function for setting up submodules
  35                 may be used for more complex stages, to link
  36                 the input (i) to submodules.  must take responsibility
  37                 for adding those submodules to the module (m).
  38                 the submodules must be combinatorial blocks and
  39                 must have their inputs and output linked combinatorially.
  40
  41     Both StageCls (for use with non-static classes) and Stage (for use
  42     by static classes) are abstract classes from which, for convenience
  43     and as a courtesy to other developers, anything conforming to the
  44     Stage API may *choose* to derive.
  45
  46     StageChain:
  47     ----------
  48
  49     A useful combinatorial wrapper around stages that chains them together
  50     and then presents a Stage-API-conformant interface.  By presenting
  51     the same API as the stages it wraps, it can clearly be used recursively.
  52
  53     RecordBasedStage:
  54     ----------------
  55
  56     A convenience class that takes an input shape, output shape, a
  57     "processing" function and an optional "setup" function.  Honestly
  58     though, there's not much more effort to just... create a class
  59     that returns a couple of Records (see ExampleAddRecordStage in
  60     examples).
  61
  62     PassThroughStage:
  63     ----------------
  64
  65     A convenience class that takes a single function as a parameter,
  66     that is chain-called to create the exact same input and output spec.
  67     It has a process() function that simply returns its input.
  68
  69     Instances of this class are completely redundant if handed to
  70     StageChain, however when passed to UnbufferedPipeline they
  71     can be used to introduce a single clock delay.
  72
  73     ControlBase:
  74     -----------
  75
  76     The base class for pipelines.  Contains previous and next ready/valid/data.
  77     Also has an extremely useful "connect" function that can be used to
  78     connect a chain of pipelines and present the exact same prev/next
  79     ready/valid/data API.
  80
  81     UnbufferedPipeline:
  82     ------------------
  83
  84     A simple stalling clock-synchronised pipeline that has no buffering
  85     (unlike BufferedHandshake).  Data flows on *every* clock cycle when
  86     the conditions are right (this is nominally when the input is valid
  87     and the output is ready).
  88
  89     A stall anywhere along the line will result in a stall back-propagating
  90     down the entire chain.  The BufferedHandshake by contrast will buffer
  91     incoming data, allowing previous stages one clock cycle's grace before
  92     also having to stall.
  93
  94     An advantage of the UnbufferedPipeline over the Buffered one is
  95     that the amount of logic needed (number of gates) is greatly
  96     reduced (no second set of buffers basically)
  97
  98     The disadvantage of the UnbufferedPipeline is that the valid/ready
  99     logic, if chained together, is *combinatorial*, resulting in
 100     progressively larger gate delay.
 101
 102     PassThroughHandshake:
 103     ------------------
 104
 105     A Control class that introduces a single clock delay, passing its
 106     data through unaltered.  Unlike RegisterPipeline (which relies
 107     on UnbufferedPipeline and PassThroughStage) it handles ready/valid
 108     itself.
 109
 110     RegisterPipeline:
 111     ----------------
 112
 113     A convenience class that, because UnbufferedPipeline introduces a single
 114     clock delay, when its stage is a PassThroughStage, it results in a Pipeline
 115     stage that, duh, delays its (unmodified) input by one clock cycle.
 116
 117     BufferedHandshake:
 118     ----------------
 119
 120     nmigen implementation of buffered pipeline stage, based on zipcpu:
 121     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
 122
 123     this module requires quite a bit of thought to understand how it works
 124     (and why it is needed in the first place).  reading the above is
 125     *strongly* recommended.
 126
 127     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
 128     the STB / ACK signals to raise and lower (on separate clocks) before
 129     data may proceeed (thus only allowing one piece of data to proceed
 130     on *ALTERNATE* cycles), the signalling here is a true pipeline
 131     where data will flow on *every* clock when the conditions are right.
 132
 133     input acceptance conditions are when:
 134         * incoming previous-stage strobe (p.i_valid) is HIGH
 135         * outgoing previous-stage ready   (p.o_ready) is LOW
 136
 137     output transmission conditions are when:
 138         * outgoing next-stage strobe (n.o_valid) is HIGH
 139         * outgoing next-stage ready   (n.i_ready) is LOW
 140
 141     the tricky bit is when the input has valid data and the output is not
 142     ready to accept it.  if it wasn't for the clock synchronisation, it
 143     would be possible to tell the input "hey don't send that data, we're
 144     not ready".  unfortunately, it's not possible to "change the past":
 145     the previous stage *has no choice* but to pass on its data.
 146
 147     therefore, the incoming data *must* be accepted - and stored: that
 148     is the responsibility / contract that this stage *must* accept.
 149     on the same clock, it's possible to tell the input that it must
 150     not send any more data.  this is the "stall" condition.
 151
 152     we now effectively have *two* possible pieces of data to "choose" from:
 153     the buffered data, and the incoming data.  the decision as to which
 154     to process and output is based on whether we are in "stall" or not.
 155     i.e. when the next stage is no longer ready, the output comes from
 156     the buffer if a stall had previously occurred, otherwise it comes
 157     direct from processing the input.
 158
 159     this allows us to respect a synchronous "travelling STB" with what
 160     dan calls a "buffered handshake".
 161
 162     it's quite a complex state machine!
 163
 164     SimpleHandshake
 165     ---------------
 166
 167     Synchronised pipeline, Based on:
 168     https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
 169 """
 170
 171 from nmigen import Signal, Cat, Const, Mux, Module, Value
 172 from nmigen.cli import verilog, rtlil
 173 from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
 174 from nmigen.hdl.ast import ArrayProxy
 175 from nmigen.hdl.rec import Record, Layout
 176
 177 from abc import ABCMeta, abstractmethod
 178 from collections.abc import Sequence
 179 from queue import Queue
 180
 181
 182 class RecordObject(Record):
 183     def __init__(self, layout=None, name=None):
 184         Record.__init__(self, layout=layout or [], name=None)
 185
 186     def __setattr__(self, k, v):
 187         if k in dir(Record) or "fields" not in self.__dict__:
 188             return object.__setattr__(self, k, v)
 189         self.fields[k] = v
 190         if isinstance(v, Record):
 191             newlayout = {k: (k, v.layout)}
 192         else:
 193             newlayout = {k: (k, v.shape())}
 194         self.layout.fields.update(newlayout)
 195
 196     def __iter__(self):
 197         for x in self.fields.values():
 198             yield x
 199
 200
 201 class PrevControl:
 202     """ contains signals that come *from* the previous stage (both in and out)
 203         * i_valid: previous stage indicating all incoming data is valid.
 204                    may be a multi-bit signal, where all bits are required
 205                    to be asserted to indicate "valid".
 206         * o_ready: output to next stage indicating readiness to accept data
 207         * i_data : an input - added by the user of this class
 208     """
 209
 210     def __init__(self, i_width=1, stage_ctl=False):
 211         self.stage_ctl = stage_ctl
 212         self.i_valid = Signal(i_width, name="p_i_valid") # prev   >>in  self
 213         self._o_ready = Signal(name="p_o_ready") # prev   <<out self
 214         self.i_data = None # XXX MUST BE ADDED BY USER
 215         if stage_ctl:
 216             self.s_o_ready = Signal(name="p_s_o_rdy") # prev   <<out self
 217         self.trigger = Signal(reset_less=True)
 218
 219     @property
 220     def o_ready(self):
 221         """ public-facing API: indicates (externally) that stage is ready
 222         """
 223         if self.stage_ctl:
 224             return self.s_o_ready # set dynamically by stage
 225         return self._o_ready      # return this when not under dynamic control
 226
 227     def _connect_in(self, prev, direct=False, fn=None):
 228         """ internal helper function to connect stage to an input source.
 229             do not use to connect stage-to-stage!
 230         """
 231         i_valid = prev.i_valid if direct else prev.i_valid_test
 232         i_data = fn(prev.i_data) if fn is not None else prev.i_data
 233         return [self.i_valid.eq(i_valid),
 234                 prev.o_ready.eq(self.o_ready),
 235                 eq(self.i_data, i_data),
 236                ]
 237
 238     @property
 239     def i_valid_test(self):
 240         vlen = len(self.i_valid)
 241         if vlen > 1:
 242             # multi-bit case: valid only when i_valid is all 1s
 243             all1s = Const(-1, (len(self.i_valid), False))
 244             i_valid = (self.i_valid == all1s)
 245         else:
 246             # single-bit i_valid case
 247             i_valid = self.i_valid
 248
 249         # when stage indicates not ready, incoming data
 250         # must "appear" to be not ready too
 251         if self.stage_ctl:
 252             i_valid = i_valid & self.s_o_ready
 253
 254         return i_valid
 255
 256     def elaborate(self, platform):
 257         m = Module()
 258         m.d.comb += self.trigger.eq(self.i_valid_test & self.o_ready)
 259         return m
 260
 261     def eq(self, i):
 262         return [self.i_data.eq(i.i_data),
 263                 self.o_ready.eq(i.o_ready),
 264                 self.i_valid.eq(i.i_valid)]
 265
 266     def __iter__(self):
 267         yield self.i_valid
 268         yield self.o_ready
 269         if hasattr(self.i_data, "ports"):
 270             yield from self.i_data.ports()
 271         elif isinstance(self.i_data, Sequence):
 272             yield from self.i_data
 273         else:
 274             yield self.i_data
 275
 276     def ports(self):
 277         return list(self)
 278
 279
 280 class NextControl:
 281     """ contains the signals that go *to* the next stage (both in and out)
 282         * o_valid: output indicating to next stage that data is valid
 283         * i_ready: input from next stage indicating that it can accept data
 284         * o_data : an output - added by the user of this class
 285     """
 286     def __init__(self, stage_ctl=False):
 287         self.stage_ctl = stage_ctl
 288         self.o_valid = Signal(name="n_o_valid") # self out>>  next
 289         self.i_ready = Signal(name="n_i_ready") # self <<in   next
 290         self.o_data = None # XXX MUST BE ADDED BY USER
 291         #if self.stage_ctl:
 292         self.d_valid = Signal(reset=1) # INTERNAL (data valid)
 293         self.trigger = Signal(reset_less=True)
 294
 295     @property
 296     def i_ready_test(self):
 297         if self.stage_ctl:
 298             return self.i_ready & self.d_valid
 299         return self.i_ready
 300
 301     def connect_to_next(self, nxt):
 302         """ helper function to connect to the next stage data/valid/ready.
 303             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
 304             use this when connecting stage-to-stage
 305         """
 306         return [nxt.i_valid.eq(self.o_valid),
 307                 self.i_ready.eq(nxt.o_ready),
 308                 eq(nxt.i_data, self.o_data),
 309                ]
 310
 311     def _connect_out(self, nxt, direct=False, fn=None):
 312         """ internal helper function to connect stage to an output source.
 313             do not use to connect stage-to-stage!
 314         """
 315         i_ready = nxt.i_ready if direct else nxt.i_ready_test
 316         o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
 317         return [nxt.o_valid.eq(self.o_valid),
 318                 self.i_ready.eq(i_ready),
 319                 eq(o_data, self.o_data),
 320                ]
 321
 322     def elaborate(self, platform):
 323         m = Module()
 324         m.d.comb += self.trigger.eq(self.i_ready_test & self.o_valid)
 325         return m
 326
 327     def __iter__(self):
 328         yield self.i_ready
 329         yield self.o_valid
 330         if hasattr(self.o_data, "ports"):
 331             yield from self.o_data.ports()
 332         elif isinstance(self.o_data, Sequence):
 333             yield from self.o_data
 334         else:
 335             yield self.o_data
 336
 337     def ports(self):
 338         return list(self)
 339
 340
 341 class Visitor2:
 342     """ a helper class for iterating twin-argument compound data structures.
 343
 344         Record is a special (unusual, recursive) case, where the input may be
 345         specified as a dictionary (which may contain further dictionaries,
 346         recursively), where the field names of the dictionary must match
 347         the Record's field spec.  Alternatively, an object with the same
 348         member names as the Record may be assigned: it does not have to
 349         *be* a Record.
 350
 351         ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
 352         has an eq function, the object being assigned to it (e.g. a python
 353         object) might not.  despite the *input* having an eq function,
 354         that doesn't help us, because it's the *ArrayProxy* that's being
 355         assigned to.  so.... we cheat.  use the ports() function of the
 356         python object, enumerate them, find out the list of Signals that way,
 357         and assign them.
 358     """
 359     def iterator2(self, o, i):
 360         if isinstance(o, dict):
 361             yield from self.dict_iter2(o, i)
 362
 363         if not isinstance(o, Sequence):
 364             o, i = [o], [i]
 365         for (ao, ai) in zip(o, i):
 366             #print ("visit", fn, ao, ai)
 367             if isinstance(ao, Record):
 368                 yield from self.record_iter2(ao, ai)
 369             elif isinstance(ao, ArrayProxy) and not isinstance(ai, Value):
 370                 yield from self.arrayproxy_iter2(ao, ai)
 371             else:
 372                 yield (ao, ai)
 373
 374     def dict_iter2(self, o, i):
 375         for (k, v) in o.items():
 376             print ("d-iter", v, i[k])
 377             yield (v, i[k])
 378         return res
 379
 380     def _not_quite_working_with_all_unit_tests_record_iter2(self, ao, ai):
 381         print ("record_iter2", ao, ai, type(ao), type(ai))
 382         if isinstance(ai, Value):
 383             if isinstance(ao, Sequence):
 384                 ao, ai = [ao], [ai]
 385             for o, i in zip(ao, ai):
 386                 yield (o, i)
 387             return
 388         for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 389             if isinstance(field_shape, Layout):
 390                 val = ai.fields
 391             else:
 392                 val = ai
 393             if hasattr(val, field_name): # check for attribute
 394                 val = getattr(val, field_name)
 395             else:
 396                 val = val[field_name] # dictionary-style specification
 397             yield from self.iterator2(ao.fields[field_name], val)
 398
 399     def record_iter2(self, ao, ai):
 400         for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 401             if isinstance(field_shape, Layout):
 402                 val = ai.fields
 403             else:
 404                 val = ai
 405             if hasattr(val, field_name): # check for attribute
 406                 val = getattr(val, field_name)
 407             else:
 408                 val = val[field_name] # dictionary-style specification
 409             yield from self.iterator2(ao.fields[field_name], val)
 410
 411     def arrayproxy_iter2(self, ao, ai):
 412         for p in ai.ports():
 413             op = getattr(ao, p.name)
 414             print ("arrayproxy - p", p, p.name)
 415             yield from self.iterator2(op, p)
 416
 417
 418 class Visitor:
 419     """ a helper class for iterating single-argument compound data structures.
 420         similar to Visitor2.
 421     """
 422     def iterate(self, i):
 423         """ iterate a compound structure recursively using yield
 424         """
 425         if not isinstance(i, Sequence):
 426             i = [i]
 427         for ai in i:
 428             print ("iterate", ai)
 429             if isinstance(ai, Record):
 430                 print ("record", list(ai.layout))
 431                 yield from self.record_iter(ai)
 432             elif isinstance(ai, ArrayProxy) and not isinstance(ai, Value):
 433                 yield from self.array_iter(ai)
 434             else:
 435                 yield ai
 436
 437     def record_iter(self, ai):
 438         for idx, (field_name, field_shape, _) in enumerate(ai.layout):
 439             if isinstance(field_shape, Layout):
 440                 val = ai.fields
 441             else:
 442                 val = ai
 443             if hasattr(val, field_name): # check for attribute
 444                 val = getattr(val, field_name)
 445             else:
 446                 val = val[field_name] # dictionary-style specification
 447             print ("recidx", idx, field_name, field_shape, val)
 448             yield from self.iterate(val)
 449
 450     def array_iter(self, ai):
 451         for p in ai.ports():
 452             yield from self.iterate(p)
 453
 454
 455 def eq(o, i):
 456     """ makes signals equal: a helper routine which identifies if it is being
 457         passed a list (or tuple) of objects, or signals, or Records, and calls
 458         the objects' eq function.
 459     """
 460     res = []
 461     for (ao, ai) in Visitor2().iterator2(o, i):
 462         rres = ao.eq(ai)
 463         if not isinstance(rres, Sequence):
 464             rres = [rres]
 465         res += rres
 466     return res
 467
 468
 469 def cat(i):
 470     """ flattens a compound structure recursively using Cat
 471     """
 472     from nmigen.tools import flatten
 473     #res = list(flatten(i)) # works (as of nmigen commit f22106e5) HOWEVER...
 474     res = list(Visitor().iterate(i)) # needed because input may be a sequence
 475     return Cat(*res)
 476
 477
 478 class StageCls(metaclass=ABCMeta):
 479     """ Class-based "Stage" API.  requires instantiation (after derivation)
 480
 481         see "Stage API" above..  Note: python does *not* require derivation
 482         from this class.  All that is required is that the pipelines *have*
 483         the functions listed in this class.  Derivation from this class
 484         is therefore merely a "courtesy" to maintainers.
 485     """
 486     @abstractmethod
 487     def ispec(self): pass       # REQUIRED
 488     @abstractmethod
 489     def ospec(self): pass       # REQUIRED
 490     #@abstractmethod
 491     #def setup(self, m, i): pass # OPTIONAL
 492     @abstractmethod
 493     def process(self, i): pass  # REQUIRED
 494
 495
 496 class Stage(metaclass=ABCMeta):
 497     """ Static "Stage" API.  does not require instantiation (after derivation)
 498
 499         see "Stage API" above.  Note: python does *not* require derivation
 500         from this class.  All that is required is that the pipelines *have*
 501         the functions listed in this class.  Derivation from this class
 502         is therefore merely a "courtesy" to maintainers.
 503     """
 504     @staticmethod
 505     @abstractmethod
 506     def ispec(): pass
 507
 508     @staticmethod
 509     @abstractmethod
 510     def ospec(): pass
 511
 512     #@staticmethod
 513     #@abstractmethod
 514     #def setup(m, i): pass
 515
 516     @staticmethod
 517     @abstractmethod
 518     def process(i): pass
 519
 520
 521 class RecordBasedStage(Stage):
 522     """ convenience class which provides a Records-based layout.
 523         honestly it's a lot easier just to create a direct Records-based
 524         class (see ExampleAddRecordStage)
 525     """
 526     def __init__(self, in_shape, out_shape, processfn, setupfn=None):
 527         self.in_shape = in_shape
 528         self.out_shape = out_shape
 529         self.__process = processfn
 530         self.__setup = setupfn
 531     def ispec(self): return Record(self.in_shape)
 532     def ospec(self): return Record(self.out_shape)
 533     def process(seif, i): return self.__process(i)
 534     def setup(seif, m, i): return self.__setup(m, i)
 535
 536
 537 class StageChain(StageCls):
 538     """ pass in a list of stages, and they will automatically be
 539         chained together via their input and output specs into a
 540         combinatorial chain.
 541
 542         the end result basically conforms to the exact same Stage API.
 543
 544         * input to this class will be the input of the first stage
 545         * output of first stage goes into input of second
 546         * output of second goes into input into third (etc. etc.)
 547         * the output of this class will be the output of the last stage
 548     """
 549     def __init__(self, chain, specallocate=False):
 550         self.chain = chain
 551         self.specallocate = specallocate
 552
 553     def ispec(self):
 554         return self.chain[0].ispec()
 555
 556     def ospec(self):
 557         return self.chain[-1].ospec()
 558
 559     def _specallocate_setup(self, m, i):
 560         for (idx, c) in enumerate(self.chain):
 561             if hasattr(c, "setup"):
 562                 c.setup(m, i)               # stage may have some module stuff
 563             o = self.chain[idx].ospec()     # last assignment survives
 564             m.d.comb += eq(o, c.process(i)) # process input into "o"
 565             if idx == len(self.chain)-1:
 566                 break
 567             i = self.chain[idx+1].ispec()   # new input on next loop
 568             m.d.comb += eq(i, o)            # assign to next input
 569         return o                            # last loop is the output
 570
 571     def _noallocate_setup(self, m, i):
 572         for (idx, c) in enumerate(self.chain):
 573             if hasattr(c, "setup"):
 574                 c.setup(m, i)               # stage may have some module stuff
 575             i = o = c.process(i)            # store input into "o"
 576         return o                            # last loop is the output
 577
 578     def setup(self, m, i):
 579         if self.specallocate:
 580             self.o = self._specallocate_setup(m, i)
 581         else:
 582             self.o = self._noallocate_setup(m, i)
 583
 584     def process(self, i):
 585         return self.o # conform to Stage API: return last-loop output
 586
 587
 588 class ControlBase:
 589     """ Common functions for Pipeline API
 590     """
 591     def __init__(self, stage=None, in_multi=None, stage_ctl=False):
 592         """ Base class containing ready/valid/data to previous and next stages
 593
 594             * p: contains ready/valid to the previous stage
 595             * n: contains ready/valid to the next stage
 596
 597             Except when calling Controlbase.connect(), user must also:
 598             * add i_data member to PrevControl (p) and
 599             * add o_data member to NextControl (n)
 600         """
 601         self.stage = stage
 602
 603         # set up input and output IO ACK (prev/next ready/valid)
 604         self.p = PrevControl(in_multi, stage_ctl)
 605         self.n = NextControl(stage_ctl)
 606
 607         # set up the input and output data
 608         if stage is not None:
 609             self.p.i_data = stage.ispec() # input type
 610             self.n.o_data = stage.ospec()
 611
 612     def connect_to_next(self, nxt):
 613         """ helper function to connect to the next stage data/valid/ready.
 614         """
 615         return self.n.connect_to_next(nxt.p)
 616
 617     def _connect_in(self, prev):
 618         """ internal helper function to connect stage to an input source.
 619             do not use to connect stage-to-stage!
 620         """
 621         return self.p._connect_in(prev.p)
 622
 623     def _connect_out(self, nxt):
 624         """ internal helper function to connect stage to an output source.
 625             do not use to connect stage-to-stage!
 626         """
 627         return self.n._connect_out(nxt.n)
 628
 629     def connect(self, pipechain):
 630         """ connects a chain (list) of Pipeline instances together and
 631             links them to this ControlBase instance:
 632
 633                       in <----> self <---> out
 634                        |                   ^
 635                        v                   |
 636                     [pipe1, pipe2, pipe3, pipe4]
 637                        |    ^  |    ^  |     ^
 638                        v    |  v    |  v     |
 639                      out---in out--in out---in
 640
 641             Also takes care of allocating i_data/o_data, by looking up
 642             the data spec for each end of the pipechain.  i.e It is NOT
 643             necessary to allocate self.p.i_data or self.n.o_data manually:
 644             this is handled AUTOMATICALLY, here.
 645
 646             Basically this function is the direct equivalent of StageChain,
 647             except that unlike StageChain, the Pipeline logic is followed.
 648
 649             Just as StageChain presents an object that conforms to the
 650             Stage API from a list of objects that also conform to the
 651             Stage API, an object that calls this Pipeline connect function
 652             has the exact same pipeline API as the list of pipline objects
 653             it is called with.
 654
 655             Thus it becomes possible to build up larger chains recursively.
 656             More complex chains (multi-input, multi-output) will have to be
 657             done manually.
 658         """
 659         eqs = [] # collated list of assignment statements
 660
 661         # connect inter-chain
 662         for i in range(len(pipechain)-1):
 663             pipe1 = pipechain[i]
 664             pipe2 = pipechain[i+1]
 665             eqs += pipe1.connect_to_next(pipe2)
 666
 667         # connect front of chain to ourselves
 668         front = pipechain[0]
 669         self.p.i_data = front.stage.ispec()
 670         eqs += front._connect_in(self)
 671
 672         # connect end of chain to ourselves
 673         end = pipechain[-1]
 674         self.n.o_data = end.stage.ospec()
 675         eqs += end._connect_out(self)
 676
 677         return eqs
 678
 679     def _postprocess(self, i): # XXX DISABLED
 680         return i # RETURNS INPUT
 681         if hasattr(self.stage, "postprocess"):
 682             return self.stage.postprocess(i)
 683         return i
 684
 685     def set_input(self, i):
 686         """ helper function to set the input data
 687         """
 688         return eq(self.p.i_data, i)
 689
 690     def ports(self):
 691         return self.p.ports() + self.n.ports()
 692
 693     def _elaborate(self, platform):
 694         """ handles case where stage has dynamic ready/valid functions
 695         """
 696         m = Module()
 697
 698         if self.stage is not None and hasattr(self.stage, "setup"):
 699             self.stage.setup(m, self.p.i_data)
 700
 701         if not self.p.stage_ctl:
 702             return m
 703
 704         # intercept the previous (outgoing) "ready", combine with stage ready
 705         m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.d_ready)
 706
 707         # intercept the next (incoming) "ready" and combine it with data valid
 708         sdv = self.stage.d_valid(self.n.i_ready)
 709         m.d.comb += self.n.d_valid.eq(self.n.i_ready & sdv)
 710
 711         return m
 712
 713
 714 class BufferedHandshake(ControlBase):
 715     """ buffered pipeline stage.  data and strobe signals travel in sync.
 716         if ever the input is ready and the output is not, processed data
 717         is shunted in a temporary register.
 718
 719         Argument: stage.  see Stage API above
 720
 721         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 722         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 723         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 724                               |             |
 725                             process --->----^
 726                               |             |
 727                               +-- r_data ->-+
 728
 729         input data p.i_data is read (only), is processed and goes into an
 730         intermediate result store [process()].  this is updated combinatorially.
 731
 732         in a non-stall condition, the intermediate result will go into the
 733         output (update_output).  however if ever there is a stall, it goes
 734         into r_data instead [update_buffer()].
 735
 736         when the non-stall condition is released, r_data is the first
 737         to be transferred to the output [flush_buffer()], and the stall
 738         condition cleared.
 739
 740         on the next cycle (as long as stall is not raised again) the
 741         input may begin to be processed and transferred directly to output.
 742     """
 743
 744     def elaborate(self, platform):
 745         self.m = ControlBase._elaborate(self, platform)
 746
 747         result = self.stage.ospec()
 748         r_data = self.stage.ospec()
 749
 750         # establish some combinatorial temporaries
 751         o_n_validn = Signal(reset_less=True)
 752         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
 753         nir_por = Signal(reset_less=True)
 754         nir_por_n = Signal(reset_less=True)
 755         p_i_valid = Signal(reset_less=True)
 756         nir_novn = Signal(reset_less=True)
 757         nirn_novn = Signal(reset_less=True)
 758         por_pivn = Signal(reset_less=True)
 759         npnn = Signal(reset_less=True)
 760         self.m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
 761                      o_n_validn.eq(~self.n.o_valid),
 762                      n_i_ready.eq(self.n.i_ready_test),
 763                      nir_por.eq(n_i_ready & self.p._o_ready),
 764                      nir_por_n.eq(n_i_ready & ~self.p._o_ready),
 765                      nir_novn.eq(n_i_ready | o_n_validn),
 766                      nirn_novn.eq(~n_i_ready & o_n_validn),
 767                      npnn.eq(nir_por | nirn_novn),
 768                      por_pivn.eq(self.p._o_ready & ~p_i_valid)
 769         ]
 770
 771         # store result of processing in combinatorial temporary
 772         self.m.d.comb += eq(result, self.stage.process(self.p.i_data))
 773
 774         # if not in stall condition, update the temporary register
 775         with self.m.If(self.p.o_ready): # not stalled
 776             self.m.d.sync += eq(r_data, result) # update buffer
 777
 778         # data pass-through conditions
 779         with self.m.If(npnn):
 780             o_data = self._postprocess(result)
 781             self.m.d.sync += [self.n.o_valid.eq(p_i_valid), # valid if p_valid
 782                               eq(self.n.o_data, o_data),    # update output
 783                              ]
 784         # buffer flush conditions (NOTE: can override data passthru conditions)
 785         with self.m.If(nir_por_n): # not stalled
 786             # Flush the [already processed] buffer to the output port.
 787             o_data = self._postprocess(r_data)
 788             self.m.d.sync += [self.n.o_valid.eq(1),  # reg empty
 789                               eq(self.n.o_data, o_data), # flush buffer
 790                              ]
 791         # output ready conditions
 792         self.m.d.sync += self.p._o_ready.eq(nir_novn | por_pivn)
 793
 794         return self.m
 795
 796
 797 class SimpleHandshake(ControlBase):
 798     """ simple handshake control.  data and strobe signals travel in sync.
 799         implements the protocol used by Wishbone and AXI4.
 800
 801         Argument: stage.  see Stage API above
 802
 803         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 804         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 805         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 806                               |             |
 807                               +--process->--^
 808         Truth Table
 809
 810         Inputs   Temporary  Output Data
 811         -------  ---------- -----  ----
 812         P P N N  PiV& ~NiR&  N P
 813         i o i o  PoR  NoV    o o
 814         V R R V              V R
 815
 816         -------   -    -     - -
 817         0 0 0 0   0    0    >0 0    reg
 818         0 0 0 1   0    1    >1 0    reg
 819         0 0 1 0   0    0     0 1    process(i_data)
 820         0 0 1 1   0    0     0 1    process(i_data)
 821         -------   -    -     - -
 822         0 1 0 0   0    0    >0 0    reg
 823         0 1 0 1   0    1    >1 0    reg
 824         0 1 1 0   0    0     0 1    process(i_data)
 825         0 1 1 1   0    0     0 1    process(i_data)
 826         -------   -    -     - -
 827         1 0 0 0   0    0    >0 0    reg
 828         1 0 0 1   0    1    >1 0    reg
 829         1 0 1 0   0    0     0 1    process(i_data)
 830         1 0 1 1   0    0     0 1    process(i_data)
 831         -------   -    -     - -
 832         1 1 0 0   1    0     1 0    process(i_data)
 833         1 1 0 1   1    1     1 0    process(i_data)
 834         1 1 1 0   1    0     1 1    process(i_data)
 835         1 1 1 1   1    0     1 1    process(i_data)
 836         -------   -    -     - -
 837     """
 838
 839     def elaborate(self, platform):
 840         self.m = m = ControlBase._elaborate(self, platform)
 841
 842         r_busy = Signal()
 843         result = self.stage.ospec()
 844
 845         # establish some combinatorial temporaries
 846         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
 847         p_i_valid_p_o_ready = Signal(reset_less=True)
 848         p_i_valid = Signal(reset_less=True)
 849         m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
 850                      n_i_ready.eq(self.n.i_ready_test),
 851                      p_i_valid_p_o_ready.eq(p_i_valid & self.p.o_ready),
 852         ]
 853
 854         # store result of processing in combinatorial temporary
 855         m.d.comb += eq(result, self.stage.process(self.p.i_data))
 856
 857         # previous valid and ready
 858         with m.If(p_i_valid_p_o_ready):
 859             o_data = self._postprocess(result)
 860             m.d.sync += [r_busy.eq(1),      # output valid
 861                          eq(self.n.o_data, o_data), # update output
 862                         ]
 863         # previous invalid or not ready, however next is accepting
 864         with m.Elif(n_i_ready):
 865             o_data = self._postprocess(result)
 866             m.d.sync += [eq(self.n.o_data, o_data)]
 867             # TODO: could still send data here (if there was any)
 868             #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
 869             m.d.sync += r_busy.eq(0) # ...so set output invalid
 870
 871         m.d.comb += self.n.o_valid.eq(r_busy)
 872         # if next is ready, so is previous
 873         m.d.comb += self.p._o_ready.eq(n_i_ready)
 874
 875         return self.m
 876
 877
 878 class UnbufferedPipeline(ControlBase):
 879     """ A simple pipeline stage with single-clock synchronisation
 880         and two-way valid/ready synchronised signalling.
 881
 882         Note that a stall in one stage will result in the entire pipeline
 883         chain stalling.
 884
 885         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 886         travel synchronously with the data: the valid/ready signalling
 887         combines in a *combinatorial* fashion.  Therefore, a long pipeline
 888         chain will lengthen propagation delays.
 889
 890         Argument: stage.  see Stage API, above
 891
 892         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 893         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 894         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 895                               |             |
 896                             r_data        result
 897                               |             |
 898                               +--process ->-+
 899
 900         Attributes:
 901         -----------
 902         p.i_data : StageInput, shaped according to ispec
 903             The pipeline input
 904         p.o_data : StageOutput, shaped according to ospec
 905             The pipeline output
 906         r_data : input_shape according to ispec
 907             A temporary (buffered) copy of a prior (valid) input.
 908             This is HELD if the output is not ready.  It is updated
 909             SYNCHRONOUSLY.
 910         result: output_shape according to ospec
 911             The output of the combinatorial logic.  it is updated
 912             COMBINATORIALLY (no clock dependence).
 913
 914         Truth Table
 915
 916         Inputs  Temp  Output  Data
 917         -------   -   -----   ----
 918         P P N N ~NiR&  N P
 919         i o i o  NoV   o o
 920         V R R V        V R
 921
 922         -------   -    - -
 923         0 0 0 0   0    0 1    reg
 924         0 0 0 1   1    1 0    reg
 925         0 0 1 0   0    0 1    reg
 926         0 0 1 1   0    0 1    reg
 927         -------   -    - -
 928         0 1 0 0   0    0 1    reg
 929         0 1 0 1   1    1 0    reg
 930         0 1 1 0   0    0 1    reg
 931         0 1 1 1   0    0 1    reg
 932         -------   -    - -
 933         1 0 0 0   0    1 1    reg
 934         1 0 0 1   1    1 0    reg
 935         1 0 1 0   0    1 1    reg
 936         1 0 1 1   0    1 1    reg
 937         -------   -    - -
 938         1 1 0 0   0    1 1    process(i_data)
 939         1 1 0 1   1    1 0    process(i_data)
 940         1 1 1 0   0    1 1    process(i_data)
 941         1 1 1 1   0    1 1    process(i_data)
 942         -------   -    - -
 943
 944         Note: PoR is *NOT* involved in the above decision-making.
 945     """
 946
 947     def elaborate(self, platform):
 948         self.m = m = ControlBase._elaborate(self, platform)
 949
 950         data_valid = Signal() # is data valid or not
 951         r_data = self.stage.ospec() # output type
 952
 953         # some temporaries
 954         p_i_valid = Signal(reset_less=True)
 955         pv = Signal(reset_less=True)
 956         buf_full = Signal(reset_less=True)
 957         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
 958         m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
 959         m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
 960
 961         m.d.comb += self.n.o_valid.eq(data_valid)
 962         m.d.comb += self.p._o_ready.eq(~data_valid | self.n.i_ready_test)
 963         m.d.sync += data_valid.eq(p_i_valid | buf_full)
 964
 965         with m.If(pv):
 966             m.d.sync += eq(r_data, self.stage.process(self.p.i_data))
 967         o_data = self._postprocess(r_data)
 968         m.d.comb += eq(self.n.o_data, o_data)
 969
 970         return self.m
 971
 972 class UnbufferedPipeline2(ControlBase):
 973     """ A simple pipeline stage with single-clock synchronisation
 974         and two-way valid/ready synchronised signalling.
 975
 976         Note that a stall in one stage will result in the entire pipeline
 977         chain stalling.
 978
 979         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 980         travel synchronously with the data: the valid/ready signalling
 981         combines in a *combinatorial* fashion.  Therefore, a long pipeline
 982         chain will lengthen propagation delays.
 983
 984         Argument: stage.  see Stage API, above
 985
 986         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 987         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 988         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 989                               |             |    |
 990                               +- process-> buf <-+
 991         Attributes:
 992         -----------
 993         p.i_data : StageInput, shaped according to ispec
 994             The pipeline input
 995         p.o_data : StageOutput, shaped according to ospec
 996             The pipeline output
 997         buf : output_shape according to ospec
 998             A temporary (buffered) copy of a valid output
 999             This is HELD if the output is not ready.  It is updated
1000             SYNCHRONOUSLY.
1001
1002         Inputs  Temp  Output Data
1003         -------   -   -----
1004         P P N N ~NiR&  N P   (buf_full)
1005         i o i o  NoV   o o
1006         V R R V        V R
1007
1008         -------   -    - -
1009         0 0 0 0   0    0 1   process(i_data)
1010         0 0 0 1   1    1 0   reg (odata, unchanged)
1011         0 0 1 0   0    0 1   process(i_data)
1012         0 0 1 1   0    0 1   process(i_data)
1013         -------   -    - -
1014         0 1 0 0   0    0 1   process(i_data)
1015         0 1 0 1   1    1 0   reg (odata, unchanged)
1016         0 1 1 0   0    0 1   process(i_data)
1017         0 1 1 1   0    0 1   process(i_data)
1018         -------   -    - -
1019         1 0 0 0   0    1 1   process(i_data)
1020         1 0 0 1   1    1 0   reg (odata, unchanged)
1021         1 0 1 0   0    1 1   process(i_data)
1022         1 0 1 1   0    1 1   process(i_data)
1023         -------   -    - -
1024         1 1 0 0   0    1 1   process(i_data)
1025         1 1 0 1   1    1 0   reg (odata, unchanged)
1026         1 1 1 0   0    1 1   process(i_data)
1027         1 1 1 1   0    1 1   process(i_data)
1028         -------   -    - -
1029
1030         Note: PoR is *NOT* involved in the above decision-making.
1031     """
1032
1033     def elaborate(self, platform):
1034         self.m = m = ControlBase._elaborate(self, platform)
1035
1036         buf_full = Signal() # is data valid or not
1037         buf = self.stage.ospec() # output type
1038
1039         # some temporaries
1040         p_i_valid = Signal(reset_less=True)
1041         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
1042
1043         m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
1044         m.d.comb += self.p._o_ready.eq(~buf_full)
1045         m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
1046
1047         o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
1048         o_data = self._postprocess(o_data)
1049         m.d.comb += eq(self.n.o_data, o_data)
1050         m.d.sync += eq(buf, self.n.o_data)
1051
1052         return self.m
1053
1054
1055 class PassThroughStage(StageCls):
1056     """ a pass-through stage which has its input data spec equal to its output,
1057         and "passes through" its data from input to output.
1058     """
1059     def __init__(self, iospecfn):
1060         self.iospecfn = iospecfn
1061     def ispec(self): return self.iospecfn()
1062     def ospec(self): return self.iospecfn()
1063     def process(self, i): return i
1064
1065
1066 class PassThroughHandshake(ControlBase):
1067     """ A control block that delays by one clock cycle.
1068
1069         Inputs   Temporary          Output Data
1070         -------  ------------------  ----- ----
1071         P P N N  PiV& PiV| NiR| pvr   N P  (pvr)
1072         i o i o  PoR  ~PoR ~NoV       o o
1073         V R R V                       V R
1074
1075         -------   -    -    -   -     - -
1076         0 0 0 0   0    1    1   0     1 1   odata (unchanged)
1077         0 0 0 1   0    1    0   0     1 0   odata (unchanged)
1078         0 0 1 0   0    1    1   0     1 1   odata (unchanged)
1079         0 0 1 1   0    1    1   0     1 1   odata (unchanged)
1080         -------   -    -    -   -     - -
1081         0 1 0 0   0    0    1   0     0 1   odata (unchanged)
1082         0 1 0 1   0    0    0   0     0 0   odata (unchanged)
1083         0 1 1 0   0    0    1   0     0 1   odata (unchanged)
1084         0 1 1 1   0    0    1   0     0 1   odata (unchanged)
1085         -------   -    -    -   -     - -
1086         1 0 0 0   0    1    1   1     1 1   process(in)
1087         1 0 0 1   0    1    0   0     1 0   odata (unchanged)
1088         1 0 1 0   0    1    1   1     1 1   process(in)
1089         1 0 1 1   0    1    1   1     1 1   process(in)
1090         -------   -    -    -   -     - -
1091         1 1 0 0   1    1    1   1     1 1   process(in)
1092         1 1 0 1   1    1    0   0     1 0   odata (unchanged)
1093         1 1 1 0   1    1    1   1     1 1   process(in)
1094         1 1 1 1   1    1    1   1     1 1   process(in)
1095         -------   -    -    -   -     - -
1096
1097     """
1098
1099     def elaborate(self, platform):
1100         self.m = m = ControlBase._elaborate(self, platform)
1101
1102         r_data = self.stage.ospec() # output type
1103
1104         # temporaries
1105         p_i_valid = Signal(reset_less=True)
1106         pvr = Signal(reset_less=True)
1107         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
1108         m.d.comb += pvr.eq(p_i_valid & self.p.o_ready)
1109
1110         m.d.comb += self.p.o_ready.eq(~self.n.o_valid |  self.n.i_ready_test)
1111         m.d.sync += self.n.o_valid.eq(p_i_valid       | ~self.p.o_ready)
1112
1113         odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
1114         m.d.sync += eq(r_data, odata)
1115         r_data = self._postprocess(r_data)
1116         m.d.comb += eq(self.n.o_data, r_data)
1117
1118         return m
1119
1120
1121 class RegisterPipeline(UnbufferedPipeline):
1122     """ A pipeline stage that delays by one clock cycle, creating a
1123         sync'd latch out of o_data and o_valid as an indirect byproduct
1124         of using PassThroughStage
1125     """
1126     def __init__(self, iospecfn):
1127         UnbufferedPipeline.__init__(self, PassThroughStage(iospecfn))
1128
1129
1130 class FIFOControl(ControlBase):
1131     """ FIFO Control.  Uses SyncFIFO to store data, coincidentally
1132         happens to have same valid/ready signalling as Stage API.
1133
1134         i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
1135     """
1136
1137     def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
1138                                      fwft=True, buffered=False, pipe=False):
1139         """ FIFO Control
1140
1141             * depth: number of entries in the FIFO
1142             * stage: data processing block
1143             * fwft : first word fall-thru mode (non-fwft introduces delay)
1144             * buffered: use buffered FIFO (introduces extra cycle delay)
1145
1146             NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
1147                     (fwft=True, buffered=False)
1148
1149             NOTE 2: i_data *must* have a shape function.  it can therefore
1150                     be a Signal, or a Record, or a RecordObject.
1151
1152             data is processed (and located) as follows:
1153
1154             self.p  self.stage temp    fn temp  fn  temp  fp   self.n
1155             i_data->process()->result->cat->din.FIFO.dout->cat(o_data)
1156
1157             yes, really: cat produces a Cat() which can be assigned to.
1158             this is how the FIFO gets de-catted without needing a de-cat
1159             function
1160         """
1161
1162         assert not (fwft and buffered), "buffered cannot do fwft"
1163         if buffered:
1164             depth += 1
1165         self.fwft = fwft
1166         self.buffered = buffered
1167         self.pipe = pipe
1168         self.fdepth = depth
1169         ControlBase.__init__(self, stage, in_multi, stage_ctl)
1170
1171     def elaborate(self, platform):
1172         self.m = m = ControlBase._elaborate(self, platform)
1173
1174         # make a FIFO with a signal of equal width to the o_data.
1175         (fwidth, _) = self.n.o_data.shape()
1176         if self.buffered:
1177             fifo = SyncFIFOBuffered(fwidth, self.fdepth)
1178         else:
1179             fifo = Queue(fwidth, self.fdepth, fwft=self.fwft, pipe=self.pipe)
1180         m.submodules.fifo = fifo
1181
1182         # store result of processing in combinatorial temporary
1183         result = self.stage.ospec()
1184         m.d.comb += eq(result, self.stage.process(self.p.i_data))
1185
1186         # connect previous rdy/valid/data - do cat on i_data
1187         # NOTE: cannot do the PrevControl-looking trick because
1188         # of need to process the data.  shaaaame....
1189         m.d.comb += [fifo.we.eq(self.p.i_valid_test),
1190                      self.p.o_ready.eq(fifo.writable),
1191                      eq(fifo.din, cat(result)),
1192                    ]
1193
1194         # connect next rdy/valid/data - do cat on o_data
1195         connections = [self.n.o_valid.eq(fifo.readable),
1196                      fifo.re.eq(self.n.i_ready_test),
1197                    ]
1198         if self.fwft or self.buffered:
1199             m.d.comb += connections
1200         else:
1201             m.d.sync += connections # unbuffered fwft mode needs sync
1202         o_data = cat(self.n.o_data).eq(fifo.dout)
1203         o_data = self._postprocess(o_data)
1204         m.d.comb += o_data
1205
1206         return m
1207
1208
1209 # aka "RegStage".
1210 class UnbufferedPipeline(FIFOControl):
1211     def __init__(self, stage, in_multi=None, stage_ctl=False):
1212         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
1213                                    fwft=True, pipe=False)
1214
1215 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
1216 class PassThroughHandshake(FIFOControl):
1217     def __init__(self, stage, in_multi=None, stage_ctl=False):
1218         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
1219                                    fwft=True, pipe=True)
1220
1221 # this is *probably* BufferedHandshake, although test #997 now succeeds.
1222 class BufferedHandshake(FIFOControl):
1223     def __init__(self, stage, in_multi=None, stage_ctl=False):
1224         FIFOControl.__init__(self, 2, stage, in_multi, stage_ctl,
1225                                    fwft=True, pipe=False)
1226
1227
1228 """
1229 # this is *probably* SimpleHandshake (note: memory cell size=0)
1230 class SimpleHandshake(FIFOControl):
1231     def __init__(self, stage, in_multi=None, stage_ctl=False):
1232         FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
1233                                    fwft=True, pipe=False)
1234 """