1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
155 Synchronised pipeline
158 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
161 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
162 from nmigen
.cli
import verilog
, rtlil
163 from nmigen
.hdl
.ast
import ArrayProxy
164 from nmigen
.hdl
.rec
import Record
, Layout
166 from abc
import ABCMeta
, abstractmethod
167 from collections
.abc
import Sequence
171 """ contains signals that come *from* the previous stage (both in and out)
172 * i_valid: previous stage indicating all incoming data is valid.
173 may be a multi-bit signal, where all bits are required
174 to be asserted to indicate "valid".
175 * o_ready: output to next stage indicating readiness to accept data
176 * i_data : an input - added by the user of this class
179 def __init__(self
, i_width
=1, stage_ctl
=False):
180 self
.stage_ctl
= stage_ctl
181 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
182 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
183 self
.i_data
= None # XXX MUST BE ADDED BY USER
185 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
189 """ public-facing API: indicates (externally) that stage is ready
192 return self
.s_o_ready
# set dynamically by stage
193 return self
._o
_ready
# return this when not under dynamic control
195 def _connect_in(self
, prev
):
196 """ internal helper function to connect stage to an input source.
197 do not use to connect stage-to-stage!
199 return [self
.i_valid
.eq(prev
.i_valid_test
),
200 prev
.o_ready
.eq(self
.o_ready
),
201 eq(self
.i_data
, prev
.i_data
),
205 def i_valid_test(self
):
206 vlen
= len(self
.i_valid
)
208 # multi-bit case: valid only when i_valid is all 1s
209 all1s
= Const(-1, (len(self
.i_valid
), False))
210 i_valid
= (self
.i_valid
== all1s
)
212 # single-bit i_valid case
213 i_valid
= self
.i_valid
215 # when stage indicates not ready, incoming data
216 # must "appear" to be not ready too
218 i_valid
= i_valid
& self
.s_o_ready
224 """ contains the signals that go *to* the next stage (both in and out)
225 * o_valid: output indicating to next stage that data is valid
226 * i_ready: input from next stage indicating that it can accept data
227 * o_data : an output - added by the user of this class
229 def __init__(self
, stage_ctl
=False):
230 self
.stage_ctl
= stage_ctl
231 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
232 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
233 self
.o_data
= None # XXX MUST BE ADDED BY USER
235 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
238 def i_ready_test(self
):
240 return self
.i_ready
& self
.d_valid
243 def connect_to_next(self
, nxt
):
244 """ helper function to connect to the next stage data/valid/ready.
245 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
246 use this when connecting stage-to-stage
248 return [nxt
.i_valid
.eq(self
.o_valid
),
249 self
.i_ready
.eq(nxt
.o_ready
),
250 eq(nxt
.i_data
, self
.o_data
),
253 def _connect_out(self
, nxt
):
254 """ internal helper function to connect stage to an output source.
255 do not use to connect stage-to-stage!
257 return [nxt
.o_valid
.eq(self
.o_valid
),
258 self
.i_ready
.eq(nxt
.i_ready_test
),
259 eq(nxt
.o_data
, self
.o_data
),
264 """ makes signals equal: a helper routine which identifies if it is being
265 passed a list (or tuple) of objects, or signals, or Records, and calls
266 the objects' eq function.
268 complex objects (classes) can be used: they must follow the
269 convention of having an eq member function, which takes the
270 responsibility of further calling eq and returning a list of
273 Record is a special (unusual, recursive) case, where the input may be
274 specified as a dictionary (which may contain further dictionaries,
275 recursively), where the field names of the dictionary must match
276 the Record's field spec. Alternatively, an object with the same
277 member names as the Record may be assigned: it does not have to
280 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
281 has an eq function, the object being assigned to it (e.g. a python
282 object) might not. despite the *input* having an eq function,
283 that doesn't help us, because it's the *ArrayProxy* that's being
284 assigned to. so.... we cheat. use the ports() function of the
285 python object, enumerate them, find out the list of Signals that way,
289 if isinstance(o
, dict):
290 for (k
, v
) in o
.items():
291 print ("d-eq", v
, i
[k
])
292 res
.append(v
.eq(i
[k
]))
295 if not isinstance(o
, Sequence
):
297 for (ao
, ai
) in zip(o
, i
):
298 #print ("eq", ao, ai)
299 if isinstance(ao
, Record
):
300 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
301 if isinstance(field_shape
, Layout
):
305 if hasattr(val
, field_name
): # check for attribute
306 val
= getattr(val
, field_name
)
308 val
= val
[field_name
] # dictionary-style specification
309 rres
= eq(ao
.fields
[field_name
], val
)
311 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
313 op
= getattr(ao
, p
.name
)
314 #print (op, p, p.name)
316 if not isinstance(rres
, Sequence
):
321 if not isinstance(rres
, Sequence
):
327 class StageCls(metaclass
=ABCMeta
):
328 """ Class-based "Stage" API. requires instantiation (after derivation)
330 see "Stage API" above.. Note: python does *not* require derivation
331 from this class. All that is required is that the pipelines *have*
332 the functions listed in this class. Derivation from this class
333 is therefore merely a "courtesy" to maintainers.
336 def ispec(self
): pass # REQUIRED
338 def ospec(self
): pass # REQUIRED
340 #def setup(self, m, i): pass # OPTIONAL
342 def process(self
, i
): pass # REQUIRED
345 class Stage(metaclass
=ABCMeta
):
346 """ Static "Stage" API. does not require instantiation (after derivation)
348 see "Stage API" above. Note: python does *not* require derivation
349 from this class. All that is required is that the pipelines *have*
350 the functions listed in this class. Derivation from this class
351 is therefore merely a "courtesy" to maintainers.
363 #def setup(m, i): pass
370 class RecordBasedStage(Stage
):
371 """ convenience class which provides a Records-based layout.
372 honestly it's a lot easier just to create a direct Records-based
373 class (see ExampleAddRecordStage)
375 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
376 self
.in_shape
= in_shape
377 self
.out_shape
= out_shape
378 self
.__process
= processfn
379 self
.__setup
= setupfn
380 def ispec(self
): return Record(self
.in_shape
)
381 def ospec(self
): return Record(self
.out_shape
)
382 def process(seif
, i
): return self
.__process
(i
)
383 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
386 class StageChain(StageCls
):
387 """ pass in a list of stages, and they will automatically be
388 chained together via their input and output specs into a
391 the end result basically conforms to the exact same Stage API.
393 * input to this class will be the input of the first stage
394 * output of first stage goes into input of second
395 * output of second goes into input into third (etc. etc.)
396 * the output of this class will be the output of the last stage
398 def __init__(self
, chain
, specallocate
=False):
400 self
.specallocate
= specallocate
403 return self
.chain
[0].ispec()
406 return self
.chain
[-1].ospec()
408 def setup(self
, m
, i
):
409 for (idx
, c
) in enumerate(self
.chain
):
410 if hasattr(c
, "setup"):
411 c
.setup(m
, i
) # stage may have some module stuff
412 if self
.specallocate
:
413 o
= self
.chain
[idx
].ospec() # last assignment survives
414 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
416 o
= c
.process(i
) # store input into "o"
417 if idx
!= len(self
.chain
)-1:
418 if self
.specallocate
:
419 ni
= self
.chain
[idx
+1].ispec() # new input on next loop
420 m
.d
.comb
+= eq(ni
, o
) # assign to next input
424 self
.o
= o
# last loop is the output
426 def process(self
, i
):
427 return self
.o
# conform to Stage API: return last-loop output
431 """ Common functions for Pipeline API
433 def __init__(self
, in_multi
=None, stage_ctl
=False):
434 """ Base class containing ready/valid/data to previous and next stages
436 * p: contains ready/valid to the previous stage
437 * n: contains ready/valid to the next stage
439 Except when calling Controlbase.connect(), user must also:
440 * add i_data member to PrevControl (p) and
441 * add o_data member to NextControl (n)
443 # set up input and output IO ACK (prev/next ready/valid)
444 self
.p
= PrevControl(in_multi
, stage_ctl
)
445 self
.n
= NextControl(stage_ctl
)
447 def connect_to_next(self
, nxt
):
448 """ helper function to connect to the next stage data/valid/ready.
450 return self
.n
.connect_to_next(nxt
.p
)
452 def _connect_in(self
, prev
):
453 """ internal helper function to connect stage to an input source.
454 do not use to connect stage-to-stage!
456 return self
.p
._connect
_in
(prev
.p
)
458 def _connect_out(self
, nxt
):
459 """ internal helper function to connect stage to an output source.
460 do not use to connect stage-to-stage!
462 return self
.n
._connect
_out
(nxt
.n
)
464 def connect(self
, pipechain
):
465 """ connects a chain (list) of Pipeline instances together and
466 links them to this ControlBase instance:
468 in <----> self <---> out
471 [pipe1, pipe2, pipe3, pipe4]
474 out---in out--in out---in
476 Also takes care of allocating i_data/o_data, by looking up
477 the data spec for each end of the pipechain. i.e It is NOT
478 necessary to allocate self.p.i_data or self.n.o_data manually:
479 this is handled AUTOMATICALLY, here.
481 Basically this function is the direct equivalent of StageChain,
482 except that unlike StageChain, the Pipeline logic is followed.
484 Just as StageChain presents an object that conforms to the
485 Stage API from a list of objects that also conform to the
486 Stage API, an object that calls this Pipeline connect function
487 has the exact same pipeline API as the list of pipline objects
490 Thus it becomes possible to build up larger chains recursively.
491 More complex chains (multi-input, multi-output) will have to be
494 eqs
= [] # collated list of assignment statements
496 # connect inter-chain
497 for i
in range(len(pipechain
)-1):
499 pipe2
= pipechain
[i
+1]
500 eqs
+= pipe1
.connect_to_next(pipe2
)
502 # connect front of chain to ourselves
504 self
.p
.i_data
= front
.stage
.ispec()
505 eqs
+= front
._connect
_in
(self
)
507 # connect end of chain to ourselves
509 self
.n
.o_data
= end
.stage
.ospec()
510 eqs
+= end
._connect
_out
(self
)
514 def set_input(self
, i
):
515 """ helper function to set the input data
517 return eq(self
.p
.i_data
, i
)
520 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
521 self
.n
.o_valid
, self
.p
.o_ready
,
523 if hasattr(self
.p
.i_data
, "ports"):
524 res
+= self
.p
.i_data
.ports()
527 if hasattr(self
.n
.o_data
, "ports"):
528 res
+= self
.n
.o_data
.ports()
533 def _elaborate(self
, platform
):
534 """ handles case where stage has dynamic ready/valid functions
537 if not self
.p
.stage_ctl
:
540 # intercept the previous (outgoing) "ready", combine with stage ready
541 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
543 # intercept the next (incoming) "ready" and combine it with data valid
544 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& self
.stage
.d_valid
)
549 class BufferedPipeline(ControlBase
):
550 """ buffered pipeline stage. data and strobe signals travel in sync.
551 if ever the input is ready and the output is not, processed data
552 is shunted in a temporary register.
554 Argument: stage. see Stage API above
556 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
557 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
558 stage-1 p.i_data >>in stage n.o_data out>> stage+1
564 input data p.i_data is read (only), is processed and goes into an
565 intermediate result store [process()]. this is updated combinatorially.
567 in a non-stall condition, the intermediate result will go into the
568 output (update_output). however if ever there is a stall, it goes
569 into r_data instead [update_buffer()].
571 when the non-stall condition is released, r_data is the first
572 to be transferred to the output [flush_buffer()], and the stall
575 on the next cycle (as long as stall is not raised again) the
576 input may begin to be processed and transferred directly to output.
579 def __init__(self
, stage
, stage_ctl
=False, buffermode
=True):
580 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
582 self
.buffermode
= buffermode
584 # set up the input and output data
585 self
.p
.i_data
= stage
.ispec() # input type
586 self
.n
.o_data
= stage
.ospec()
588 def elaborate(self
, platform
):
590 self
.m
= ControlBase
._elaborate
(self
, platform
)
592 result
= self
.stage
.ospec()
594 r_data
= self
.stage
.ospec()
595 if hasattr(self
.stage
, "setup"):
596 self
.stage
.setup(self
.m
, self
.p
.i_data
)
598 # establish some combinatorial temporaries
599 o_n_validn
= Signal(reset_less
=True)
600 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
601 i_p_valid_o_p_ready
= Signal(reset_less
=True)
602 p_i_valid
= Signal(reset_less
=True)
603 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
604 o_n_validn
.eq(~self
.n
.o_valid
),
605 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
606 n_i_ready
.eq(self
.n
.i_ready_test
),
609 # store result of processing in combinatorial temporary
610 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
613 # if not in stall condition, update the temporary register
614 with self
.m
.If(self
.p
.o_ready
): # not stalled
615 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
617 with self
.m
.If(n_i_ready
): # next stage is ready
618 with self
.m
.If(self
.p
._o
_ready
): # not stalled
619 # nothing in buffer: send (processed) input direct to output
620 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
621 eq(self
.n
.o_data
, result
), # update output
624 with self
.m
.Else(): # p.o_ready is false, and data in buffer
625 # Flush the [already processed] buffer to the output port.
626 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
627 eq(self
.n
.o_data
, r_data
), # flush buffer
628 self
.p
._o
_ready
.eq(1), # clear stall
630 # ignore input, since p.o_ready is also false.
632 # (n.i_ready) is false here: next stage is ready
633 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
634 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
635 self
.p
._o
_ready
.eq(1), # Keep the buffer empty
636 eq(self
.n
.o_data
, result
), # set output data
639 # (n.i_ready) false and (n.o_valid) true:
640 with self
.m
.Elif(i_p_valid_o_p_ready
):
641 # If next stage *is* ready, and not stalled yet, accept input
642 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
647 class BufferedPipeline2(ControlBase
):
648 """ buffered pipeline stage. data and strobe signals travel in sync.
649 if ever the input is ready and the output is not, processed data
650 is shunted in a temporary register.
652 Argument: stage. see Stage API above
654 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
655 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
656 stage-1 p.i_data >>in stage n.o_data out>> stage+1
662 input data p.i_data is read (only), is processed and goes into an
663 intermediate result store [process()]. this is updated combinatorially.
665 in a non-stall condition, the intermediate result will go into the
666 output (update_output). however if ever there is a stall, it goes
667 into r_data instead [update_buffer()].
669 when the non-stall condition is released, r_data is the first
670 to be transferred to the output [flush_buffer()], and the stall
673 on the next cycle (as long as stall is not raised again) the
674 input may begin to be processed and transferred directly to output.
677 def __init__(self
, stage
, stage_ctl
=False):
678 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
681 # set up the input and output data
682 self
.p
.i_data
= stage
.ispec() # input type
683 self
.n
.o_data
= stage
.ospec()
685 def elaborate(self
, platform
):
687 self
.m
= ControlBase
._elaborate
(self
, platform
)
689 result
= self
.stage
.ospec()
690 if hasattr(self
.stage
, "setup"):
691 self
.stage
.setup(self
.m
, self
.p
.i_data
)
693 # establish some combinatorial temporaries
694 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
695 p_i_valid_p_o_ready
= Signal(reset_less
=True)
696 p_i_valid
= Signal(reset_less
=True)
697 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
698 n_i_ready
.eq(self
.n
.i_ready_test
),
699 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
702 # store result of processing in combinatorial temporary
703 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
705 # previous valid and ready
706 with self
.m
.If(p_i_valid_p_o_ready
):
707 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # output valid
708 eq(self
.n
.o_data
, result
), # update output
710 # previous invalid or not ready, however next is accepting
711 with self
.m
.Elif(n_i_ready
):
712 # TODO: could still send data here (if there was any)
713 self
.m
.d
.sync
+= self
.n
.o_valid
.eq(0), # ...so set output invalid
715 # if next is ready, so is previous
716 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
721 class UnbufferedPipeline(ControlBase
):
722 """ A simple pipeline stage with single-clock synchronisation
723 and two-way valid/ready synchronised signalling.
725 Note that a stall in one stage will result in the entire pipeline
728 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
729 travel synchronously with the data: the valid/ready signalling
730 combines in a *combinatorial* fashion. Therefore, a long pipeline
731 chain will lengthen propagation delays.
733 Argument: stage. see Stage API, above
735 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
736 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
737 stage-1 p.i_data >>in stage n.o_data out>> stage+1
745 p.i_data : StageInput, shaped according to ispec
747 p.o_data : StageOutput, shaped according to ospec
749 r_data : input_shape according to ispec
750 A temporary (buffered) copy of a prior (valid) input.
751 This is HELD if the output is not ready. It is updated
753 result: output_shape according to ospec
754 The output of the combinatorial logic. it is updated
755 COMBINATORIALLY (no clock dependence).
758 def __init__(self
, stage
, stage_ctl
=False):
759 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
762 # set up the input and output data
763 self
.p
.i_data
= stage
.ispec() # input type
764 self
.n
.o_data
= stage
.ospec() # output type
766 def elaborate(self
, platform
):
767 self
.m
= ControlBase
._elaborate
(self
, platform
)
769 data_valid
= Signal() # is data valid or not
770 r_data
= self
.stage
.ispec() # input type
771 if hasattr(self
.stage
, "setup"):
772 self
.stage
.setup(self
.m
, r_data
)
775 p_i_valid
= Signal(reset_less
=True)
776 pv
= Signal(reset_less
=True)
777 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
778 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
780 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
781 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
782 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
783 (~self
.n
.i_ready_test
& data_valid
))
785 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
786 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
790 class UnbufferedPipeline2(ControlBase
):
791 """ A simple pipeline stage with single-clock synchronisation
792 and two-way valid/ready synchronised signalling.
794 Note that a stall in one stage will result in the entire pipeline
797 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
798 travel synchronously with the data: the valid/ready signalling
799 combines in a *combinatorial* fashion. Therefore, a long pipeline
800 chain will lengthen propagation delays.
802 Argument: stage. see Stage API, above
804 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
805 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
806 stage-1 p.i_data >>in stage n.o_data out>> stage+1
814 p.i_data : StageInput, shaped according to ispec
816 p.o_data : StageOutput, shaped according to ospec
818 buf : output_shape according to ospec
819 A temporary (buffered) copy of a valid output
820 This is HELD if the output is not ready. It is updated
824 def __init__(self
, stage
, stage_ctl
=False):
825 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
828 # set up the input and output data
829 self
.p
.i_data
= stage
.ispec() # input type
830 self
.n
.o_data
= stage
.ospec() # output type
832 def elaborate(self
, platform
):
833 self
.m
= ControlBase
._elaborate
(self
, platform
)
835 buf_full
= Signal() # is data valid or not
836 buf
= self
.stage
.ospec() # output type
837 if hasattr(self
.stage
, "setup"):
838 self
.stage
.setup(self
.m
, self
.p
.i_data
)
841 p_i_valid
= Signal(reset_less
=True)
842 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
844 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
845 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
846 self
.m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& \
847 (p_i_valid | buf_full
))
848 with self
.m
.If(buf_full
):
849 self
.m
.d
.comb
+= eq(self
.n
.o_data
, buf
)
851 self
.m
.d
.comb
+= eq(self
.n
.o_data
,
852 self
.stage
.process(self
.p
.i_data
))
853 self
.m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
858 class PassThroughStage(StageCls
):
859 """ a pass-through stage which has its input data spec equal to its output,
860 and "passes through" its data from input to output.
862 def __init__(self
, iospecfn
):
863 self
.iospecfn
= iospecfn
864 def ispec(self
): return self
.iospecfn()
865 def ospec(self
): return self
.iospecfn()
866 def process(self
, i
): return i
869 class RegisterPipeline(UnbufferedPipeline
):
870 """ A pipeline stage that delays by one clock cycle, creating a
871 sync'd latch out of o_data and o_valid as an indirect byproduct
872 of using PassThroughStage
874 def __init__(self
, iospecfn
):
875 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))