1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
155 Synchronised pipeline, Based on:
156 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
159 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
160 from nmigen
.cli
import verilog
, rtlil
161 from nmigen
.hdl
.ast
import ArrayProxy
162 from nmigen
.hdl
.rec
import Record
, Layout
164 from abc
import ABCMeta
, abstractmethod
165 from collections
.abc
import Sequence
169 """ contains signals that come *from* the previous stage (both in and out)
170 * i_valid: previous stage indicating all incoming data is valid.
171 may be a multi-bit signal, where all bits are required
172 to be asserted to indicate "valid".
173 * o_ready: output to next stage indicating readiness to accept data
174 * i_data : an input - added by the user of this class
177 def __init__(self
, i_width
=1, stage_ctl
=False):
178 self
.stage_ctl
= stage_ctl
179 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
180 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
181 self
.i_data
= None # XXX MUST BE ADDED BY USER
183 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
187 """ public-facing API: indicates (externally) that stage is ready
190 return self
.s_o_ready
# set dynamically by stage
191 return self
._o
_ready
# return this when not under dynamic control
193 def _connect_in(self
, prev
):
194 """ internal helper function to connect stage to an input source.
195 do not use to connect stage-to-stage!
197 return [self
.i_valid
.eq(prev
.i_valid_test
),
198 prev
.o_ready
.eq(self
.o_ready
),
199 eq(self
.i_data
, prev
.i_data
),
203 def i_valid_test(self
):
204 vlen
= len(self
.i_valid
)
206 # multi-bit case: valid only when i_valid is all 1s
207 all1s
= Const(-1, (len(self
.i_valid
), False))
208 i_valid
= (self
.i_valid
== all1s
)
210 # single-bit i_valid case
211 i_valid
= self
.i_valid
213 # when stage indicates not ready, incoming data
214 # must "appear" to be not ready too
216 i_valid
= i_valid
& self
.s_o_ready
222 """ contains the signals that go *to* the next stage (both in and out)
223 * o_valid: output indicating to next stage that data is valid
224 * i_ready: input from next stage indicating that it can accept data
225 * o_data : an output - added by the user of this class
227 def __init__(self
, stage_ctl
=False):
228 self
.stage_ctl
= stage_ctl
229 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
230 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
231 self
.o_data
= None # XXX MUST BE ADDED BY USER
233 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
236 def i_ready_test(self
):
238 return self
.i_ready
& self
.d_valid
241 def connect_to_next(self
, nxt
):
242 """ helper function to connect to the next stage data/valid/ready.
243 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
244 use this when connecting stage-to-stage
246 return [nxt
.i_valid
.eq(self
.o_valid
),
247 self
.i_ready
.eq(nxt
.o_ready
),
248 eq(nxt
.i_data
, self
.o_data
),
251 def _connect_out(self
, nxt
):
252 """ internal helper function to connect stage to an output source.
253 do not use to connect stage-to-stage!
255 return [nxt
.o_valid
.eq(self
.o_valid
),
256 self
.i_ready
.eq(nxt
.i_ready_test
),
257 eq(nxt
.o_data
, self
.o_data
),
262 """ makes signals equal: a helper routine which identifies if it is being
263 passed a list (or tuple) of objects, or signals, or Records, and calls
264 the objects' eq function.
266 complex objects (classes) can be used: they must follow the
267 convention of having an eq member function, which takes the
268 responsibility of further calling eq and returning a list of
271 Record is a special (unusual, recursive) case, where the input may be
272 specified as a dictionary (which may contain further dictionaries,
273 recursively), where the field names of the dictionary must match
274 the Record's field spec. Alternatively, an object with the same
275 member names as the Record may be assigned: it does not have to
278 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
279 has an eq function, the object being assigned to it (e.g. a python
280 object) might not. despite the *input* having an eq function,
281 that doesn't help us, because it's the *ArrayProxy* that's being
282 assigned to. so.... we cheat. use the ports() function of the
283 python object, enumerate them, find out the list of Signals that way,
287 if isinstance(o
, dict):
288 for (k
, v
) in o
.items():
289 print ("d-eq", v
, i
[k
])
290 res
.append(v
.eq(i
[k
]))
293 if not isinstance(o
, Sequence
):
295 for (ao
, ai
) in zip(o
, i
):
296 #print ("eq", ao, ai)
297 if isinstance(ao
, Record
):
298 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
299 if isinstance(field_shape
, Layout
):
303 if hasattr(val
, field_name
): # check for attribute
304 val
= getattr(val
, field_name
)
306 val
= val
[field_name
] # dictionary-style specification
307 rres
= eq(ao
.fields
[field_name
], val
)
309 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
311 op
= getattr(ao
, p
.name
)
312 #print (op, p, p.name)
314 if not isinstance(rres
, Sequence
):
319 if not isinstance(rres
, Sequence
):
325 class StageCls(metaclass
=ABCMeta
):
326 """ Class-based "Stage" API. requires instantiation (after derivation)
328 see "Stage API" above.. Note: python does *not* require derivation
329 from this class. All that is required is that the pipelines *have*
330 the functions listed in this class. Derivation from this class
331 is therefore merely a "courtesy" to maintainers.
334 def ispec(self
): pass # REQUIRED
336 def ospec(self
): pass # REQUIRED
338 #def setup(self, m, i): pass # OPTIONAL
340 def process(self
, i
): pass # REQUIRED
343 class Stage(metaclass
=ABCMeta
):
344 """ Static "Stage" API. does not require instantiation (after derivation)
346 see "Stage API" above. Note: python does *not* require derivation
347 from this class. All that is required is that the pipelines *have*
348 the functions listed in this class. Derivation from this class
349 is therefore merely a "courtesy" to maintainers.
361 #def setup(m, i): pass
368 class RecordBasedStage(Stage
):
369 """ convenience class which provides a Records-based layout.
370 honestly it's a lot easier just to create a direct Records-based
371 class (see ExampleAddRecordStage)
373 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
374 self
.in_shape
= in_shape
375 self
.out_shape
= out_shape
376 self
.__process
= processfn
377 self
.__setup
= setupfn
378 def ispec(self
): return Record(self
.in_shape
)
379 def ospec(self
): return Record(self
.out_shape
)
380 def process(seif
, i
): return self
.__process
(i
)
381 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
384 class StageChain(StageCls
):
385 """ pass in a list of stages, and they will automatically be
386 chained together via their input and output specs into a
389 the end result basically conforms to the exact same Stage API.
391 * input to this class will be the input of the first stage
392 * output of first stage goes into input of second
393 * output of second goes into input into third (etc. etc.)
394 * the output of this class will be the output of the last stage
396 def __init__(self
, chain
, specallocate
=False):
398 self
.specallocate
= specallocate
401 return self
.chain
[0].ispec()
404 return self
.chain
[-1].ospec()
406 def setup(self
, m
, i
):
407 for (idx
, c
) in enumerate(self
.chain
):
408 if hasattr(c
, "setup"):
409 c
.setup(m
, i
) # stage may have some module stuff
410 if self
.specallocate
:
411 o
= self
.chain
[idx
].ospec() # last assignment survives
412 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
414 o
= c
.process(i
) # store input into "o"
415 if idx
!= len(self
.chain
)-1:
416 if self
.specallocate
:
417 ni
= self
.chain
[idx
+1].ispec() # new input on next loop
418 m
.d
.comb
+= eq(ni
, o
) # assign to next input
422 self
.o
= o
# last loop is the output
424 def process(self
, i
):
425 return self
.o
# conform to Stage API: return last-loop output
429 """ Common functions for Pipeline API
431 def __init__(self
, in_multi
=None, stage_ctl
=False):
432 """ Base class containing ready/valid/data to previous and next stages
434 * p: contains ready/valid to the previous stage
435 * n: contains ready/valid to the next stage
437 Except when calling Controlbase.connect(), user must also:
438 * add i_data member to PrevControl (p) and
439 * add o_data member to NextControl (n)
441 # set up input and output IO ACK (prev/next ready/valid)
442 self
.p
= PrevControl(in_multi
, stage_ctl
)
443 self
.n
= NextControl(stage_ctl
)
445 def connect_to_next(self
, nxt
):
446 """ helper function to connect to the next stage data/valid/ready.
448 return self
.n
.connect_to_next(nxt
.p
)
450 def _connect_in(self
, prev
):
451 """ internal helper function to connect stage to an input source.
452 do not use to connect stage-to-stage!
454 return self
.p
._connect
_in
(prev
.p
)
456 def _connect_out(self
, nxt
):
457 """ internal helper function to connect stage to an output source.
458 do not use to connect stage-to-stage!
460 return self
.n
._connect
_out
(nxt
.n
)
462 def connect(self
, pipechain
):
463 """ connects a chain (list) of Pipeline instances together and
464 links them to this ControlBase instance:
466 in <----> self <---> out
469 [pipe1, pipe2, pipe3, pipe4]
472 out---in out--in out---in
474 Also takes care of allocating i_data/o_data, by looking up
475 the data spec for each end of the pipechain. i.e It is NOT
476 necessary to allocate self.p.i_data or self.n.o_data manually:
477 this is handled AUTOMATICALLY, here.
479 Basically this function is the direct equivalent of StageChain,
480 except that unlike StageChain, the Pipeline logic is followed.
482 Just as StageChain presents an object that conforms to the
483 Stage API from a list of objects that also conform to the
484 Stage API, an object that calls this Pipeline connect function
485 has the exact same pipeline API as the list of pipline objects
488 Thus it becomes possible to build up larger chains recursively.
489 More complex chains (multi-input, multi-output) will have to be
492 eqs
= [] # collated list of assignment statements
494 # connect inter-chain
495 for i
in range(len(pipechain
)-1):
497 pipe2
= pipechain
[i
+1]
498 eqs
+= pipe1
.connect_to_next(pipe2
)
500 # connect front of chain to ourselves
502 self
.p
.i_data
= front
.stage
.ispec()
503 eqs
+= front
._connect
_in
(self
)
505 # connect end of chain to ourselves
507 self
.n
.o_data
= end
.stage
.ospec()
508 eqs
+= end
._connect
_out
(self
)
512 def set_input(self
, i
):
513 """ helper function to set the input data
515 return eq(self
.p
.i_data
, i
)
518 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
519 self
.n
.o_valid
, self
.p
.o_ready
,
521 if hasattr(self
.p
.i_data
, "ports"):
522 res
+= self
.p
.i_data
.ports()
525 if hasattr(self
.n
.o_data
, "ports"):
526 res
+= self
.n
.o_data
.ports()
531 def _elaborate(self
, platform
):
532 """ handles case where stage has dynamic ready/valid functions
535 if not self
.p
.stage_ctl
:
538 # intercept the previous (outgoing) "ready", combine with stage ready
539 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
541 # intercept the next (incoming) "ready" and combine it with data valid
542 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
543 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
548 class BufferedPipeline(ControlBase
):
549 """ buffered pipeline stage. data and strobe signals travel in sync.
550 if ever the input is ready and the output is not, processed data
551 is shunted in a temporary register.
553 Argument: stage. see Stage API above
555 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
556 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
557 stage-1 p.i_data >>in stage n.o_data out>> stage+1
563 input data p.i_data is read (only), is processed and goes into an
564 intermediate result store [process()]. this is updated combinatorially.
566 in a non-stall condition, the intermediate result will go into the
567 output (update_output). however if ever there is a stall, it goes
568 into r_data instead [update_buffer()].
570 when the non-stall condition is released, r_data is the first
571 to be transferred to the output [flush_buffer()], and the stall
574 on the next cycle (as long as stall is not raised again) the
575 input may begin to be processed and transferred directly to output.
578 def __init__(self
, stage
, stage_ctl
=False):
579 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
582 # set up the input and output data
583 self
.p
.i_data
= stage
.ispec() # input type
584 self
.n
.o_data
= stage
.ospec()
586 def elaborate(self
, platform
):
588 self
.m
= ControlBase
._elaborate
(self
, platform
)
590 result
= self
.stage
.ospec()
591 r_data
= self
.stage
.ospec()
592 if hasattr(self
.stage
, "setup"):
593 self
.stage
.setup(self
.m
, self
.p
.i_data
)
595 # establish some combinatorial temporaries
596 o_n_validn
= Signal(reset_less
=True)
597 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
598 i_p_valid_o_p_ready
= Signal(reset_less
=True)
599 p_i_valid
= Signal(reset_less
=True)
600 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
601 o_n_validn
.eq(~self
.n
.o_valid
),
602 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
603 n_i_ready
.eq(self
.n
.i_ready_test
),
606 # store result of processing in combinatorial temporary
607 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
609 # if not in stall condition, update the temporary register
610 with self
.m
.If(self
.p
.o_ready
): # not stalled
611 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
613 with self
.m
.If(n_i_ready
): # next stage is ready
614 with self
.m
.If(self
.p
._o
_ready
): # not stalled
615 # nothing in buffer: send (processed) input direct to output
616 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
617 eq(self
.n
.o_data
, result
), # update output
619 with self
.m
.Else(): # p.o_ready is false, and data in buffer
620 # Flush the [already processed] buffer to the output port.
621 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
622 eq(self
.n
.o_data
, r_data
), # flush buffer
623 self
.p
._o
_ready
.eq(1), # clear stall
625 # ignore input, since p.o_ready is also false.
627 # (n.i_ready) is false here: next stage is ready
628 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
629 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
630 self
.p
._o
_ready
.eq(1), # Keep the buffer empty
631 eq(self
.n
.o_data
, result
), # set output data
634 # (n.i_ready) false and (n.o_valid) true:
635 with self
.m
.Elif(i_p_valid_o_p_ready
):
636 # If next stage *is* ready, and not stalled yet, accept input
637 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
642 class SimpleHandshake(ControlBase
):
643 """ simple handshake control. data and strobe signals travel in sync.
644 implements the protocol used by Wishbone and AXI4.
646 Argument: stage. see Stage API above
648 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
649 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
650 stage-1 p.i_data >>in stage n.o_data out>> stage+1
654 def __init__(self
, stage
, stage_ctl
=False):
655 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
658 # set up the input and output data
659 self
.p
.i_data
= stage
.ispec() # input type
660 self
.n
.o_data
= stage
.ospec()
662 def elaborate(self
, platform
):
664 self
.m
= ControlBase
._elaborate
(self
, platform
)
667 result
= self
.stage
.ospec()
668 if hasattr(self
.stage
, "setup"):
669 self
.stage
.setup(self
.m
, self
.p
.i_data
)
671 # establish some combinatorial temporaries
672 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
673 p_i_valid_p_o_ready
= Signal(reset_less
=True)
674 p_i_valid
= Signal(reset_less
=True)
675 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
676 n_i_ready
.eq(self
.n
.i_ready_test
),
677 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
680 # store result of processing in combinatorial temporary
681 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
683 # previous valid and ready
684 with self
.m
.If(p_i_valid_p_o_ready
):
685 self
.m
.d
.sync
+= [r_busy
.eq(1), # output valid
686 #self.n.o_valid.eq(1), # output valid
687 eq(self
.n
.o_data
, result
), # update output
689 # previous invalid or not ready, however next is accepting
690 with self
.m
.Elif(n_i_ready
):
691 self
.m
.d
.sync
+= [ eq(self
.n
.o_data
, result
)]
692 # TODO: could still send data here (if there was any)
693 #self.m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
694 self
.m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
696 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
697 # if next is ready, so is previous
698 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
703 class UnbufferedPipeline(ControlBase
):
704 """ A simple pipeline stage with single-clock synchronisation
705 and two-way valid/ready synchronised signalling.
707 Note that a stall in one stage will result in the entire pipeline
710 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
711 travel synchronously with the data: the valid/ready signalling
712 combines in a *combinatorial* fashion. Therefore, a long pipeline
713 chain will lengthen propagation delays.
715 Argument: stage. see Stage API, above
717 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
718 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
719 stage-1 p.i_data >>in stage n.o_data out>> stage+1
727 p.i_data : StageInput, shaped according to ispec
729 p.o_data : StageOutput, shaped according to ospec
731 r_data : input_shape according to ispec
732 A temporary (buffered) copy of a prior (valid) input.
733 This is HELD if the output is not ready. It is updated
735 result: output_shape according to ospec
736 The output of the combinatorial logic. it is updated
737 COMBINATORIALLY (no clock dependence).
740 def __init__(self
, stage
, stage_ctl
=False):
741 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
744 # set up the input and output data
745 self
.p
.i_data
= stage
.ispec() # input type
746 self
.n
.o_data
= stage
.ospec() # output type
748 def elaborate(self
, platform
):
749 self
.m
= ControlBase
._elaborate
(self
, platform
)
751 data_valid
= Signal() # is data valid or not
752 r_data
= self
.stage
.ispec() # input type
753 if hasattr(self
.stage
, "setup"):
754 self
.stage
.setup(self
.m
, r_data
)
757 p_i_valid
= Signal(reset_less
=True)
758 pv
= Signal(reset_less
=True)
759 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
760 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
762 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
763 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
764 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
765 (~self
.n
.i_ready_test
& data_valid
))
767 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
768 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
772 class UnbufferedPipeline2(ControlBase
):
773 """ A simple pipeline stage with single-clock synchronisation
774 and two-way valid/ready synchronised signalling.
776 Note that a stall in one stage will result in the entire pipeline
779 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
780 travel synchronously with the data: the valid/ready signalling
781 combines in a *combinatorial* fashion. Therefore, a long pipeline
782 chain will lengthen propagation delays.
784 Argument: stage. see Stage API, above
786 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
787 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
788 stage-1 p.i_data >>in stage n.o_data out>> stage+1
796 p.i_data : StageInput, shaped according to ispec
798 p.o_data : StageOutput, shaped according to ospec
800 buf : output_shape according to ospec
801 A temporary (buffered) copy of a valid output
802 This is HELD if the output is not ready. It is updated
806 def __init__(self
, stage
, stage_ctl
=False):
807 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
810 # set up the input and output data
811 self
.p
.i_data
= stage
.ispec() # input type
812 self
.n
.o_data
= stage
.ospec() # output type
814 def elaborate(self
, platform
):
815 self
.m
= ControlBase
._elaborate
(self
, platform
)
817 buf_full
= Signal() # is data valid or not
818 buf
= self
.stage
.ospec() # output type
819 if hasattr(self
.stage
, "setup"):
820 self
.stage
.setup(self
.m
, self
.p
.i_data
)
823 p_i_valid
= Signal(reset_less
=True)
824 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
826 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
827 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
828 self
.m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
830 odata
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
831 self
.m
.d
.comb
+= eq(self
.n
.o_data
, odata
)
832 self
.m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
837 class PassThroughStage(StageCls
):
838 """ a pass-through stage which has its input data spec equal to its output,
839 and "passes through" its data from input to output.
841 def __init__(self
, iospecfn
):
842 self
.iospecfn
= iospecfn
843 def ispec(self
): return self
.iospecfn()
844 def ospec(self
): return self
.iospecfn()
845 def process(self
, i
): return i
848 class RegisterPipeline(UnbufferedPipeline
):
849 """ A pipeline stage that delays by one clock cycle, creating a
850 sync'd latch out of o_data and o_valid as an indirect byproduct
851 of using PassThroughStage
853 def __init__(self
, iospecfn
):
854 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))