1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedHandshake). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedHandshake by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A Control class that introduces a single clock delay, passing its
102 data through unaltered. Unlike RegisterPipeline (which relies
103 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
109 A convenience class that, because UnbufferedPipeline introduces a single
110 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
111 stage that, duh, delays its (unmodified) input by one clock cycle.
116 nmigen implementation of buffered pipeline stage, based on zipcpu:
117 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
119 this module requires quite a bit of thought to understand how it works
120 (and why it is needed in the first place). reading the above is
121 *strongly* recommended.
123 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
124 the STB / ACK signals to raise and lower (on separate clocks) before
125 data may proceeed (thus only allowing one piece of data to proceed
126 on *ALTERNATE* cycles), the signalling here is a true pipeline
127 where data will flow on *every* clock when the conditions are right.
129 input acceptance conditions are when:
130 * incoming previous-stage strobe (p.i_valid) is HIGH
131 * outgoing previous-stage ready (p.o_ready) is LOW
133 output transmission conditions are when:
134 * outgoing next-stage strobe (n.o_valid) is HIGH
135 * outgoing next-stage ready (n.i_ready) is LOW
137 the tricky bit is when the input has valid data and the output is not
138 ready to accept it. if it wasn't for the clock synchronisation, it
139 would be possible to tell the input "hey don't send that data, we're
140 not ready". unfortunately, it's not possible to "change the past":
141 the previous stage *has no choice* but to pass on its data.
143 therefore, the incoming data *must* be accepted - and stored: that
144 is the responsibility / contract that this stage *must* accept.
145 on the same clock, it's possible to tell the input that it must
146 not send any more data. this is the "stall" condition.
148 we now effectively have *two* possible pieces of data to "choose" from:
149 the buffered data, and the incoming data. the decision as to which
150 to process and output is based on whether we are in "stall" or not.
151 i.e. when the next stage is no longer ready, the output comes from
152 the buffer if a stall had previously occurred, otherwise it comes
153 direct from processing the input.
155 this allows us to respect a synchronous "travelling STB" with what
156 dan calls a "buffered handshake".
158 it's quite a complex state machine!
163 Synchronised pipeline, Based on:
164 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
167 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
168 from nmigen
.cli
import verilog
, rtlil
169 from nmigen
.lib
.fifo
import SyncFIFO
170 from nmigen
.hdl
.ast
import ArrayProxy
171 from nmigen
.hdl
.rec
import Record
, Layout
173 from abc
import ABCMeta
, abstractmethod
174 from collections
.abc
import Sequence
178 """ contains signals that come *from* the previous stage (both in and out)
179 * i_valid: previous stage indicating all incoming data is valid.
180 may be a multi-bit signal, where all bits are required
181 to be asserted to indicate "valid".
182 * o_ready: output to next stage indicating readiness to accept data
183 * i_data : an input - added by the user of this class
186 def __init__(self
, i_width
=1, stage_ctl
=False):
187 self
.stage_ctl
= stage_ctl
188 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
189 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
190 self
.i_data
= None # XXX MUST BE ADDED BY USER
192 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
196 """ public-facing API: indicates (externally) that stage is ready
199 return self
.s_o_ready
# set dynamically by stage
200 return self
._o
_ready
# return this when not under dynamic control
202 def _connect_in(self
, prev
, direct
=False):
203 """ internal helper function to connect stage to an input source.
204 do not use to connect stage-to-stage!
207 i_valid
= prev
.i_valid
209 i_valid
= prev
.i_valid_test
210 return [self
.i_valid
.eq(i_valid
),
211 prev
.o_ready
.eq(self
.o_ready
),
212 eq(self
.i_data
, prev
.i_data
),
216 def i_valid_test(self
):
217 vlen
= len(self
.i_valid
)
219 # multi-bit case: valid only when i_valid is all 1s
220 all1s
= Const(-1, (len(self
.i_valid
), False))
221 i_valid
= (self
.i_valid
== all1s
)
223 # single-bit i_valid case
224 i_valid
= self
.i_valid
226 # when stage indicates not ready, incoming data
227 # must "appear" to be not ready too
229 i_valid
= i_valid
& self
.s_o_ready
235 """ contains the signals that go *to* the next stage (both in and out)
236 * o_valid: output indicating to next stage that data is valid
237 * i_ready: input from next stage indicating that it can accept data
238 * o_data : an output - added by the user of this class
240 def __init__(self
, stage_ctl
=False):
241 self
.stage_ctl
= stage_ctl
242 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
243 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
244 self
.o_data
= None # XXX MUST BE ADDED BY USER
246 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
249 def i_ready_test(self
):
251 return self
.i_ready
& self
.d_valid
254 def connect_to_next(self
, nxt
):
255 """ helper function to connect to the next stage data/valid/ready.
256 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
257 use this when connecting stage-to-stage
259 return [nxt
.i_valid
.eq(self
.o_valid
),
260 self
.i_ready
.eq(nxt
.o_ready
),
261 eq(nxt
.i_data
, self
.o_data
),
264 def _connect_out(self
, nxt
, direct
=False):
265 """ internal helper function to connect stage to an output source.
266 do not use to connect stage-to-stage!
269 i_ready
= nxt
.i_ready
271 i_ready
= nxt
.i_ready_test
272 return [nxt
.o_valid
.eq(self
.o_valid
),
273 self
.i_ready
.eq(i_ready
),
274 eq(nxt
.o_data
, self
.o_data
),
279 """ a helper routine which identifies if it is being passed a list
280 (or tuple) of objects, or signals, or Records, and calls
283 the visiting fn is called when an object is identified.
285 Record is a special (unusual, recursive) case, where the input may be
286 specified as a dictionary (which may contain further dictionaries,
287 recursively), where the field names of the dictionary must match
288 the Record's field spec. Alternatively, an object with the same
289 member names as the Record may be assigned: it does not have to
292 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
293 has an eq function, the object being assigned to it (e.g. a python
294 object) might not. despite the *input* having an eq function,
295 that doesn't help us, because it's the *ArrayProxy* that's being
296 assigned to. so.... we cheat. use the ports() function of the
297 python object, enumerate them, find out the list of Signals that way,
300 def visit(self
, o
, i
, fn
):
302 if isinstance(o
, dict):
303 for (k
, v
) in o
.items():
304 print ("d-eq", v
, i
[k
])
305 res
.append(fn(v
, i
[k
]))
308 if not isinstance(o
, Sequence
):
310 for (ao
, ai
) in zip(o
, i
):
311 #print ("visit", fn, ao, ai)
312 if isinstance(ao
, Record
):
314 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
315 if isinstance(field_shape
, Layout
):
319 if hasattr(val
, field_name
): # check for attribute
320 val
= getattr(val
, field_name
)
322 val
= val
[field_name
] # dictionary-style specification
323 rres
+= self
.visit(ao
.fields
[field_name
], val
, fn
)
324 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
327 op
= getattr(ao
, p
.name
)
328 #print (op, p, p.name)
329 rres
.append(fn(op
, p
))
332 if not isinstance(rres
, Sequence
):
341 def __call__(self
, o
, i
):
344 res
= self
.visit(o
, i
, _eq_fn
)
348 """ makes signals equal: a helper routine which identifies if it is being
349 passed a list (or tuple) of objects, or signals, or Records, and calls
350 the objects' eq function.
355 class StageCls(metaclass
=ABCMeta
):
356 """ Class-based "Stage" API. requires instantiation (after derivation)
358 see "Stage API" above.. Note: python does *not* require derivation
359 from this class. All that is required is that the pipelines *have*
360 the functions listed in this class. Derivation from this class
361 is therefore merely a "courtesy" to maintainers.
364 def ispec(self
): pass # REQUIRED
366 def ospec(self
): pass # REQUIRED
368 #def setup(self, m, i): pass # OPTIONAL
370 def process(self
, i
): pass # REQUIRED
373 class Stage(metaclass
=ABCMeta
):
374 """ Static "Stage" API. does not require instantiation (after derivation)
376 see "Stage API" above. Note: python does *not* require derivation
377 from this class. All that is required is that the pipelines *have*
378 the functions listed in this class. Derivation from this class
379 is therefore merely a "courtesy" to maintainers.
391 #def setup(m, i): pass
398 class RecordBasedStage(Stage
):
399 """ convenience class which provides a Records-based layout.
400 honestly it's a lot easier just to create a direct Records-based
401 class (see ExampleAddRecordStage)
403 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
404 self
.in_shape
= in_shape
405 self
.out_shape
= out_shape
406 self
.__process
= processfn
407 self
.__setup
= setupfn
408 def ispec(self
): return Record(self
.in_shape
)
409 def ospec(self
): return Record(self
.out_shape
)
410 def process(seif
, i
): return self
.__process
(i
)
411 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
414 class StageChain(StageCls
):
415 """ pass in a list of stages, and they will automatically be
416 chained together via their input and output specs into a
419 the end result basically conforms to the exact same Stage API.
421 * input to this class will be the input of the first stage
422 * output of first stage goes into input of second
423 * output of second goes into input into third (etc. etc.)
424 * the output of this class will be the output of the last stage
426 def __init__(self
, chain
, specallocate
=False):
428 self
.specallocate
= specallocate
431 return self
.chain
[0].ispec()
434 return self
.chain
[-1].ospec()
436 def _specallocate_setup(self
, m
, i
):
437 for (idx
, c
) in enumerate(self
.chain
):
438 if hasattr(c
, "setup"):
439 c
.setup(m
, i
) # stage may have some module stuff
440 o
= self
.chain
[idx
].ospec() # last assignment survives
441 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
442 if idx
== len(self
.chain
)-1:
444 i
= self
.chain
[idx
+1].ispec() # new input on next loop
445 m
.d
.comb
+= eq(i
, o
) # assign to next input
446 return o
# last loop is the output
448 def _noallocate_setup(self
, m
, i
):
449 for (idx
, c
) in enumerate(self
.chain
):
450 if hasattr(c
, "setup"):
451 c
.setup(m
, i
) # stage may have some module stuff
452 i
= o
= c
.process(i
) # store input into "o"
453 return o
# last loop is the output
455 def setup(self
, m
, i
):
456 if self
.specallocate
:
457 self
.o
= self
._specallocate
_setup
(m
, i
)
459 self
.o
= self
._noallocate
_setup
(m
, i
)
461 def process(self
, i
):
462 return self
.o
# conform to Stage API: return last-loop output
466 """ Common functions for Pipeline API
468 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
469 """ Base class containing ready/valid/data to previous and next stages
471 * p: contains ready/valid to the previous stage
472 * n: contains ready/valid to the next stage
474 Except when calling Controlbase.connect(), user must also:
475 * add i_data member to PrevControl (p) and
476 * add o_data member to NextControl (n)
480 # set up input and output IO ACK (prev/next ready/valid)
481 self
.p
= PrevControl(in_multi
, stage_ctl
)
482 self
.n
= NextControl(stage_ctl
)
484 # set up the input and output data
485 if stage
is not None:
486 self
.p
.i_data
= stage
.ispec() # input type
487 self
.n
.o_data
= stage
.ospec()
489 def connect_to_next(self
, nxt
):
490 """ helper function to connect to the next stage data/valid/ready.
492 return self
.n
.connect_to_next(nxt
.p
)
494 def _connect_in(self
, prev
):
495 """ internal helper function to connect stage to an input source.
496 do not use to connect stage-to-stage!
498 return self
.p
._connect
_in
(prev
.p
)
500 def _connect_out(self
, nxt
):
501 """ internal helper function to connect stage to an output source.
502 do not use to connect stage-to-stage!
504 return self
.n
._connect
_out
(nxt
.n
)
506 def connect(self
, pipechain
):
507 """ connects a chain (list) of Pipeline instances together and
508 links them to this ControlBase instance:
510 in <----> self <---> out
513 [pipe1, pipe2, pipe3, pipe4]
516 out---in out--in out---in
518 Also takes care of allocating i_data/o_data, by looking up
519 the data spec for each end of the pipechain. i.e It is NOT
520 necessary to allocate self.p.i_data or self.n.o_data manually:
521 this is handled AUTOMATICALLY, here.
523 Basically this function is the direct equivalent of StageChain,
524 except that unlike StageChain, the Pipeline logic is followed.
526 Just as StageChain presents an object that conforms to the
527 Stage API from a list of objects that also conform to the
528 Stage API, an object that calls this Pipeline connect function
529 has the exact same pipeline API as the list of pipline objects
532 Thus it becomes possible to build up larger chains recursively.
533 More complex chains (multi-input, multi-output) will have to be
536 eqs
= [] # collated list of assignment statements
538 # connect inter-chain
539 for i
in range(len(pipechain
)-1):
541 pipe2
= pipechain
[i
+1]
542 eqs
+= pipe1
.connect_to_next(pipe2
)
544 # connect front of chain to ourselves
546 self
.p
.i_data
= front
.stage
.ispec()
547 eqs
+= front
._connect
_in
(self
)
549 # connect end of chain to ourselves
551 self
.n
.o_data
= end
.stage
.ospec()
552 eqs
+= end
._connect
_out
(self
)
556 def set_input(self
, i
):
557 """ helper function to set the input data
559 return eq(self
.p
.i_data
, i
)
562 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
563 self
.n
.o_valid
, self
.p
.o_ready
,
565 if hasattr(self
.p
.i_data
, "ports"):
566 res
+= self
.p
.i_data
.ports()
569 if hasattr(self
.n
.o_data
, "ports"):
570 res
+= self
.n
.o_data
.ports()
575 def _elaborate(self
, platform
):
576 """ handles case where stage has dynamic ready/valid functions
580 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
581 self
.stage
.setup(m
, self
.p
.i_data
)
583 if not self
.p
.stage_ctl
:
586 # intercept the previous (outgoing) "ready", combine with stage ready
587 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
589 # intercept the next (incoming) "ready" and combine it with data valid
590 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
591 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
596 class BufferedHandshake(ControlBase
):
597 """ buffered pipeline stage. data and strobe signals travel in sync.
598 if ever the input is ready and the output is not, processed data
599 is shunted in a temporary register.
601 Argument: stage. see Stage API above
603 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
604 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
605 stage-1 p.i_data >>in stage n.o_data out>> stage+1
611 input data p.i_data is read (only), is processed and goes into an
612 intermediate result store [process()]. this is updated combinatorially.
614 in a non-stall condition, the intermediate result will go into the
615 output (update_output). however if ever there is a stall, it goes
616 into r_data instead [update_buffer()].
618 when the non-stall condition is released, r_data is the first
619 to be transferred to the output [flush_buffer()], and the stall
622 on the next cycle (as long as stall is not raised again) the
623 input may begin to be processed and transferred directly to output.
626 def elaborate(self
, platform
):
627 self
.m
= ControlBase
._elaborate
(self
, platform
)
629 result
= self
.stage
.ospec()
630 r_data
= self
.stage
.ospec()
632 # establish some combinatorial temporaries
633 o_n_validn
= Signal(reset_less
=True)
634 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
635 nir_por
= Signal(reset_less
=True)
636 nir_por_n
= Signal(reset_less
=True)
637 p_i_valid
= Signal(reset_less
=True)
638 nir_novn
= Signal(reset_less
=True)
639 nirn_novn
= Signal(reset_less
=True)
640 por_pivn
= Signal(reset_less
=True)
641 npnn
= Signal(reset_less
=True)
642 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
643 o_n_validn
.eq(~self
.n
.o_valid
),
644 n_i_ready
.eq(self
.n
.i_ready_test
),
645 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
646 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
647 nir_novn
.eq(n_i_ready | o_n_validn
),
648 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
649 npnn
.eq(nir_por | nirn_novn
),
650 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
653 # store result of processing in combinatorial temporary
654 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
656 # if not in stall condition, update the temporary register
657 with self
.m
.If(self
.p
.o_ready
): # not stalled
658 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
660 # data pass-through conditions
661 with self
.m
.If(npnn
):
662 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
663 eq(self
.n
.o_data
, result
), # update output
665 # buffer flush conditions (NOTE: can override data passthru conditions)
666 with self
.m
.If(nir_por_n
): # not stalled
667 # Flush the [already processed] buffer to the output port.
668 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
669 eq(self
.n
.o_data
, r_data
), # flush buffer
671 # output ready conditions
672 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
677 class SimpleHandshake(ControlBase
):
678 """ simple handshake control. data and strobe signals travel in sync.
679 implements the protocol used by Wishbone and AXI4.
681 Argument: stage. see Stage API above
683 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
684 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
685 stage-1 p.i_data >>in stage n.o_data out>> stage+1
690 Inputs Temporary Output
691 ------- ---------- -----
692 P P N N PiV& ~NiV& N P
719 def elaborate(self
, platform
):
720 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
723 result
= self
.stage
.ospec()
725 # establish some combinatorial temporaries
726 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
727 p_i_valid_p_o_ready
= Signal(reset_less
=True)
728 p_i_valid
= Signal(reset_less
=True)
729 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
730 n_i_ready
.eq(self
.n
.i_ready_test
),
731 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
734 # store result of processing in combinatorial temporary
735 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
737 # previous valid and ready
738 with m
.If(p_i_valid_p_o_ready
):
739 m
.d
.sync
+= [r_busy
.eq(1), # output valid
740 eq(self
.n
.o_data
, result
), # update output
742 # previous invalid or not ready, however next is accepting
743 with m
.Elif(n_i_ready
):
744 m
.d
.sync
+= [eq(self
.n
.o_data
, result
)]
745 # TODO: could still send data here (if there was any)
746 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
747 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
749 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
750 # if next is ready, so is previous
751 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
756 class UnbufferedPipeline(ControlBase
):
757 """ A simple pipeline stage with single-clock synchronisation
758 and two-way valid/ready synchronised signalling.
760 Note that a stall in one stage will result in the entire pipeline
763 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
764 travel synchronously with the data: the valid/ready signalling
765 combines in a *combinatorial* fashion. Therefore, a long pipeline
766 chain will lengthen propagation delays.
768 Argument: stage. see Stage API, above
770 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
771 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
772 stage-1 p.i_data >>in stage n.o_data out>> stage+1
780 p.i_data : StageInput, shaped according to ispec
782 p.o_data : StageOutput, shaped according to ospec
784 r_data : input_shape according to ispec
785 A temporary (buffered) copy of a prior (valid) input.
786 This is HELD if the output is not ready. It is updated
788 result: output_shape according to ospec
789 The output of the combinatorial logic. it is updated
790 COMBINATORIALLY (no clock dependence).
822 Note: PoR is *NOT* involved in the above decision-making.
825 def elaborate(self
, platform
):
826 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
828 data_valid
= Signal() # is data valid or not
829 r_data
= self
.stage
.ospec() # output type
832 p_i_valid
= Signal(reset_less
=True)
833 pv
= Signal(reset_less
=True)
834 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
835 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
837 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
838 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
839 m
.d
.sync
+= data_valid
.eq(p_i_valid | \
840 (~self
.n
.i_ready_test
& data_valid
))
842 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
843 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
848 class UnbufferedPipeline2(ControlBase
):
849 """ A simple pipeline stage with single-clock synchronisation
850 and two-way valid/ready synchronised signalling.
852 Note that a stall in one stage will result in the entire pipeline
855 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
856 travel synchronously with the data: the valid/ready signalling
857 combines in a *combinatorial* fashion. Therefore, a long pipeline
858 chain will lengthen propagation delays.
860 Argument: stage. see Stage API, above
862 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
863 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
864 stage-1 p.i_data >>in stage n.o_data out>> stage+1
869 p.i_data : StageInput, shaped according to ispec
871 p.o_data : StageOutput, shaped according to ospec
873 buf : output_shape according to ospec
874 A temporary (buffered) copy of a valid output
875 This is HELD if the output is not ready. It is updated
879 def elaborate(self
, platform
):
880 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
882 buf_full
= Signal() # is data valid or not
883 buf
= self
.stage
.ospec() # output type
886 p_i_valid
= Signal(reset_less
=True)
887 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
889 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
890 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
891 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
893 odata
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
894 m
.d
.comb
+= eq(self
.n
.o_data
, odata
)
895 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
900 class PassThroughStage(StageCls
):
901 """ a pass-through stage which has its input data spec equal to its output,
902 and "passes through" its data from input to output.
904 def __init__(self
, iospecfn
):
905 self
.iospecfn
= iospecfn
906 def ispec(self
): return self
.iospecfn()
907 def ospec(self
): return self
.iospecfn()
908 def process(self
, i
): return i
911 class PassThroughHandshake(ControlBase
):
912 """ A control block that delays by one clock cycle.
915 def elaborate(self
, platform
):
916 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
919 p_i_valid
= Signal(reset_less
=True)
920 pvr
= Signal(reset_less
=True)
921 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
922 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
924 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
925 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
927 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), self
.n
.o_data
)
928 m
.d
.sync
+= eq(self
.n
.o_data
, odata
)
933 class RegisterPipeline(UnbufferedPipeline
):
934 """ A pipeline stage that delays by one clock cycle, creating a
935 sync'd latch out of o_data and o_valid as an indirect byproduct
936 of using PassThroughStage
938 def __init__(self
, iospecfn
):
939 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
942 class FIFOtest(ControlBase
):
943 """ A test of using a SyncFIFO to see if it will work.
944 Note: the only things it will accept is a Signal of width "width".
947 def __init__(self
, width
, depth
):
952 return Signal(width
, name
="data")
953 stage
= PassThroughStage(iospecfn
)
954 ControlBase
.__init
__(self
, stage
=stage
)
956 def elaborate(self
, platform
):
957 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
959 fifo
= SyncFIFO(self
.fwidth
, self
.fdepth
)
960 m
.submodules
.fifo
= fifo
962 # prev: make the FIFO "look" like a PrevControl...
965 fp
._o
_ready
= fifo
.writable
967 # ... so we can do this!
968 m
.d
.comb
+= fp
._connect
_in
(self
.p
, True)
970 # next: make the FIFO "look" like a NextControl...
972 fn
.o_valid
= fifo
.readable
974 fn
.o_data
= fifo
.dout
975 # ... so we can do this!
976 m
.d
.comb
+= fn
._connect
_out
(self
.n
)
978 # err... that should be all!