1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
4 Associated development bugs:
5 * http://bugs.libre-riscv.org/show_bug.cgi?id=64
6 * http://bugs.libre-riscv.org/show_bug.cgi?id=57
11 a strategically very important function that is identical in function
12 to nmigen's Signal.eq function, except it may take objects, or a list
13 of objects, or a tuple of objects, and where objects may also be
19 stage requires compliance with a strict API that may be
20 implemented in several means, including as a static class.
21 the methods of a stage instance must be as follows:
23 * ispec() - Input data format specification
24 returns an object or a list or tuple of objects, or
25 a Record, each object having an "eq" function which
26 takes responsibility for copying by assignment all
28 * ospec() - Output data format specification
29 requirements as for ospec
30 * process(m, i) - Processes an ispec-formatted object
31 returns a combinatorial block of a result that
32 may be assigned to the output, by way of the "eq"
34 * setup(m, i) - Optional function for setting up submodules
35 may be used for more complex stages, to link
36 the input (i) to submodules. must take responsibility
37 for adding those submodules to the module (m).
38 the submodules must be combinatorial blocks and
39 must have their inputs and output linked combinatorially.
41 Both StageCls (for use with non-static classes) and Stage (for use
42 by static classes) are abstract classes from which, for convenience
43 and as a courtesy to other developers, anything conforming to the
44 Stage API may *choose* to derive.
49 A useful combinatorial wrapper around stages that chains them together
50 and then presents a Stage-API-conformant interface. By presenting
51 the same API as the stages it wraps, it can clearly be used recursively.
56 A convenience class that takes an input shape, output shape, a
57 "processing" function and an optional "setup" function. Honestly
58 though, there's not much more effort to just... create a class
59 that returns a couple of Records (see ExampleAddRecordStage in
65 A convenience class that takes a single function as a parameter,
66 that is chain-called to create the exact same input and output spec.
67 It has a process() function that simply returns its input.
69 Instances of this class are completely redundant if handed to
70 StageChain, however when passed to UnbufferedPipeline they
71 can be used to introduce a single clock delay.
76 The base class for pipelines. Contains previous and next ready/valid/data.
77 Also has an extremely useful "connect" function that can be used to
78 connect a chain of pipelines and present the exact same prev/next
84 A simple stalling clock-synchronised pipeline that has no buffering
85 (unlike BufferedHandshake). Data flows on *every* clock cycle when
86 the conditions are right (this is nominally when the input is valid
87 and the output is ready).
89 A stall anywhere along the line will result in a stall back-propagating
90 down the entire chain. The BufferedHandshake by contrast will buffer
91 incoming data, allowing previous stages one clock cycle's grace before
94 An advantage of the UnbufferedPipeline over the Buffered one is
95 that the amount of logic needed (number of gates) is greatly
96 reduced (no second set of buffers basically)
98 The disadvantage of the UnbufferedPipeline is that the valid/ready
99 logic, if chained together, is *combinatorial*, resulting in
100 progressively larger gate delay.
102 PassThroughHandshake:
105 A Control class that introduces a single clock delay, passing its
106 data through unaltered. Unlike RegisterPipeline (which relies
107 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
113 A convenience class that, because UnbufferedPipeline introduces a single
114 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
115 stage that, duh, delays its (unmodified) input by one clock cycle.
120 nmigen implementation of buffered pipeline stage, based on zipcpu:
121 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
123 this module requires quite a bit of thought to understand how it works
124 (and why it is needed in the first place). reading the above is
125 *strongly* recommended.
127 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
128 the STB / ACK signals to raise and lower (on separate clocks) before
129 data may proceeed (thus only allowing one piece of data to proceed
130 on *ALTERNATE* cycles), the signalling here is a true pipeline
131 where data will flow on *every* clock when the conditions are right.
133 input acceptance conditions are when:
134 * incoming previous-stage strobe (p.i_valid) is HIGH
135 * outgoing previous-stage ready (p.o_ready) is LOW
137 output transmission conditions are when:
138 * outgoing next-stage strobe (n.o_valid) is HIGH
139 * outgoing next-stage ready (n.i_ready) is LOW
141 the tricky bit is when the input has valid data and the output is not
142 ready to accept it. if it wasn't for the clock synchronisation, it
143 would be possible to tell the input "hey don't send that data, we're
144 not ready". unfortunately, it's not possible to "change the past":
145 the previous stage *has no choice* but to pass on its data.
147 therefore, the incoming data *must* be accepted - and stored: that
148 is the responsibility / contract that this stage *must* accept.
149 on the same clock, it's possible to tell the input that it must
150 not send any more data. this is the "stall" condition.
152 we now effectively have *two* possible pieces of data to "choose" from:
153 the buffered data, and the incoming data. the decision as to which
154 to process and output is based on whether we are in "stall" or not.
155 i.e. when the next stage is no longer ready, the output comes from
156 the buffer if a stall had previously occurred, otherwise it comes
157 direct from processing the input.
159 this allows us to respect a synchronous "travelling STB" with what
160 dan calls a "buffered handshake".
162 it's quite a complex state machine!
167 Synchronised pipeline, Based on:
168 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
171 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
172 from nmigen
.cli
import verilog
, rtlil
173 from nmigen
.lib
.fifo
import SyncFIFO
, SyncFIFOBuffered
174 from nmigen
.hdl
.ast
import ArrayProxy
175 from nmigen
.hdl
.rec
import Record
, Layout
177 from abc
import ABCMeta
, abstractmethod
178 from collections
.abc
import Sequence
179 from queue
import Queue
182 class RecordObject(Record
):
183 def __init__(self
, layout
=None, name
=None):
184 Record
.__init
__(self
, layout
=layout
or [], name
=None)
186 def __setattr__(self
, k
, v
):
187 if k
in dir(Record
) or "fields" not in self
.__dict
__:
188 return object.__setattr
__(self
, k
, v
)
190 if isinstance(v
, Record
):
191 newlayout
= {k
: (k
, v
.layout
)}
193 newlayout
= {k
: (k
, v
.shape())}
194 self
.layout
.fields
.update(newlayout
)
199 """ contains signals that come *from* the previous stage (both in and out)
200 * i_valid: previous stage indicating all incoming data is valid.
201 may be a multi-bit signal, where all bits are required
202 to be asserted to indicate "valid".
203 * o_ready: output to next stage indicating readiness to accept data
204 * i_data : an input - added by the user of this class
207 def __init__(self
, i_width
=1, stage_ctl
=False):
208 self
.stage_ctl
= stage_ctl
209 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
210 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
211 self
.i_data
= None # XXX MUST BE ADDED BY USER
213 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
217 """ public-facing API: indicates (externally) that stage is ready
220 return self
.s_o_ready
# set dynamically by stage
221 return self
._o
_ready
# return this when not under dynamic control
223 def _connect_in(self
, prev
, direct
=False, fn
=None):
224 """ internal helper function to connect stage to an input source.
225 do not use to connect stage-to-stage!
227 i_valid
= prev
.i_valid
if direct
else prev
.i_valid_test
228 i_data
= fn(prev
.i_data
) if fn
is not None else prev
.i_data
229 return [self
.i_valid
.eq(i_valid
),
230 prev
.o_ready
.eq(self
.o_ready
),
231 eq(self
.i_data
, i_data
),
235 def i_valid_test(self
):
236 vlen
= len(self
.i_valid
)
238 # multi-bit case: valid only when i_valid is all 1s
239 all1s
= Const(-1, (len(self
.i_valid
), False))
240 i_valid
= (self
.i_valid
== all1s
)
242 # single-bit i_valid case
243 i_valid
= self
.i_valid
245 # when stage indicates not ready, incoming data
246 # must "appear" to be not ready too
248 i_valid
= i_valid
& self
.s_o_ready
254 """ contains the signals that go *to* the next stage (both in and out)
255 * o_valid: output indicating to next stage that data is valid
256 * i_ready: input from next stage indicating that it can accept data
257 * o_data : an output - added by the user of this class
259 def __init__(self
, stage_ctl
=False):
260 self
.stage_ctl
= stage_ctl
261 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
262 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
263 self
.o_data
= None # XXX MUST BE ADDED BY USER
265 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
268 def i_ready_test(self
):
270 return self
.i_ready
& self
.d_valid
273 def connect_to_next(self
, nxt
):
274 """ helper function to connect to the next stage data/valid/ready.
275 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
276 use this when connecting stage-to-stage
278 return [nxt
.i_valid
.eq(self
.o_valid
),
279 self
.i_ready
.eq(nxt
.o_ready
),
280 eq(nxt
.i_data
, self
.o_data
),
283 def _connect_out(self
, nxt
, direct
=False, fn
=None):
284 """ internal helper function to connect stage to an output source.
285 do not use to connect stage-to-stage!
287 i_ready
= nxt
.i_ready
if direct
else nxt
.i_ready_test
288 o_data
= fn(nxt
.o_data
) if fn
is not None else nxt
.o_data
289 return [nxt
.o_valid
.eq(self
.o_valid
),
290 self
.i_ready
.eq(i_ready
),
291 eq(o_data
, self
.o_data
),
296 """ a helper class for iterating twin-argument compound data structures.
298 Record is a special (unusual, recursive) case, where the input may be
299 specified as a dictionary (which may contain further dictionaries,
300 recursively), where the field names of the dictionary must match
301 the Record's field spec. Alternatively, an object with the same
302 member names as the Record may be assigned: it does not have to
305 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
306 has an eq function, the object being assigned to it (e.g. a python
307 object) might not. despite the *input* having an eq function,
308 that doesn't help us, because it's the *ArrayProxy* that's being
309 assigned to. so.... we cheat. use the ports() function of the
310 python object, enumerate them, find out the list of Signals that way,
313 def iterator2(self
, o
, i
):
314 if isinstance(o
, dict):
315 yield from self
.dict_iter2(o
, i
)
317 if not isinstance(o
, Sequence
):
319 for (ao
, ai
) in zip(o
, i
):
320 #print ("visit", fn, ao, ai)
321 if isinstance(ao
, Record
):
322 yield from self
.record_iter2(ao
, ai
)
323 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
324 yield from self
.arrayproxy_iter2(ao
, ai
)
328 def dict_iter2(self
, o
, i
):
329 for (k
, v
) in o
.items():
330 print ("d-iter", v
, i
[k
])
334 def record_iter2(self
, ao
, ai
):
335 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
336 if isinstance(field_shape
, Layout
):
340 if hasattr(val
, field_name
): # check for attribute
341 val
= getattr(val
, field_name
)
343 val
= val
[field_name
] # dictionary-style specification
344 yield from self
.iterator2(ao
.fields
[field_name
], val
)
346 def arrayproxy_iter2(self
, ao
, ai
):
348 op
= getattr(ao
, p
.name
)
349 #print (op, p, p.name)
350 yield from self
.iterator2(op
, p
)
353 """ a helper class for iterating single-argument compound data structures.
356 def iterate(self
, i
):
357 """ iterate a compound structure recursively using yield
359 if not isinstance(i
, Sequence
):
362 print ("iterate", ai
)
363 if isinstance(ai
, Record
):
364 print ("record", list(ai
.layout
))
365 yield from self
.record_iter(ai
)
366 elif isinstance(ai
, ArrayProxy
) and not isinstance(ai
, Value
):
367 yield from self
.array_iter(ai
)
371 def record_iter(self
, ai
):
372 for idx
, (field_name
, field_shape
, _
) in enumerate(ai
.layout
):
373 if isinstance(field_shape
, Layout
):
377 if hasattr(val
, field_name
): # check for attribute
378 val
= getattr(val
, field_name
)
380 val
= val
[field_name
] # dictionary-style specification
381 print ("recidx", idx
, field_name
, field_shape
, val
)
382 yield from self
.iterate(val
)
384 def array_iter(self
, ai
):
386 yield from self
.iterate(p
)
390 """ makes signals equal: a helper routine which identifies if it is being
391 passed a list (or tuple) of objects, or signals, or Records, and calls
392 the objects' eq function.
395 for (ao
, ai
) in Visitor2().iterator2(o
, i
):
397 if not isinstance(rres
, Sequence
):
405 """ flattens a compound structure recursively using Cat
407 res
= list(Visitor().iterate(i
))
411 class StageCls(metaclass
=ABCMeta
):
412 """ Class-based "Stage" API. requires instantiation (after derivation)
414 see "Stage API" above.. Note: python does *not* require derivation
415 from this class. All that is required is that the pipelines *have*
416 the functions listed in this class. Derivation from this class
417 is therefore merely a "courtesy" to maintainers.
420 def ispec(self
): pass # REQUIRED
422 def ospec(self
): pass # REQUIRED
424 #def setup(self, m, i): pass # OPTIONAL
426 def process(self
, i
): pass # REQUIRED
429 class Stage(metaclass
=ABCMeta
):
430 """ Static "Stage" API. does not require instantiation (after derivation)
432 see "Stage API" above. Note: python does *not* require derivation
433 from this class. All that is required is that the pipelines *have*
434 the functions listed in this class. Derivation from this class
435 is therefore merely a "courtesy" to maintainers.
447 #def setup(m, i): pass
454 class RecordBasedStage(Stage
):
455 """ convenience class which provides a Records-based layout.
456 honestly it's a lot easier just to create a direct Records-based
457 class (see ExampleAddRecordStage)
459 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
460 self
.in_shape
= in_shape
461 self
.out_shape
= out_shape
462 self
.__process
= processfn
463 self
.__setup
= setupfn
464 def ispec(self
): return Record(self
.in_shape
)
465 def ospec(self
): return Record(self
.out_shape
)
466 def process(seif
, i
): return self
.__process
(i
)
467 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
470 class StageChain(StageCls
):
471 """ pass in a list of stages, and they will automatically be
472 chained together via their input and output specs into a
475 the end result basically conforms to the exact same Stage API.
477 * input to this class will be the input of the first stage
478 * output of first stage goes into input of second
479 * output of second goes into input into third (etc. etc.)
480 * the output of this class will be the output of the last stage
482 def __init__(self
, chain
, specallocate
=False):
484 self
.specallocate
= specallocate
487 return self
.chain
[0].ispec()
490 return self
.chain
[-1].ospec()
492 def _specallocate_setup(self
, m
, i
):
493 for (idx
, c
) in enumerate(self
.chain
):
494 if hasattr(c
, "setup"):
495 c
.setup(m
, i
) # stage may have some module stuff
496 o
= self
.chain
[idx
].ospec() # last assignment survives
497 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
498 if idx
== len(self
.chain
)-1:
500 i
= self
.chain
[idx
+1].ispec() # new input on next loop
501 m
.d
.comb
+= eq(i
, o
) # assign to next input
502 return o
# last loop is the output
504 def _noallocate_setup(self
, m
, i
):
505 for (idx
, c
) in enumerate(self
.chain
):
506 if hasattr(c
, "setup"):
507 c
.setup(m
, i
) # stage may have some module stuff
508 i
= o
= c
.process(i
) # store input into "o"
509 return o
# last loop is the output
511 def setup(self
, m
, i
):
512 if self
.specallocate
:
513 self
.o
= self
._specallocate
_setup
(m
, i
)
515 self
.o
= self
._noallocate
_setup
(m
, i
)
517 def process(self
, i
):
518 return self
.o
# conform to Stage API: return last-loop output
522 """ Common functions for Pipeline API
524 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
525 """ Base class containing ready/valid/data to previous and next stages
527 * p: contains ready/valid to the previous stage
528 * n: contains ready/valid to the next stage
530 Except when calling Controlbase.connect(), user must also:
531 * add i_data member to PrevControl (p) and
532 * add o_data member to NextControl (n)
536 # set up input and output IO ACK (prev/next ready/valid)
537 self
.p
= PrevControl(in_multi
, stage_ctl
)
538 self
.n
= NextControl(stage_ctl
)
540 # set up the input and output data
541 if stage
is not None:
542 self
.p
.i_data
= stage
.ispec() # input type
543 self
.n
.o_data
= stage
.ospec()
545 def connect_to_next(self
, nxt
):
546 """ helper function to connect to the next stage data/valid/ready.
548 return self
.n
.connect_to_next(nxt
.p
)
550 def _connect_in(self
, prev
):
551 """ internal helper function to connect stage to an input source.
552 do not use to connect stage-to-stage!
554 return self
.p
._connect
_in
(prev
.p
)
556 def _connect_out(self
, nxt
):
557 """ internal helper function to connect stage to an output source.
558 do not use to connect stage-to-stage!
560 return self
.n
._connect
_out
(nxt
.n
)
562 def connect(self
, pipechain
):
563 """ connects a chain (list) of Pipeline instances together and
564 links them to this ControlBase instance:
566 in <----> self <---> out
569 [pipe1, pipe2, pipe3, pipe4]
572 out---in out--in out---in
574 Also takes care of allocating i_data/o_data, by looking up
575 the data spec for each end of the pipechain. i.e It is NOT
576 necessary to allocate self.p.i_data or self.n.o_data manually:
577 this is handled AUTOMATICALLY, here.
579 Basically this function is the direct equivalent of StageChain,
580 except that unlike StageChain, the Pipeline logic is followed.
582 Just as StageChain presents an object that conforms to the
583 Stage API from a list of objects that also conform to the
584 Stage API, an object that calls this Pipeline connect function
585 has the exact same pipeline API as the list of pipline objects
588 Thus it becomes possible to build up larger chains recursively.
589 More complex chains (multi-input, multi-output) will have to be
592 eqs
= [] # collated list of assignment statements
594 # connect inter-chain
595 for i
in range(len(pipechain
)-1):
597 pipe2
= pipechain
[i
+1]
598 eqs
+= pipe1
.connect_to_next(pipe2
)
600 # connect front of chain to ourselves
602 self
.p
.i_data
= front
.stage
.ispec()
603 eqs
+= front
._connect
_in
(self
)
605 # connect end of chain to ourselves
607 self
.n
.o_data
= end
.stage
.ospec()
608 eqs
+= end
._connect
_out
(self
)
612 def _postprocess(self
, i
): # XXX DISABLED
613 return i
# RETURNS INPUT
614 if hasattr(self
.stage
, "postprocess"):
615 return self
.stage
.postprocess(i
)
618 def set_input(self
, i
):
619 """ helper function to set the input data
621 return eq(self
.p
.i_data
, i
)
624 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
625 self
.n
.o_valid
, self
.p
.o_ready
,
627 if hasattr(self
.p
.i_data
, "ports"):
628 res
+= self
.p
.i_data
.ports()
631 if hasattr(self
.n
.o_data
, "ports"):
632 res
+= self
.n
.o_data
.ports()
637 def _elaborate(self
, platform
):
638 """ handles case where stage has dynamic ready/valid functions
642 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
643 self
.stage
.setup(m
, self
.p
.i_data
)
645 if not self
.p
.stage_ctl
:
648 # intercept the previous (outgoing) "ready", combine with stage ready
649 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
651 # intercept the next (incoming) "ready" and combine it with data valid
652 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
653 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
658 class BufferedHandshake(ControlBase
):
659 """ buffered pipeline stage. data and strobe signals travel in sync.
660 if ever the input is ready and the output is not, processed data
661 is shunted in a temporary register.
663 Argument: stage. see Stage API above
665 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
666 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
667 stage-1 p.i_data >>in stage n.o_data out>> stage+1
673 input data p.i_data is read (only), is processed and goes into an
674 intermediate result store [process()]. this is updated combinatorially.
676 in a non-stall condition, the intermediate result will go into the
677 output (update_output). however if ever there is a stall, it goes
678 into r_data instead [update_buffer()].
680 when the non-stall condition is released, r_data is the first
681 to be transferred to the output [flush_buffer()], and the stall
684 on the next cycle (as long as stall is not raised again) the
685 input may begin to be processed and transferred directly to output.
688 def elaborate(self
, platform
):
689 self
.m
= ControlBase
._elaborate
(self
, platform
)
691 result
= self
.stage
.ospec()
692 r_data
= self
.stage
.ospec()
694 # establish some combinatorial temporaries
695 o_n_validn
= Signal(reset_less
=True)
696 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
697 nir_por
= Signal(reset_less
=True)
698 nir_por_n
= Signal(reset_less
=True)
699 p_i_valid
= Signal(reset_less
=True)
700 nir_novn
= Signal(reset_less
=True)
701 nirn_novn
= Signal(reset_less
=True)
702 por_pivn
= Signal(reset_less
=True)
703 npnn
= Signal(reset_less
=True)
704 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
705 o_n_validn
.eq(~self
.n
.o_valid
),
706 n_i_ready
.eq(self
.n
.i_ready_test
),
707 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
708 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
709 nir_novn
.eq(n_i_ready | o_n_validn
),
710 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
711 npnn
.eq(nir_por | nirn_novn
),
712 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
715 # store result of processing in combinatorial temporary
716 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
718 # if not in stall condition, update the temporary register
719 with self
.m
.If(self
.p
.o_ready
): # not stalled
720 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
722 # data pass-through conditions
723 with self
.m
.If(npnn
):
724 o_data
= self
._postprocess
(result
)
725 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
726 eq(self
.n
.o_data
, o_data
), # update output
728 # buffer flush conditions (NOTE: can override data passthru conditions)
729 with self
.m
.If(nir_por_n
): # not stalled
730 # Flush the [already processed] buffer to the output port.
731 o_data
= self
._postprocess
(r_data
)
732 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
733 eq(self
.n
.o_data
, o_data
), # flush buffer
735 # output ready conditions
736 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
741 class SimpleHandshake(ControlBase
):
742 """ simple handshake control. data and strobe signals travel in sync.
743 implements the protocol used by Wishbone and AXI4.
745 Argument: stage. see Stage API above
747 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
748 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
749 stage-1 p.i_data >>in stage n.o_data out>> stage+1
754 Inputs Temporary Output Data
755 ------- ---------- ----- ----
756 P P N N PiV& ~NiR& N P
763 0 0 1 0 0 0 0 1 process(i_data)
764 0 0 1 1 0 0 0 1 process(i_data)
768 0 1 1 0 0 0 0 1 process(i_data)
769 0 1 1 1 0 0 0 1 process(i_data)
773 1 0 1 0 0 0 0 1 process(i_data)
774 1 0 1 1 0 0 0 1 process(i_data)
776 1 1 0 0 1 0 1 0 process(i_data)
777 1 1 0 1 1 1 1 0 process(i_data)
778 1 1 1 0 1 0 1 1 process(i_data)
779 1 1 1 1 1 0 1 1 process(i_data)
783 def elaborate(self
, platform
):
784 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
787 result
= self
.stage
.ospec()
789 # establish some combinatorial temporaries
790 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
791 p_i_valid_p_o_ready
= Signal(reset_less
=True)
792 p_i_valid
= Signal(reset_less
=True)
793 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
794 n_i_ready
.eq(self
.n
.i_ready_test
),
795 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
798 # store result of processing in combinatorial temporary
799 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
801 # previous valid and ready
802 with m
.If(p_i_valid_p_o_ready
):
803 o_data
= self
._postprocess
(result
)
804 m
.d
.sync
+= [r_busy
.eq(1), # output valid
805 eq(self
.n
.o_data
, o_data
), # update output
807 # previous invalid or not ready, however next is accepting
808 with m
.Elif(n_i_ready
):
809 o_data
= self
._postprocess
(result
)
810 m
.d
.sync
+= [eq(self
.n
.o_data
, o_data
)]
811 # TODO: could still send data here (if there was any)
812 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
813 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
815 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
816 # if next is ready, so is previous
817 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
822 class UnbufferedPipeline(ControlBase
):
823 """ A simple pipeline stage with single-clock synchronisation
824 and two-way valid/ready synchronised signalling.
826 Note that a stall in one stage will result in the entire pipeline
829 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
830 travel synchronously with the data: the valid/ready signalling
831 combines in a *combinatorial* fashion. Therefore, a long pipeline
832 chain will lengthen propagation delays.
834 Argument: stage. see Stage API, above
836 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
837 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
838 stage-1 p.i_data >>in stage n.o_data out>> stage+1
846 p.i_data : StageInput, shaped according to ispec
848 p.o_data : StageOutput, shaped according to ospec
850 r_data : input_shape according to ispec
851 A temporary (buffered) copy of a prior (valid) input.
852 This is HELD if the output is not ready. It is updated
854 result: output_shape according to ospec
855 The output of the combinatorial logic. it is updated
856 COMBINATORIALLY (no clock dependence).
860 Inputs Temp Output Data
882 1 1 0 0 0 1 1 process(i_data)
883 1 1 0 1 1 1 0 process(i_data)
884 1 1 1 0 0 1 1 process(i_data)
885 1 1 1 1 0 1 1 process(i_data)
888 Note: PoR is *NOT* involved in the above decision-making.
891 def elaborate(self
, platform
):
892 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
894 data_valid
= Signal() # is data valid or not
895 r_data
= self
.stage
.ospec() # output type
898 p_i_valid
= Signal(reset_less
=True)
899 pv
= Signal(reset_less
=True)
900 buf_full
= Signal(reset_less
=True)
901 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
902 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
903 m
.d
.comb
+= buf_full
.eq(~self
.n
.i_ready_test
& data_valid
)
905 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
906 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
907 m
.d
.sync
+= data_valid
.eq(p_i_valid | buf_full
)
910 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
911 o_data
= self
._postprocess
(r_data
)
912 m
.d
.comb
+= eq(self
.n
.o_data
, o_data
)
916 class UnbufferedPipeline2(ControlBase
):
917 """ A simple pipeline stage with single-clock synchronisation
918 and two-way valid/ready synchronised signalling.
920 Note that a stall in one stage will result in the entire pipeline
923 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
924 travel synchronously with the data: the valid/ready signalling
925 combines in a *combinatorial* fashion. Therefore, a long pipeline
926 chain will lengthen propagation delays.
928 Argument: stage. see Stage API, above
930 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
931 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
932 stage-1 p.i_data >>in stage n.o_data out>> stage+1
937 p.i_data : StageInput, shaped according to ispec
939 p.o_data : StageOutput, shaped according to ospec
941 buf : output_shape according to ospec
942 A temporary (buffered) copy of a valid output
943 This is HELD if the output is not ready. It is updated
946 Inputs Temp Output Data
948 P P N N ~NiR& N P (buf_full)
953 0 0 0 0 0 0 1 process(i_data)
954 0 0 0 1 1 1 0 reg (odata, unchanged)
955 0 0 1 0 0 0 1 process(i_data)
956 0 0 1 1 0 0 1 process(i_data)
958 0 1 0 0 0 0 1 process(i_data)
959 0 1 0 1 1 1 0 reg (odata, unchanged)
960 0 1 1 0 0 0 1 process(i_data)
961 0 1 1 1 0 0 1 process(i_data)
963 1 0 0 0 0 1 1 process(i_data)
964 1 0 0 1 1 1 0 reg (odata, unchanged)
965 1 0 1 0 0 1 1 process(i_data)
966 1 0 1 1 0 1 1 process(i_data)
968 1 1 0 0 0 1 1 process(i_data)
969 1 1 0 1 1 1 0 reg (odata, unchanged)
970 1 1 1 0 0 1 1 process(i_data)
971 1 1 1 1 0 1 1 process(i_data)
974 Note: PoR is *NOT* involved in the above decision-making.
977 def elaborate(self
, platform
):
978 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
980 buf_full
= Signal() # is data valid or not
981 buf
= self
.stage
.ospec() # output type
984 p_i_valid
= Signal(reset_less
=True)
985 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
987 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
988 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
989 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
991 o_data
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
992 o_data
= self
._postprocess
(o_data
)
993 m
.d
.comb
+= eq(self
.n
.o_data
, o_data
)
994 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
999 class PassThroughStage(StageCls
):
1000 """ a pass-through stage which has its input data spec equal to its output,
1001 and "passes through" its data from input to output.
1003 def __init__(self
, iospecfn
):
1004 self
.iospecfn
= iospecfn
1005 def ispec(self
): return self
.iospecfn()
1006 def ospec(self
): return self
.iospecfn()
1007 def process(self
, i
): return i
1010 class PassThroughHandshake(ControlBase
):
1011 """ A control block that delays by one clock cycle.
1013 Inputs Temporary Output Data
1014 ------- ------------------ ----- ----
1015 P P N N PiV& PiV| NiR| pvr N P (pvr)
1016 i o i o PoR ~PoR ~NoV o o
1020 0 0 0 0 0 1 1 0 1 1 odata (unchanged)
1021 0 0 0 1 0 1 0 0 1 0 odata (unchanged)
1022 0 0 1 0 0 1 1 0 1 1 odata (unchanged)
1023 0 0 1 1 0 1 1 0 1 1 odata (unchanged)
1025 0 1 0 0 0 0 1 0 0 1 odata (unchanged)
1026 0 1 0 1 0 0 0 0 0 0 odata (unchanged)
1027 0 1 1 0 0 0 1 0 0 1 odata (unchanged)
1028 0 1 1 1 0 0 1 0 0 1 odata (unchanged)
1030 1 0 0 0 0 1 1 1 1 1 process(in)
1031 1 0 0 1 0 1 0 0 1 0 odata (unchanged)
1032 1 0 1 0 0 1 1 1 1 1 process(in)
1033 1 0 1 1 0 1 1 1 1 1 process(in)
1035 1 1 0 0 1 1 1 1 1 1 process(in)
1036 1 1 0 1 1 1 0 0 1 0 odata (unchanged)
1037 1 1 1 0 1 1 1 1 1 1 process(in)
1038 1 1 1 1 1 1 1 1 1 1 process(in)
1043 def elaborate(self
, platform
):
1044 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1046 r_data
= self
.stage
.ospec() # output type
1049 p_i_valid
= Signal(reset_less
=True)
1050 pvr
= Signal(reset_less
=True)
1051 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
1052 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
1054 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
1055 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
1057 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), r_data
)
1058 m
.d
.sync
+= eq(r_data
, odata
)
1059 r_data
= self
._postprocess
(r_data
)
1060 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
1065 class RegisterPipeline(UnbufferedPipeline
):
1066 """ A pipeline stage that delays by one clock cycle, creating a
1067 sync'd latch out of o_data and o_valid as an indirect byproduct
1068 of using PassThroughStage
1070 def __init__(self
, iospecfn
):
1071 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
1074 class FIFOControl(ControlBase
):
1075 """ FIFO Control. Uses SyncFIFO to store data, coincidentally
1076 happens to have same valid/ready signalling as Stage API.
1078 i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
1081 def __init__(self
, depth
, stage
, in_multi
=None, stage_ctl
=False,
1082 fwft
=True, buffered
=False, pipe
=False):
1085 * depth: number of entries in the FIFO
1086 * stage: data processing block
1087 * fwft : first word fall-thru mode (non-fwft introduces delay)
1088 * buffered: use buffered FIFO (introduces extra cycle delay)
1090 NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
1091 (fwft=True, buffered=False)
1093 NOTE 2: i_data *must* have a shape function. it can therefore
1094 be a Signal, or a Record, or a RecordObject.
1096 data is processed (and located) as follows:
1098 self.p self.stage temp fn temp fn temp fp self.n
1099 i_data->process()->result->flatten->din.FIFO.dout->flatten(o_data)
1101 yes, really: flatten produces a Cat() which can be assigned to.
1102 this is how the FIFO gets de-flattened without needing a de-flatten
1106 assert not (fwft
and buffered
), "buffered cannot do fwft"
1110 self
.buffered
= buffered
1113 ControlBase
.__init
__(self
, stage
, in_multi
, stage_ctl
)
1115 def elaborate(self
, platform
):
1116 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1118 # make a FIFO with a signal of equal width to the o_data.
1119 (fwidth
, _
) = self
.n
.o_data
.shape()
1121 fifo
= SyncFIFOBuffered(fwidth
, self
.fdepth
)
1123 fifo
= Queue(fwidth
, self
.fdepth
, fwft
=self
.fwft
, pipe
=self
.pipe
)
1124 m
.submodules
.fifo
= fifo
1126 # store result of processing in combinatorial temporary
1127 result
= self
.stage
.ospec()
1128 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
1130 # connect previous rdy/valid/data - do flatten on i_data
1131 # NOTE: cannot do the PrevControl-looking trick because
1132 # of need to process the data. shaaaame....
1133 m
.d
.comb
+= [fifo
.we
.eq(self
.p
.i_valid_test
),
1134 self
.p
.o_ready
.eq(fifo
.writable
),
1135 eq(fifo
.din
, flatten(result
)),
1138 # connect next rdy/valid/data - do flatten on o_data
1139 connections
= [self
.n
.o_valid
.eq(fifo
.readable
),
1140 fifo
.re
.eq(self
.n
.i_ready_test
),
1142 if self
.fwft
or self
.buffered
:
1143 m
.d
.comb
+= connections
1145 m
.d
.sync
+= connections
# unbuffered fwft mode needs sync
1146 o_data
= flatten(self
.n
.o_data
).eq(fifo
.dout
)
1147 o_data
= self
._postprocess
(o_data
)
1154 class UnbufferedPipeline(FIFOControl
):
1155 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1156 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
1157 fwft
=True, pipe
=False)
1159 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
1160 class PassThroughHandshake(FIFOControl
):
1161 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1162 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
1163 fwft
=True, pipe
=True)
1165 # this is *probably* BufferedHandshake, although test #997 now succeeds.
1166 class BufferedHandshake(FIFOControl
):
1167 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1168 FIFOControl
.__init
__(self
, 2, stage
, in_multi
, stage_ctl
,
1169 fwft
=True, pipe
=False)
1173 # this is *probably* SimpleHandshake (note: memory cell size=0)
1174 class SimpleHandshake(FIFOControl):
1175 def __init__(self, stage, in_multi=None, stage_ctl=False):
1176 FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
1177 fwft=True, pipe=False)