src/add/test_add.py

   1 from nmigen import Module, Signal
   2 from nmigen.compat.sim import run_simulation
   3
   4 from nmigen_add_experiment import FPADD
   5
   6 class ORGate:
   7     def __init__(self):
   8         self.a = Signal()
   9         self.b = Signal()
  10         self.x = Signal()
  11
  12     def get_fragment(self, platform=None):
  13
  14         m = Module()
  15         m.d.comb += self.x.eq(self.a | self.b)
  16
  17         return m
  18
  19 def check_case(dut, a, b, z):
  20     yield dut.in_a.v.eq(a)
  21     yield dut.in_a.stb.eq(1)
  22     yield
  23     yield
  24     a_ack = (yield dut.in_a.ack)
  25     assert a_ack == 0
  26     yield dut.in_b.v.eq(b)
  27     yield dut.in_b.stb.eq(1)
  28     b_ack = (yield dut.in_b.ack)
  29     assert b_ack == 0
  30
  31     while True:
  32         yield
  33         out_z_stb = (yield dut.out_z.stb)
  34         if not out_z_stb:
  35             continue
  36         yield dut.in_a.stb.eq(0)
  37         yield dut.in_b.stb.eq(0)
  38         yield dut.out_z.ack.eq(1)
  39         yield
  40         yield dut.out_z.ack.eq(0)
  41         yield
  42         yield
  43         break
  44
  45     out_z = yield dut.out_z.v
  46     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
  47
  48 def testbench(dut):
  49     yield from check_case(dut, 0, 0, 0)
  50     yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
  51     yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
  52     yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
  53     yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
  54     yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
  55     yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
  56     yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
  57     yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
  58     yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
  59     yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000)
  60     yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
  61     yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
  62     yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
  63     yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
  64     yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
  65     yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
  66     yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000)
  67     yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  68     yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
  69     yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
  70     yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
  71     yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
  72     yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
  73     yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
  74     yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
  75     #yield from check_case(dut, 1, 0, 1)
  76     #yield from check_case(dut, 1, 1, 1)
  77
  78 if __name__ == '__main__':
  79     dut = FPADD(width=32, single_cycle=True)
  80     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
  81