src/add/test_add16.py

   1 from random import randint
   2 from random import seed
   3 from operator import add
   4
   5 from nmigen import Module, Signal
   6 from nmigen.compat.sim import run_simulation
   7
   8 from nmigen_add_experiment import FPADD
   9
  10 from unit_test_half import (get_mantissa, get_exponent, get_sign, is_nan,
  11                                 is_inf, is_pos_inf, is_neg_inf,
  12                                 match, get_case, check_case, run_test,
  13                                 run_edge_cases, run_corner_cases)
  14
  15 def testbench(dut):
  16     yield from check_case(dut, 0xfc00, 0x7c00, 0xfe00)
  17     yield from check_case(dut, 0x8000, 0, 0)
  18     yield from check_case(dut, 0, 0, 0)
  19
  20     count = 0
  21
  22     #regression tests
  23     stimulus_a = [ 0x8000 ]
  24     stimulus_b = [ 0x0000 ]
  25     yield from run_test(dut, stimulus_a, stimulus_b, add)
  26     count += len(stimulus_a)
  27     print (count, "vectors passed")
  28
  29     yield from run_corner_cases(dut, count, add)
  30     yield from run_edge_cases(dut, count, add)
  31
  32 if __name__ == '__main__':
  33     dut = FPADD(width=16, single_cycle=True)
  34     run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")
  35