src/add/test_add_base.py

   1 from random import randint
   2 from operator import add
   3
   4 from nmigen import Module, Signal
   5 from nmigen.compat.sim import run_simulation
   6
   7 from nmigen_add_experiment import FPADDBase, FPADDBaseMod
   8
   9 def get_case(dut, a, b, mid):
  10     yield dut.in_mid.eq(mid)
  11     yield dut.in_a.eq(a)
  12     yield dut.in_b.eq(b)
  13     yield dut.in_t.stb.eq(1)
  14     yield
  15     yield
  16     yield
  17     yield
  18     ack = (yield dut.in_t.ack)
  19     assert ack == 0
  20
  21     yield dut.in_t.stb.eq(0)
  22
  23     yield dut.out_z.ack.eq(1)
  24
  25     while True:
  26         out_z_stb = (yield dut.out_z.stb)
  27         if not out_z_stb:
  28             yield
  29             continue
  30         out_z = yield dut.out_z.v
  31         out_mid = yield dut.out_mid
  32         yield dut.out_z.ack.eq(0)
  33         yield
  34         break
  35
  36     return out_z, out_mid
  37
  38 def check_case(dut, a, b, z, mid=None):
  39     if mid is None:
  40         mid = randint(0, 6)
  41     out_z, out_mid = yield from get_case(dut, a, b, mid)
  42     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
  43     assert out_mid == mid, "Output mid 0x%x != expected 0x%x" % (out_mid, mid)
  44
  45
  46
  47 def testbench(dut):
  48     yield from check_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
  49     yield from check_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
  50     yield from check_case(dut, 0x00000047, 0x80000048, 0x80000001)
  51     yield from check_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
  52     yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
  53     yield from check_case(dut, 0, 0, 0)
  54     yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
  55     yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  56     #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  57     yield from check_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
  58     yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
  59     yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
  60     yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
  61     yield from check_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
  62     yield from check_case(dut, 0x40000000, 0xc0000000, 0x00000000)
  63     yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
  64     yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
  65     yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
  66     yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
  67     yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
  68     yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
  69     yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
  70     yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
  71     yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
  72     yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
  73     yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
  74     yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
  75     yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
  76     yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
  77     yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
  78     yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  79     yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
  80     yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
  81     yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
  82     yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
  83     yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
  84     yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
  85     yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
  86     yield from check_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
  87     yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
  88     yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
  89     yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
  90
  91 if __name__ == '__main__':
  92     dut = FPADDBaseMod(width=32, id_wid=5, single_cycle=True)
  93     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
  94