add unit test for multi-in multi-out FPADDBasePipe
[ieee754fpu.git] / src / add / test_buf_pipe.py
1 """ Unit tests for Buffered and Unbuffered pipelines
2
3 contains useful worked examples of how to use the Pipeline API,
4 including:
5
6 * Combinatorial Stage "Chaining"
7 * class-based data stages
8 * nmigen module-based data stages
9 * special nmigen module-based data stage, where the stage *is* the module
10 * Record-based data stages
11 * static-class data stages
12 * multi-stage pipelines (and how to connect them)
13 * how to *use* the pipelines (see Test5) - how to get data in and out
14
15 """
16
17 from nmigen import Module, Signal, Mux
18 from nmigen.hdl.rec import Record
19 from nmigen.compat.sim import run_simulation
20 from nmigen.cli import verilog, rtlil
21
22 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
23 from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
24 from example_buf_pipe import ExampleStageCls
25 from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
26 from example_buf_pipe import StageChain, ControlBase, StageCls
27
28 from random import randint
29
30
31 def check_o_n_valid(dut, val):
32 o_n_valid = yield dut.n.o_valid
33 assert o_n_valid == val
34
35 def check_o_n_valid2(dut, val):
36 o_n_valid = yield dut.n.o_valid
37 assert o_n_valid == val
38
39
40 def testbench(dut):
41 #yield dut.i_p_rst.eq(1)
42 yield dut.n.i_ready.eq(0)
43 yield dut.p.o_ready.eq(0)
44 yield
45 yield
46 #yield dut.i_p_rst.eq(0)
47 yield dut.n.i_ready.eq(1)
48 yield dut.p.i_data.eq(5)
49 yield dut.p.i_valid.eq(1)
50 yield
51
52 yield dut.p.i_data.eq(7)
53 yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
54 yield
55 yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
56
57 yield dut.p.i_data.eq(2)
58 yield
59 yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
60 yield dut.p.i_data.eq(9)
61 yield
62 yield dut.p.i_valid.eq(0)
63 yield dut.p.i_data.eq(12)
64 yield
65 yield dut.p.i_data.eq(32)
66 yield dut.n.i_ready.eq(1)
67 yield
68 yield from check_o_n_valid(dut, 1) # buffer still needs to output
69 yield
70 yield from check_o_n_valid(dut, 1) # buffer still needs to output
71 yield
72 yield from check_o_n_valid(dut, 0) # buffer outputted, *now* we're done.
73 yield
74
75
76 def testbench2(dut):
77 #yield dut.p.i_rst.eq(1)
78 yield dut.n.i_ready.eq(0)
79 #yield dut.p.o_ready.eq(0)
80 yield
81 yield
82 #yield dut.p.i_rst.eq(0)
83 yield dut.n.i_ready.eq(1)
84 yield dut.p.i_data.eq(5)
85 yield dut.p.i_valid.eq(1)
86 yield
87
88 yield dut.p.i_data.eq(7)
89 yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
90 yield
91 yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
92
93 yield dut.p.i_data.eq(2)
94 yield
95 yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
96 yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
97 yield dut.p.i_data.eq(9)
98 yield
99 yield dut.p.i_valid.eq(0)
100 yield dut.p.i_data.eq(12)
101 yield
102 yield dut.p.i_data.eq(32)
103 yield dut.n.i_ready.eq(1)
104 yield
105 yield from check_o_n_valid2(dut, 1) # buffer still needs to output
106 yield
107 yield from check_o_n_valid2(dut, 1) # buffer still needs to output
108 yield
109 yield from check_o_n_valid2(dut, 1) # buffer still needs to output
110 yield
111 yield from check_o_n_valid2(dut, 0) # buffer outputted, *now* we're done.
112 yield
113 yield
114 yield
115
116
117 class Test3:
118 def __init__(self, dut, resultfn):
119 self.dut = dut
120 self.resultfn = resultfn
121 self.data = []
122 for i in range(num_tests):
123 #data.append(randint(0, 1<<16-1))
124 self.data.append(i+1)
125 self.i = 0
126 self.o = 0
127
128 def send(self):
129 while self.o != len(self.data):
130 send_range = randint(0, 3)
131 for j in range(randint(1,10)):
132 if send_range == 0:
133 send = True
134 else:
135 send = randint(0, send_range) != 0
136 o_p_ready = yield self.dut.p.o_ready
137 if not o_p_ready:
138 yield
139 continue
140 if send and self.i != len(self.data):
141 yield self.dut.p.i_valid.eq(1)
142 yield self.dut.p.i_data.eq(self.data[self.i])
143 self.i += 1
144 else:
145 yield self.dut.p.i_valid.eq(0)
146 yield
147
148 def rcv(self):
149 while self.o != len(self.data):
150 stall_range = randint(0, 3)
151 for j in range(randint(1,10)):
152 stall = randint(0, stall_range) != 0
153 yield self.dut.n.i_ready.eq(stall)
154 yield
155 o_n_valid = yield self.dut.n.o_valid
156 i_n_ready = yield self.dut.n.i_ready
157 if not o_n_valid or not i_n_ready:
158 continue
159 o_data = yield self.dut.n.o_data
160 self.resultfn(o_data, self.data[self.o], self.i, self.o)
161 self.o += 1
162 if self.o == len(self.data):
163 break
164
165 def test3_resultfn(o_data, expected, i, o):
166 assert o_data == expected + 1, \
167 "%d-%d data %x not match %x\n" \
168 % (i, o, o_data, expected)
169
170 def data_placeholder():
171 data = []
172 for i in range(num_tests):
173 d = PlaceHolder()
174 d.src1 = randint(0, 1<<16-1)
175 d.src2 = randint(0, 1<<16-1)
176 data.append(d)
177 return data
178
179 def data_dict():
180 data = []
181 for i in range(num_tests):
182 data.append({'src1': randint(0, 1<<16-1),
183 'src2': randint(0, 1<<16-1)})
184 return data
185
186
187 class Test5:
188 def __init__(self, dut, resultfn, data=None):
189 self.dut = dut
190 self.resultfn = resultfn
191 if data:
192 self.data = data
193 else:
194 self.data = []
195 for i in range(num_tests):
196 self.data.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
197 self.i = 0
198 self.o = 0
199
200 def send(self):
201 while self.o != len(self.data):
202 send_range = randint(0, 3)
203 for j in range(randint(1,10)):
204 if send_range == 0:
205 send = True
206 else:
207 send = randint(0, send_range) != 0
208 o_p_ready = yield self.dut.p.o_ready
209 if not o_p_ready:
210 yield
211 continue
212 if send and self.i != len(self.data):
213 yield self.dut.p.i_valid.eq(1)
214 for v in self.dut.set_input(self.data[self.i]):
215 yield v
216 self.i += 1
217 else:
218 yield self.dut.p.i_valid.eq(0)
219 yield
220
221 def rcv(self):
222 while self.o != len(self.data):
223 stall_range = randint(0, 3)
224 for j in range(randint(1,10)):
225 stall = randint(0, stall_range) != 0
226 yield self.dut.n.i_ready.eq(stall)
227 yield
228 o_n_valid = yield self.dut.n.o_valid
229 i_n_ready = yield self.dut.n.i_ready
230 if not o_n_valid or not i_n_ready:
231 continue
232 if isinstance(self.dut.n.o_data, Record):
233 o_data = {}
234 dod = self.dut.n.o_data
235 for k, v in dod.fields.items():
236 o_data[k] = yield v
237 else:
238 o_data = yield self.dut.n.o_data
239 self.resultfn(o_data, self.data[self.o], self.i, self.o)
240 self.o += 1
241 if self.o == len(self.data):
242 break
243
244 def test5_resultfn(o_data, expected, i, o):
245 res = expected[0] + expected[1]
246 assert o_data == res, \
247 "%d-%d data %x not match %s\n" \
248 % (i, o, o_data, repr(expected))
249
250 def testbench4(dut):
251 data = []
252 for i in range(num_tests):
253 #data.append(randint(0, 1<<16-1))
254 data.append(i+1)
255 i = 0
256 o = 0
257 while True:
258 stall = randint(0, 3) != 0
259 send = randint(0, 5) != 0
260 yield dut.n.i_ready.eq(stall)
261 o_p_ready = yield dut.p.o_ready
262 if o_p_ready:
263 if send and i != len(data):
264 yield dut.p.i_valid.eq(1)
265 yield dut.p.i_data.eq(data[i])
266 i += 1
267 else:
268 yield dut.p.i_valid.eq(0)
269 yield
270 o_n_valid = yield dut.n.o_valid
271 i_n_ready = yield dut.n.i_ready
272 if o_n_valid and i_n_ready:
273 o_data = yield dut.n.o_data
274 assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
275 % (i, o, o_data, data[o])
276 o += 1
277 if o == len(data):
278 break
279
280 ######################################################################
281 # Test 2 and 4
282 ######################################################################
283
284 class ExampleBufPipe2(ControlBase):
285 """ Example of how to do chained pipeline stages.
286 """
287
288 def elaborate(self, platform):
289 m = Module()
290
291 pipe1 = ExampleBufPipe()
292 pipe2 = ExampleBufPipe()
293
294 self.p.i_data = pipe1.stage.ispec()
295 self.n.o_data = pipe2.stage.ospec()
296
297 m.submodules.pipe1 = pipe1
298 m.submodules.pipe2 = pipe2
299
300 self.connect(m, [pipe1, pipe2])
301
302 return m
303
304
305 ######################################################################
306 # Test 9
307 ######################################################################
308
309 class ExampleBufPipeChain2(BufferedPipeline):
310 """ connects two stages together as a *single* combinatorial stage.
311 """
312 def __init__(self):
313 stage1 = ExampleStageCls()
314 stage2 = ExampleStageCls()
315 combined = StageChain([stage1, stage2])
316 BufferedPipeline.__init__(self, combined)
317
318
319 def data_chain2():
320 data = []
321 for i in range(num_tests):
322 data.append(randint(0, 1<<16-2))
323 return data
324
325
326 def test9_resultfn(o_data, expected, i, o):
327 res = expected + 2
328 assert o_data == res, \
329 "%d-%d data %x not match %s\n" \
330 % (i, o, o_data, repr(expected))
331
332
333 ######################################################################
334 # Test 6 and 10
335 ######################################################################
336
337 class SetLessThan:
338 def __init__(self, width, signed):
339 self.src1 = Signal((width, signed))
340 self.src2 = Signal((width, signed))
341 self.output = Signal(width)
342
343 def elaborate(self, platform):
344 m = Module()
345 m.d.comb += self.output.eq(Mux(self.src1 < self.src2, 1, 0))
346 return m
347
348
349 class LTStage(StageCls):
350 """ module-based stage example
351 """
352 def __init__(self):
353 self.slt = SetLessThan(16, True)
354
355 def ispec(self):
356 return (Signal(16), Signal(16))
357
358 def ospec(self):
359 return Signal(16)
360
361 def setup(self, m, i):
362 self.o = Signal(16)
363 m.submodules.slt = self.slt
364 m.d.comb += self.slt.src1.eq(i[0])
365 m.d.comb += self.slt.src2.eq(i[1])
366 m.d.comb += self.o.eq(self.slt.output)
367
368 def process(self, i):
369 return self.o
370
371
372 class LTStageDerived(SetLessThan, StageCls):
373 """ special version of a nmigen module where the module is also a stage
374
375 shows that you don't actually need to combinatorially connect
376 to the outputs, or add the module as a submodule: just return
377 the module output parameter(s) from the Stage.process() function
378 """
379
380 def __init__(self):
381 SetLessThan.__init__(self, 16, True)
382
383 def ispec(self):
384 return (Signal(16), Signal(16))
385
386 def ospec(self):
387 return Signal(16)
388
389 def setup(self, m, i):
390 m.submodules.slt = self
391 m.d.comb += self.src1.eq(i[0])
392 m.d.comb += self.src2.eq(i[1])
393
394 def process(self, i):
395 return self.output
396
397
398 class ExampleLTPipeline(UnbufferedPipeline):
399 """ an example of how to use the unbuffered pipeline.
400 """
401
402 def __init__(self):
403 stage = LTStage()
404 UnbufferedPipeline.__init__(self, stage)
405
406
407 class ExampleLTBufferedPipeDerived(BufferedPipeline):
408 """ an example of how to use the buffered pipeline.
409 """
410
411 def __init__(self):
412 stage = LTStageDerived()
413 BufferedPipeline.__init__(self, stage)
414
415
416 def test6_resultfn(o_data, expected, i, o):
417 res = 1 if expected[0] < expected[1] else 0
418 assert o_data == res, \
419 "%d-%d data %x not match %s\n" \
420 % (i, o, o_data, repr(expected))
421
422
423 ######################################################################
424 # Test 7
425 ######################################################################
426
427 class ExampleAddRecordStage(StageCls):
428 """ example use of a Record
429 """
430
431 record_spec = [('src1', 16), ('src2', 16)]
432 def ispec(self):
433 """ returns a Record using the specification
434 """
435 return Record(self.record_spec)
436
437 def ospec(self):
438 return Record(self.record_spec)
439
440 def process(self, i):
441 """ process the input data, returning a dictionary with key names
442 that exactly match the Record's attributes.
443 """
444 return {'src1': i.src1 + 1,
445 'src2': i.src2 + 1}
446
447 ######################################################################
448 # Test 11
449 ######################################################################
450
451 class ExampleAddRecordPlaceHolderStage(StageCls):
452 """ example use of a Record, with a placeholder as the processing result
453 """
454
455 record_spec = [('src1', 16), ('src2', 16)]
456 def ispec(self):
457 """ returns a Record using the specification
458 """
459 return Record(self.record_spec)
460
461 def ospec(self):
462 return Record(self.record_spec)
463
464 def process(self, i):
465 """ process the input data, returning a PlaceHolder class instance
466 with attributes that exactly match those of the Record.
467 """
468 o = PlaceHolder()
469 o.src1 = i.src1 + 1
470 o.src2 = i.src2 + 1
471 return o
472
473
474 class PlaceHolder: pass
475
476
477 class ExampleAddRecordPipe(UnbufferedPipeline):
478 """ an example of how to use the combinatorial pipeline.
479 """
480
481 def __init__(self):
482 stage = ExampleAddRecordStage()
483 UnbufferedPipeline.__init__(self, stage)
484
485
486 def test7_resultfn(o_data, expected, i, o):
487 res = (expected['src1'] + 1, expected['src2'] + 1)
488 assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \
489 "%d-%d data %s not match %s\n" \
490 % (i, o, repr(o_data), repr(expected))
491
492
493 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
494 """ an example of how to use the combinatorial pipeline.
495 """
496
497 def __init__(self):
498 stage = ExampleAddRecordPlaceHolderStage()
499 UnbufferedPipeline.__init__(self, stage)
500
501
502 def test11_resultfn(o_data, expected, i, o):
503 res1 = expected.src1 + 1
504 res2 = expected.src2 + 1
505 assert o_data['src1'] == res1 and o_data['src2'] == res2, \
506 "%d-%d data %s not match %s\n" \
507 % (i, o, repr(o_data), repr(expected))
508
509
510 ######################################################################
511 # Test 8
512 ######################################################################
513
514
515 class Example2OpClass:
516 """ an example of a class used to store 2 operands.
517 requires an eq function, to conform with the pipeline stage API
518 """
519
520 def __init__(self):
521 self.op1 = Signal(16)
522 self.op2 = Signal(16)
523
524 def eq(self, i):
525 return [self.op1.eq(i.op1), self.op2.eq(i.op2)]
526
527
528 class ExampleAddClassStage(StageCls):
529 """ an example of how to use the buffered pipeline, as a class instance
530 """
531
532 def ispec(self):
533 """ returns an instance of an Example2OpClass.
534 """
535 return Example2OpClass()
536
537 def ospec(self):
538 """ returns an output signal which will happen to contain the sum
539 of the two inputs
540 """
541 return Signal(16)
542
543 def process(self, i):
544 """ process the input data (sums the values in the tuple) and returns it
545 """
546 return i.op1 + i.op2
547
548
549 class ExampleBufPipeAddClass(BufferedPipeline):
550 """ an example of how to use the buffered pipeline, using a class instance
551 """
552
553 def __init__(self):
554 addstage = ExampleAddClassStage()
555 BufferedPipeline.__init__(self, addstage)
556
557
558 class TestInputAdd:
559 """ the eq function, called by set_input, needs an incoming object
560 that conforms to the Example2OpClass.eq function requirements
561 easiest way to do that is to create a class that has the exact
562 same member layout (self.op1, self.op2) as Example2OpClass
563 """
564 def __init__(self, op1, op2):
565 self.op1 = op1
566 self.op2 = op2
567
568
569 def test8_resultfn(o_data, expected, i, o):
570 res = expected.op1 + expected.op2 # these are a TestInputAdd instance
571 assert o_data == res, \
572 "%d-%d data %x not match %s\n" \
573 % (i, o, o_data, repr(expected))
574
575 def data_2op():
576 data = []
577 for i in range(num_tests):
578 data.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
579 return data
580
581
582 num_tests = 100
583
584 if __name__ == '__main__':
585 print ("test 1")
586 dut = ExampleBufPipe()
587 run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
588
589 print ("test 2")
590 dut = ExampleBufPipe2()
591 run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
592 ports = [dut.p.i_valid, dut.n.i_ready,
593 dut.n.o_valid, dut.p.o_ready] + \
594 [dut.p.i_data] + [dut.n.o_data]
595 vl = rtlil.convert(dut, ports=ports)
596 with open("test_bufpipe2.il", "w") as f:
597 f.write(vl)
598
599
600 print ("test 3")
601 dut = ExampleBufPipe()
602 test = Test3(dut, test3_resultfn)
603 run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
604
605 print ("test 3.5")
606 dut = ExamplePipeline()
607 test = Test3(dut, test3_resultfn)
608 run_simulation(dut, [test.send, test.rcv], vcd_name="test_combpipe3.vcd")
609
610 print ("test 4")
611 dut = ExampleBufPipe2()
612 run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
613
614 print ("test 5")
615 dut = ExampleBufPipeAdd()
616 test = Test5(dut, test5_resultfn)
617 run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd")
618
619 print ("test 6")
620 dut = ExampleLTPipeline()
621 test = Test5(dut, test6_resultfn)
622 run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
623
624 ports = [dut.p.i_valid, dut.n.i_ready,
625 dut.n.o_valid, dut.p.o_ready] + \
626 list(dut.p.i_data) + [dut.n.o_data]
627 vl = rtlil.convert(dut, ports=ports)
628 with open("test_ltcomb_pipe.il", "w") as f:
629 f.write(vl)
630
631 print ("test 7")
632 dut = ExampleAddRecordPipe()
633 data=data_dict()
634 test = Test5(dut, test7_resultfn, data=data)
635 run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
636
637 ports = [dut.p.i_valid, dut.n.i_ready,
638 dut.n.o_valid, dut.p.o_ready,
639 dut.p.i_data.src1, dut.p.i_data.src2,
640 dut.n.o_data.src1, dut.n.o_data.src2]
641 vl = rtlil.convert(dut, ports=ports)
642 with open("test_recordcomb_pipe.il", "w") as f:
643 f.write(vl)
644
645 print ("test 8")
646 dut = ExampleBufPipeAddClass()
647 data=data_2op()
648 test = Test5(dut, test8_resultfn, data=data)
649 run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe8.vcd")
650
651 print ("test 9")
652 dut = ExampleBufPipeChain2()
653 ports = [dut.p.i_valid, dut.n.i_ready,
654 dut.n.o_valid, dut.p.o_ready] + \
655 [dut.p.i_data] + [dut.n.o_data]
656 vl = rtlil.convert(dut, ports=ports)
657 with open("test_bufpipechain2.il", "w") as f:
658 f.write(vl)
659
660 data = data_chain2()
661 test = Test5(dut, test9_resultfn, data=data)
662 run_simulation(dut, [test.send, test.rcv],
663 vcd_name="test_bufpipechain2.vcd")
664
665 print ("test 10")
666 dut = ExampleLTBufferedPipeDerived()
667 test = Test5(dut, test6_resultfn)
668 run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd")
669 vl = rtlil.convert(dut, ports=ports)
670 with open("test_ltbufpipe10.il", "w") as f:
671 f.write(vl)
672
673 print ("test 11")
674 dut = ExampleAddRecordPlaceHolderPipe()
675 data=data_placeholder()
676 test = Test5(dut, test11_resultfn, data=data)
677 run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
678
679