1 """ Unit tests for Buffered and Unbuffered pipelines
3 contains useful worked examples of how to use the Pipeline API,
6 * Combinatorial Stage "Chaining"
7 * class-based data stages
8 * nmigen module-based data stages
9 * special nmigen module-based data stage, where the stage *is* the module
10 * Record-based data stages
11 * static-class data stages
12 * multi-stage pipelines (and how to connect them)
13 * how to *use* the pipelines (see Test5) - how to get data in and out
17 from nmigen
import Module
, Signal
, Mux
, Const
18 from nmigen
.hdl
.rec
import Record
19 from nmigen
.compat
.sim
import run_simulation
20 from nmigen
.cli
import verilog
, rtlil
22 from example_buf_pipe
import ExampleBufPipe
, ExampleBufPipeAdd
23 from example_buf_pipe
import ExamplePipeline
, UnbufferedPipeline
24 from example_buf_pipe
import ExampleStageCls
25 from example_buf_pipe
import PrevControl
, NextControl
, BufferedPipeline
26 from example_buf_pipe
import StageChain
, ControlBase
, StageCls
27 from singlepipe
import UnbufferedPipeline2
29 from random
import randint
, seed
34 def check_o_n_valid(dut
, val
):
35 o_n_valid
= yield dut
.n
.o_valid
36 assert o_n_valid
== val
38 def check_o_n_valid2(dut
, val
):
39 o_n_valid
= yield dut
.n
.o_valid
40 assert o_n_valid
== val
44 #yield dut.i_p_rst.eq(1)
45 yield dut
.n
.i_ready
.eq(0)
46 yield dut
.p
.o_ready
.eq(0)
49 #yield dut.i_p_rst.eq(0)
50 yield dut
.n
.i_ready
.eq(1)
51 yield dut
.p
.i_data
.eq(5)
52 yield dut
.p
.i_valid
.eq(1)
55 yield dut
.p
.i_data
.eq(7)
56 yield from check_o_n_valid(dut
, 0) # effects of i_p_valid delayed
58 yield from check_o_n_valid(dut
, 1) # ok *now* i_p_valid effect is felt
60 yield dut
.p
.i_data
.eq(2)
62 yield dut
.n
.i_ready
.eq(0) # begin going into "stall" (next stage says ready)
63 yield dut
.p
.i_data
.eq(9)
65 yield dut
.p
.i_valid
.eq(0)
66 yield dut
.p
.i_data
.eq(12)
68 yield dut
.p
.i_data
.eq(32)
69 yield dut
.n
.i_ready
.eq(1)
71 yield from check_o_n_valid(dut
, 1) # buffer still needs to output
73 yield from check_o_n_valid(dut
, 1) # buffer still needs to output
75 yield from check_o_n_valid(dut
, 0) # buffer outputted, *now* we're done.
80 #yield dut.p.i_rst.eq(1)
81 yield dut
.n
.i_ready
.eq(0)
82 #yield dut.p.o_ready.eq(0)
85 #yield dut.p.i_rst.eq(0)
86 yield dut
.n
.i_ready
.eq(1)
87 yield dut
.p
.i_data
.eq(5)
88 yield dut
.p
.i_valid
.eq(1)
91 yield dut
.p
.i_data
.eq(7)
92 yield from check_o_n_valid2(dut
, 0) # effects of i_p_valid delayed 2 clocks
94 yield from check_o_n_valid2(dut
, 0) # effects of i_p_valid delayed 2 clocks
96 yield dut
.p
.i_data
.eq(2)
98 yield from check_o_n_valid2(dut
, 1) # ok *now* i_p_valid effect is felt
99 yield dut
.n
.i_ready
.eq(0) # begin going into "stall" (next stage says ready)
100 yield dut
.p
.i_data
.eq(9)
102 yield dut
.p
.i_valid
.eq(0)
103 yield dut
.p
.i_data
.eq(12)
105 yield dut
.p
.i_data
.eq(32)
106 yield dut
.n
.i_ready
.eq(1)
108 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
110 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
112 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
114 yield from check_o_n_valid2(dut
, 0) # buffer outputted, *now* we're done.
121 def __init__(self
, dut
, resultfn
):
123 self
.resultfn
= resultfn
125 for i
in range(num_tests
):
126 #data.append(randint(0, 1<<16-1))
127 self
.data
.append(i
+1)
132 while self
.o
!= len(self
.data
):
133 send_range
= randint(0, 3)
134 for j
in range(randint(1,10)):
138 send
= randint(0, send_range
) != 0
139 o_p_ready
= yield self
.dut
.p
.o_ready
143 if send
and self
.i
!= len(self
.data
):
144 yield self
.dut
.p
.i_valid
.eq(1)
145 yield self
.dut
.p
.i_data
.eq(self
.data
[self
.i
])
148 yield self
.dut
.p
.i_valid
.eq(0)
152 while self
.o
!= len(self
.data
):
153 stall_range
= randint(0, 3)
154 for j
in range(randint(1,10)):
155 stall
= randint(0, stall_range
) != 0
156 yield self
.dut
.n
.i_ready
.eq(stall
)
158 o_n_valid
= yield self
.dut
.n
.o_valid
159 i_n_ready
= yield self
.dut
.n
.i_ready_test
160 if not o_n_valid
or not i_n_ready
:
162 o_data
= yield self
.dut
.n
.o_data
163 self
.resultfn(o_data
, self
.data
[self
.o
], self
.i
, self
.o
)
165 if self
.o
== len(self
.data
):
168 def test3_resultfn(o_data
, expected
, i
, o
):
169 assert o_data
== expected
+ 1, \
170 "%d-%d data %x not match %x\n" \
171 % (i
, o
, o_data
, expected
)
173 def data_placeholder():
175 for i
in range(num_tests
):
177 d
.src1
= randint(0, 1<<16-1)
178 d
.src2
= randint(0, 1<<16-1)
184 for i
in range(num_tests
):
185 data
.append({'src1': randint(0, 1<<16-1),
186 'src2': randint(0, 1<<16-1)})
191 def __init__(self
, dut
, resultfn
, data
=None, stage_ctl
=False):
193 self
.resultfn
= resultfn
194 self
.stage_ctl
= stage_ctl
199 for i
in range(num_tests
):
200 self
.data
.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
205 while self
.o
!= len(self
.data
):
206 send_range
= randint(0, 3)
207 for j
in range(randint(1,10)):
211 send
= randint(0, send_range
) != 0
213 o_p_ready
= yield self
.dut
.p
.o_ready
217 if send
and self
.i
!= len(self
.data
):
218 yield self
.dut
.p
.i_valid
.eq(1)
219 for v
in self
.dut
.set_input(self
.data
[self
.i
]):
223 yield self
.dut
.p
.i_valid
.eq(0)
227 while self
.o
!= len(self
.data
):
228 stall_range
= randint(0, 3)
229 for j
in range(randint(1,10)):
230 ready
= randint(0, stall_range
) != 0
232 yield self
.dut
.n
.i_ready
.eq(ready
)
234 o_n_valid
= yield self
.dut
.n
.o_valid
235 i_n_ready
= yield self
.dut
.n
.i_ready_test
236 if not o_n_valid
or not i_n_ready
:
238 if isinstance(self
.dut
.n
.o_data
, Record
):
240 dod
= self
.dut
.n
.o_data
241 for k
, v
in dod
.fields
.items():
244 o_data
= yield self
.dut
.n
.o_data
245 self
.resultfn(o_data
, self
.data
[self
.o
], self
.i
, self
.o
)
247 if self
.o
== len(self
.data
):
250 def test5_resultfn(o_data
, expected
, i
, o
):
251 res
= expected
[0] + expected
[1]
252 assert o_data
== res
, \
253 "%d-%d data %x not match %s\n" \
254 % (i
, o
, o_data
, repr(expected
))
258 for i
in range(num_tests
):
259 #data.append(randint(0, 1<<16-1))
264 stall
= randint(0, 3) != 0
265 send
= randint(0, 5) != 0
266 yield dut
.n
.i_ready
.eq(stall
)
267 o_p_ready
= yield dut
.p
.o_ready
269 if send
and i
!= len(data
):
270 yield dut
.p
.i_valid
.eq(1)
271 yield dut
.p
.i_data
.eq(data
[i
])
274 yield dut
.p
.i_valid
.eq(0)
276 o_n_valid
= yield dut
.n
.o_valid
277 i_n_ready
= yield dut
.n
.i_ready_test
278 if o_n_valid
and i_n_ready
:
279 o_data
= yield dut
.n
.o_data
280 assert o_data
== data
[o
] + 2, "%d-%d data %x not match %x\n" \
281 % (i
, o
, o_data
, data
[o
])
286 ######################################################################
288 ######################################################################
290 class ExampleBufPipe2(ControlBase
):
291 """ Example of how to do chained pipeline stages.
294 def elaborate(self
, platform
):
297 pipe1
= ExampleBufPipe()
298 pipe2
= ExampleBufPipe()
300 m
.submodules
.pipe1
= pipe1
301 m
.submodules
.pipe2
= pipe2
303 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
308 ######################################################################
310 ######################################################################
312 class ExampleBufPipeChain2(BufferedPipeline
):
313 """ connects two stages together as a *single* combinatorial stage.
316 stage1
= ExampleStageCls()
317 stage2
= ExampleStageCls()
318 combined
= StageChain([stage1
, stage2
])
319 BufferedPipeline
.__init
__(self
, combined
)
324 for i
in range(num_tests
):
325 data
.append(randint(0, 1<<16-2))
329 def test9_resultfn(o_data
, expected
, i
, o
):
331 assert o_data
== res
, \
332 "%d-%d received data %x not match expected %x\n" \
333 % (i
, o
, o_data
, res
)
336 ######################################################################
338 ######################################################################
341 def __init__(self
, width
, signed
):
343 self
.src1
= Signal((width
, signed
), name
="src1")
344 self
.src2
= Signal((width
, signed
), name
="src2")
345 self
.output
= Signal(width
, name
="out")
347 def elaborate(self
, platform
):
348 self
.m
.d
.comb
+= self
.output
.eq(Mux(self
.src1
< self
.src2
, 1, 0))
352 class LTStage(StageCls
):
353 """ module-based stage example
356 self
.slt
= SetLessThan(16, True)
359 return (Signal(16, name
="sig1"), Signal(16, "sig2"))
362 return Signal(16, "out")
364 def setup(self
, m
, i
):
366 m
.submodules
.slt
= self
.slt
367 m
.d
.comb
+= self
.slt
.src1
.eq(i
[0])
368 m
.d
.comb
+= self
.slt
.src2
.eq(i
[1])
369 m
.d
.comb
+= self
.o
.eq(self
.slt
.output
)
371 def process(self
, i
):
375 class LTStageDerived(SetLessThan
, StageCls
):
376 """ special version of a nmigen module where the module is also a stage
378 shows that you don't actually need to combinatorially connect
379 to the outputs, or add the module as a submodule: just return
380 the module output parameter(s) from the Stage.process() function
384 SetLessThan
.__init
__(self
, 16, True)
387 return (Signal(16), Signal(16))
392 def setup(self
, m
, i
):
393 m
.submodules
.slt
= self
394 m
.d
.comb
+= self
.src1
.eq(i
[0])
395 m
.d
.comb
+= self
.src2
.eq(i
[1])
397 def process(self
, i
):
401 class ExampleLTPipeline(UnbufferedPipeline
):
402 """ an example of how to use the unbuffered pipeline.
407 UnbufferedPipeline
.__init
__(self
, stage
)
410 class ExampleLTBufferedPipeDerived(BufferedPipeline
):
411 """ an example of how to use the buffered pipeline.
415 stage
= LTStageDerived()
416 BufferedPipeline
.__init
__(self
, stage
)
419 def test6_resultfn(o_data
, expected
, i
, o
):
420 res
= 1 if expected
[0] < expected
[1] else 0
421 assert o_data
== res
, \
422 "%d-%d data %x not match %s\n" \
423 % (i
, o
, o_data
, repr(expected
))
426 ######################################################################
428 ######################################################################
430 class ExampleAddRecordStage(StageCls
):
431 """ example use of a Record
434 record_spec
= [('src1', 16), ('src2', 16)]
436 """ returns a Record using the specification
438 return Record(self
.record_spec
)
441 return Record(self
.record_spec
)
443 def process(self
, i
):
444 """ process the input data, returning a dictionary with key names
445 that exactly match the Record's attributes.
447 return {'src1': i
.src1
+ 1,
450 ######################################################################
452 ######################################################################
454 class ExampleAddRecordPlaceHolderStage(StageCls
):
455 """ example use of a Record, with a placeholder as the processing result
458 record_spec
= [('src1', 16), ('src2', 16)]
460 """ returns a Record using the specification
462 return Record(self
.record_spec
)
465 return Record(self
.record_spec
)
467 def process(self
, i
):
468 """ process the input data, returning a PlaceHolder class instance
469 with attributes that exactly match those of the Record.
477 class PlaceHolder
: pass
480 class ExampleAddRecordPipe(UnbufferedPipeline
):
481 """ an example of how to use the combinatorial pipeline.
485 stage
= ExampleAddRecordStage()
486 UnbufferedPipeline
.__init
__(self
, stage
)
489 def test7_resultfn(o_data
, expected
, i
, o
):
490 res
= (expected
['src1'] + 1, expected
['src2'] + 1)
491 assert o_data
['src1'] == res
[0] and o_data
['src2'] == res
[1], \
492 "%d-%d data %s not match %s\n" \
493 % (i
, o
, repr(o_data
), repr(expected
))
496 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline
):
497 """ an example of how to use the combinatorial pipeline.
501 stage
= ExampleAddRecordPlaceHolderStage()
502 UnbufferedPipeline
.__init
__(self
, stage
)
505 def test11_resultfn(o_data
, expected
, i
, o
):
506 res1
= expected
.src1
+ 1
507 res2
= expected
.src2
+ 1
508 assert o_data
['src1'] == res1
and o_data
['src2'] == res2
, \
509 "%d-%d data %s not match %s\n" \
510 % (i
, o
, repr(o_data
), repr(expected
))
513 ######################################################################
515 ######################################################################
518 class Example2OpClass
:
519 """ an example of a class used to store 2 operands.
520 requires an eq function, to conform with the pipeline stage API
524 self
.op1
= Signal(16)
525 self
.op2
= Signal(16)
528 return [self
.op1
.eq(i
.op1
), self
.op2
.eq(i
.op2
)]
531 class ExampleAddClassStage(StageCls
):
532 """ an example of how to use the buffered pipeline, as a class instance
536 """ returns an instance of an Example2OpClass.
538 return Example2OpClass()
541 """ returns an output signal which will happen to contain the sum
546 def process(self
, i
):
547 """ process the input data (sums the values in the tuple) and returns it
552 class ExampleBufPipeAddClass(BufferedPipeline
):
553 """ an example of how to use the buffered pipeline, using a class instance
557 addstage
= ExampleAddClassStage()
558 BufferedPipeline
.__init
__(self
, addstage
)
562 """ the eq function, called by set_input, needs an incoming object
563 that conforms to the Example2OpClass.eq function requirements
564 easiest way to do that is to create a class that has the exact
565 same member layout (self.op1, self.op2) as Example2OpClass
567 def __init__(self
, op1
, op2
):
572 def test8_resultfn(o_data
, expected
, i
, o
):
573 res
= expected
.op1
+ expected
.op2
# these are a TestInputAdd instance
574 assert o_data
== res
, \
575 "%d-%d data %x not match %s\n" \
576 % (i
, o
, o_data
, repr(expected
))
580 for i
in range(num_tests
):
581 data
.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
585 ######################################################################
587 ######################################################################
589 class ExampleStageDelayCls(StageCls
):
590 """ an example of how to use the buffered pipeline, in a static class
594 def __init__(self
, valid_trigger
=2):
595 self
.count
= Signal(2)
596 self
.valid_trigger
= valid_trigger
599 return Signal(16, name
="example_input_signal")
602 return Signal(16, name
="example_output_signal")
606 return (self
.count
== 1)# | (self.count == 3)
611 return self
.count
== self
.valid_trigger
614 def process(self
, i
):
615 """ process the input data and returns it (adds 1)
619 def elaborate(self
, platform
):
621 m
.d
.sync
+= self
.count
.eq(self
.count
+ 1)
625 class ExampleBufDelayedPipe(BufferedPipeline
):
628 stage
= ExampleStageDelayCls()
629 BufferedPipeline
.__init
__(self
, stage
, stage_ctl
=True)
631 def elaborate(self
, platform
):
632 m
= BufferedPipeline
.elaborate(self
, platform
)
633 m
.submodules
.stage
= self
.stage
639 for i
in range(num_tests
):
640 #data.append(1<<((i*2)%15))
641 data
.append(randint(0, 1<<16-2))
642 print (hex(data
[-1]))
646 def test12_resultfn(o_data
, expected
, i
, o
):
648 assert o_data
== res
, \
649 "%d-%d data %x not match %x\n" \
650 % (i
, o
, o_data
, res
)
653 ######################################################################
655 ######################################################################
657 class ExampleUnBufDelayedPipe(UnbufferedPipeline
):
660 stage
= ExampleStageDelayCls()
661 UnbufferedPipeline
.__init
__(self
, stage
, stage_ctl
=True)
663 def elaborate(self
, platform
):
664 m
= UnbufferedPipeline
.elaborate(self
, platform
)
665 m
.submodules
.stage
= self
.stage
668 ######################################################################
670 ######################################################################
672 class ExampleBufPipe3(ControlBase
):
673 """ Example of how to do delayed pipeline, where the stage signals
677 def elaborate(self
, platform
):
678 m
= ControlBase
._elaborate
(self
, platform
)
680 pipe1
= ExampleBufDelayedPipe()
681 pipe2
= ExampleBufPipe()
683 m
.submodules
.pipe1
= pipe1
684 m
.submodules
.pipe2
= pipe2
686 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
690 ######################################################################
692 ######################################################################
694 class ExampleBufModeAdd1Pipe(BufferedPipeline
):
697 stage
= ExampleStageCls()
698 BufferedPipeline
.__init
__(self
, stage
, buffermode
=False)
701 class ExampleBufModeUnBufPipe(ControlBase
):
703 def elaborate(self
, platform
):
704 m
= ControlBase
._elaborate
(self
, platform
)
706 pipe1
= ExampleBufModeAdd1Pipe()
707 pipe2
= ExampleBufAdd1Pipe()
709 m
.submodules
.pipe1
= pipe1
710 m
.submodules
.pipe2
= pipe2
712 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
717 ######################################################################
718 # Test 999 - XXX FAILS
719 # http://bugs.libre-riscv.org/show_bug.cgi?id=57
720 ######################################################################
722 class ExampleBufAdd1Pipe(BufferedPipeline
):
725 stage
= ExampleStageCls()
726 BufferedPipeline
.__init
__(self
, stage
)
729 class ExampleUnBufAdd1Pipe(UnbufferedPipeline
):
732 stage
= ExampleStageCls()
733 UnbufferedPipeline
.__init
__(self
, stage
)
736 class ExampleBufUnBufPipe(ControlBase
):
738 def elaborate(self
, platform
):
739 m
= ControlBase
._elaborate
(self
, platform
)
741 # XXX currently fails: any other permutation works fine.
742 # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
743 # also fails using UnbufferedPipeline as well
744 #pipe1 = ExampleUnBufAdd1Pipe()
745 #pipe2 = ExampleBufAdd1Pipe()
746 pipe1
= ExampleBufAdd1Pipe()
747 pipe2
= ExampleUnBufAdd1Pipe()
749 m
.submodules
.pipe1
= pipe1
750 m
.submodules
.pipe2
= pipe2
752 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
757 ######################################################################
759 ######################################################################
763 if __name__
== '__main__':
765 dut
= ExampleBufPipe()
766 run_simulation(dut
, testbench(dut
), vcd_name
="test_bufpipe.vcd")
769 dut
= ExampleBufPipe2()
770 run_simulation(dut
, testbench2(dut
), vcd_name
="test_bufpipe2.vcd")
771 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
772 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
773 [dut
.p
.i_data
] + [dut
.n
.o_data
]
774 vl
= rtlil
.convert(dut
, ports
=ports
)
775 with
open("test_bufpipe2.il", "w") as f
:
780 dut
= ExampleBufPipe()
781 test
= Test3(dut
, test3_resultfn
)
782 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe3.vcd")
785 dut
= ExamplePipeline()
786 test
= Test3(dut
, test3_resultfn
)
787 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_combpipe3.vcd")
790 dut
= ExampleBufPipe2()
791 run_simulation(dut
, testbench4(dut
), vcd_name
="test_bufpipe4.vcd")
794 dut
= ExampleBufPipeAdd()
795 test
= Test5(dut
, test5_resultfn
, stage_ctl
=True)
796 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe5.vcd")
799 dut
= ExampleLTPipeline()
800 test
= Test5(dut
, test6_resultfn
)
801 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_ltcomb6.vcd")
803 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
804 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
805 list(dut
.p
.i_data
) + [dut
.n
.o_data
]
806 vl
= rtlil
.convert(dut
, ports
=ports
)
807 with
open("test_ltcomb_pipe.il", "w") as f
:
811 dut
= ExampleAddRecordPipe()
813 test
= Test5(dut
, test7_resultfn
, data
=data
)
814 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord.vcd")
816 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
817 dut
.n
.o_valid
, dut
.p
.o_ready
,
818 dut
.p
.i_data
.src1
, dut
.p
.i_data
.src2
,
819 dut
.n
.o_data
.src1
, dut
.n
.o_data
.src2
]
820 vl
= rtlil
.convert(dut
, ports
=ports
)
821 with
open("test_recordcomb_pipe.il", "w") as f
:
825 dut
= ExampleBufPipeAddClass()
827 test
= Test5(dut
, test8_resultfn
, data
=data
)
828 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe8.vcd")
831 dut
= ExampleBufPipeChain2()
832 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
833 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
834 [dut
.p
.i_data
] + [dut
.n
.o_data
]
835 vl
= rtlil
.convert(dut
, ports
=ports
)
836 with
open("test_bufpipechain2.il", "w") as f
:
840 test
= Test5(dut
, test9_resultfn
, data
=data
)
841 run_simulation(dut
, [test
.send
, test
.rcv
],
842 vcd_name
="test_bufpipechain2.vcd")
845 dut
= ExampleLTBufferedPipeDerived()
846 test
= Test5(dut
, test6_resultfn
)
847 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_ltbufpipe10.vcd")
848 vl
= rtlil
.convert(dut
, ports
=ports
)
849 with
open("test_ltbufpipe10.il", "w") as f
:
853 dut
= ExampleAddRecordPlaceHolderPipe()
854 data
=data_placeholder()
855 test
= Test5(dut
, test11_resultfn
, data
=data
)
856 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord.vcd")
860 dut
= ExampleBufDelayedPipe()
862 test
= Test5(dut
, test12_resultfn
, data
=data
)
863 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe12.vcd")
864 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
865 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
866 [dut
.p
.i_data
] + [dut
.n
.o_data
]
867 vl
= rtlil
.convert(dut
, ports
=ports
)
868 with
open("test_bufpipe12.il", "w") as f
:
872 dut
= ExampleUnBufDelayedPipe()
874 test
= Test5(dut
, test12_resultfn
, data
=data
)
875 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_unbufpipe13.vcd")
876 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
877 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
878 [dut
.p
.i_data
] + [dut
.n
.o_data
]
879 vl
= rtlil
.convert(dut
, ports
=ports
)
880 with
open("test_unbufpipe13.il", "w") as f
:
884 dut
= ExampleBufPipe3()
886 test
= Test5(dut
, test9_resultfn
, data
=data
)
887 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe14.vcd")
888 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
889 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
890 [dut
.p
.i_data
] + [dut
.n
.o_data
]
891 vl
= rtlil
.convert(dut
, ports
=ports
)
892 with
open("test_bufpipe14.il", "w") as f
:
896 dut
= ExampleBufModeUnBufPipe()
898 test
= Test5(dut
, test9_resultfn
, data
=data
)
899 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf999.vcd")
900 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
901 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
902 [dut
.p
.i_data
] + [dut
.n
.o_data
]
903 vl
= rtlil
.convert(dut
, ports
=ports
)
904 with
open("test_bufunbuf999.il", "w") as f
:
907 print ("test 999 (expected to fail, which is a bug)")
908 dut
= ExampleBufUnBufPipe()
910 test
= Test5(dut
, test9_resultfn
, data
=data
)
911 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf999.vcd")
912 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
913 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
914 [dut
.p
.i_data
] + [dut
.n
.o_data
]
915 vl
= rtlil
.convert(dut
, ports
=ports
)
916 with
open("test_bufunbuf999.il", "w") as f
: