src/add/test_buf_pipe.py

   1 """ Unit tests for Buffered and Unbuffered pipelines
   2
   3     contains useful worked examples of how to use the Pipeline API,
   4     including:
   5
   6     * Combinatorial Stage "Chaining"
   7     * class-based data stages
   8     * nmigen module-based data stages
   9     * special nmigen module-based data stage, where the stage *is* the module
  10     * Record-based data stages
  11     * static-class data stages
  12     * multi-stage pipelines (and how to connect them)
  13     * how to *use* the pipelines (see Test5) - how to get data in and out
  14
  15 """
  16
  17 from nmigen import Module, Signal, Mux, Const
  18 from nmigen.hdl.rec import Record
  19 from nmigen.compat.sim import run_simulation
  20 from nmigen.cli import verilog, rtlil
  21
  22 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
  23 from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
  24 from example_buf_pipe import ExampleStageCls
  25 from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
  26 from example_buf_pipe import StageChain, ControlBase, StageCls
  27
  28 from random import randint
  29
  30
  31 def check_o_n_valid(dut, val):
  32     o_n_valid = yield dut.n.o_valid
  33     assert o_n_valid == val
  34
  35 def check_o_n_valid2(dut, val):
  36     o_n_valid = yield dut.n.o_valid
  37     assert o_n_valid == val
  38
  39
  40 def testbench(dut):
  41     #yield dut.i_p_rst.eq(1)
  42     yield dut.n.i_ready.eq(0)
  43     yield dut.p.o_ready.eq(0)
  44     yield
  45     yield
  46     #yield dut.i_p_rst.eq(0)
  47     yield dut.n.i_ready.eq(1)
  48     yield dut.p.i_data.eq(5)
  49     yield dut.p.i_valid.eq(1)
  50     yield
  51
  52     yield dut.p.i_data.eq(7)
  53     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
  54     yield
  55     yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
  56
  57     yield dut.p.i_data.eq(2)
  58     yield
  59     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
  60     yield dut.p.i_data.eq(9)
  61     yield
  62     yield dut.p.i_valid.eq(0)
  63     yield dut.p.i_data.eq(12)
  64     yield
  65     yield dut.p.i_data.eq(32)
  66     yield dut.n.i_ready.eq(1)
  67     yield
  68     yield from check_o_n_valid(dut, 1) # buffer still needs to output
  69     yield
  70     yield from check_o_n_valid(dut, 1) # buffer still needs to output
  71     yield
  72     yield from check_o_n_valid(dut, 0) # buffer outputted, *now* we're done.
  73     yield
  74
  75
  76 def testbench2(dut):
  77     #yield dut.p.i_rst.eq(1)
  78     yield dut.n.i_ready.eq(0)
  79     #yield dut.p.o_ready.eq(0)
  80     yield
  81     yield
  82     #yield dut.p.i_rst.eq(0)
  83     yield dut.n.i_ready.eq(1)
  84     yield dut.p.i_data.eq(5)
  85     yield dut.p.i_valid.eq(1)
  86     yield
  87
  88     yield dut.p.i_data.eq(7)
  89     yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
  90     yield
  91     yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
  92
  93     yield dut.p.i_data.eq(2)
  94     yield
  95     yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
  96     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
  97     yield dut.p.i_data.eq(9)
  98     yield
  99     yield dut.p.i_valid.eq(0)
 100     yield dut.p.i_data.eq(12)
 101     yield
 102     yield dut.p.i_data.eq(32)
 103     yield dut.n.i_ready.eq(1)
 104     yield
 105     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
 106     yield
 107     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
 108     yield
 109     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
 110     yield
 111     yield from check_o_n_valid2(dut, 0) # buffer outputted, *now* we're done.
 112     yield
 113     yield
 114     yield
 115
 116
 117 class Test3:
 118     def __init__(self, dut, resultfn):
 119         self.dut = dut
 120         self.resultfn = resultfn
 121         self.data = []
 122         for i in range(num_tests):
 123             #data.append(randint(0, 1<<16-1))
 124             self.data.append(i+1)
 125         self.i = 0
 126         self.o = 0
 127
 128     def send(self):
 129         while self.o != len(self.data):
 130             send_range = randint(0, 3)
 131             for j in range(randint(1,10)):
 132                 if send_range == 0:
 133                     send = True
 134                 else:
 135                     send = randint(0, send_range) != 0
 136                 o_p_ready = yield self.dut.p.o_ready
 137                 if not o_p_ready:
 138                     yield
 139                     continue
 140                 if send and self.i != len(self.data):
 141                     yield self.dut.p.i_valid.eq(1)
 142                     yield self.dut.p.i_data.eq(self.data[self.i])
 143                     self.i += 1
 144                 else:
 145                     yield self.dut.p.i_valid.eq(0)
 146                 yield
 147
 148     def rcv(self):
 149         while self.o != len(self.data):
 150             stall_range = randint(0, 3)
 151             for j in range(randint(1,10)):
 152                 stall = randint(0, stall_range) != 0
 153                 yield self.dut.n.i_ready.eq(stall)
 154                 yield
 155                 o_n_valid = yield self.dut.n.o_valid
 156                 i_n_ready = yield self.dut.n.i_ready_test
 157                 if not o_n_valid or not i_n_ready:
 158                     continue
 159                 o_data = yield self.dut.n.o_data
 160                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
 161                 self.o += 1
 162                 if self.o == len(self.data):
 163                     break
 164
 165 def test3_resultfn(o_data, expected, i, o):
 166     assert o_data == expected + 1, \
 167                 "%d-%d data %x not match %x\n" \
 168                 % (i, o, o_data, expected)
 169
 170 def data_placeholder():
 171         data = []
 172         for i in range(num_tests):
 173             d = PlaceHolder()
 174             d.src1 = randint(0, 1<<16-1)
 175             d.src2 = randint(0, 1<<16-1)
 176             data.append(d)
 177         return data
 178
 179 def data_dict():
 180         data = []
 181         for i in range(num_tests):
 182             data.append({'src1': randint(0, 1<<16-1),
 183                          'src2': randint(0, 1<<16-1)})
 184         return data
 185
 186
 187 class Test5:
 188     def __init__(self, dut, resultfn, data=None, stage_ctl=False):
 189         self.dut = dut
 190         self.resultfn = resultfn
 191         self.stage_ctl = stage_ctl
 192         if data:
 193             self.data = data
 194         else:
 195             self.data = []
 196             for i in range(num_tests):
 197                 self.data.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
 198         self.i = 0
 199         self.o = 0
 200
 201     def send(self):
 202         while self.o != len(self.data):
 203             send_range = randint(0, 3)
 204             for j in range(randint(1,10)):
 205                 if send_range == 0:
 206                     send = True
 207                 else:
 208                     send = randint(0, send_range) != 0
 209                 send = True
 210                 o_p_ready = yield self.dut.p.o_ready
 211                 if not o_p_ready:
 212                     yield
 213                     continue
 214                 if send and self.i != len(self.data):
 215                     yield self.dut.p.i_valid.eq(1)
 216                     for v in self.dut.set_input(self.data[self.i]):
 217                         yield v
 218                     self.i += 1
 219                 else:
 220                     yield self.dut.p.i_valid.eq(0)
 221                 yield
 222
 223     def rcv(self):
 224         while self.o != len(self.data):
 225             stall_range = randint(0, 3)
 226             for j in range(randint(1,10)):
 227                 stall = randint(0, stall_range) != 0
 228                 yield self.dut.n.i_ready.eq(stall)
 229                 yield
 230                 o_n_valid = yield self.dut.n.o_valid
 231                 i_n_ready = yield self.dut.n.i_ready_test
 232                 if not o_n_valid or not i_n_ready:
 233                     continue
 234                 if isinstance(self.dut.n.o_data, Record):
 235                     o_data = {}
 236                     dod = self.dut.n.o_data
 237                     for k, v in dod.fields.items():
 238                         o_data[k] = yield v
 239                 else:
 240                     o_data = yield self.dut.n.o_data
 241                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
 242                 self.o += 1
 243                 if self.o == len(self.data):
 244                     break
 245
 246 def test5_resultfn(o_data, expected, i, o):
 247     res = expected[0] + expected[1]
 248     assert o_data == res, \
 249                 "%d-%d data %x not match %s\n" \
 250                 % (i, o, o_data, repr(expected))
 251
 252 def testbench4(dut):
 253     data = []
 254     for i in range(num_tests):
 255         #data.append(randint(0, 1<<16-1))
 256         data.append(i+1)
 257     i = 0
 258     o = 0
 259     while True:
 260         stall = randint(0, 3) != 0
 261         send = randint(0, 5) != 0
 262         yield dut.n.i_ready.eq(stall)
 263         o_p_ready = yield dut.p.o_ready
 264         if o_p_ready:
 265             if send and i != len(data):
 266                 yield dut.p.i_valid.eq(1)
 267                 yield dut.p.i_data.eq(data[i])
 268                 i += 1
 269             else:
 270                 yield dut.p.i_valid.eq(0)
 271         yield
 272         o_n_valid = yield dut.n.o_valid
 273         i_n_ready = yield dut.n.i_ready_test
 274         if o_n_valid and i_n_ready:
 275             o_data = yield dut.n.o_data
 276             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
 277                                         % (i, o, o_data, data[o])
 278             o += 1
 279             if o == len(data):
 280                 break
 281
 282 ######################################################################
 283 # Test 2 and 4
 284 ######################################################################
 285
 286 class ExampleBufPipe2(ControlBase):
 287     """ Example of how to do chained pipeline stages.
 288     """
 289
 290     def elaborate(self, platform):
 291         m = Module()
 292
 293         pipe1 = ExampleBufPipe()
 294         pipe2 = ExampleBufPipe()
 295
 296         m.submodules.pipe1 = pipe1
 297         m.submodules.pipe2 = pipe2
 298
 299         m.d.comb += self.connect([pipe1, pipe2])
 300
 301         return m
 302
 303
 304 ######################################################################
 305 # Test 9
 306 ######################################################################
 307
 308 class ExampleBufPipeChain2(BufferedPipeline):
 309     """ connects two stages together as a *single* combinatorial stage.
 310     """
 311     def __init__(self):
 312         stage1 = ExampleStageCls()
 313         stage2 = ExampleStageCls()
 314         combined = StageChain([stage1, stage2])
 315         BufferedPipeline.__init__(self, combined)
 316
 317
 318 def data_chain2():
 319         data = []
 320         for i in range(num_tests):
 321             data.append(randint(0, 1<<16-2))
 322         return data
 323
 324
 325 def test9_resultfn(o_data, expected, i, o):
 326     res = expected + 2
 327     assert o_data == res, \
 328                 "%d-%d data %x not match %s\n" \
 329                 % (i, o, o_data, repr(expected))
 330
 331
 332 ######################################################################
 333 # Test 6 and 10
 334 ######################################################################
 335
 336 class SetLessThan:
 337     def __init__(self, width, signed):
 338         self.m = Module()
 339         self.src1 = Signal((width, signed), name="src1")
 340         self.src2 = Signal((width, signed), name="src2")
 341         self.output = Signal(width, name="out")
 342
 343     def elaborate(self, platform):
 344         self.m.d.comb += self.output.eq(Mux(self.src1 < self.src2, 1, 0))
 345         return self.m
 346
 347
 348 class LTStage(StageCls):
 349     """ module-based stage example
 350     """
 351     def __init__(self):
 352         self.slt = SetLessThan(16, True)
 353
 354     def ispec(self):
 355         return (Signal(16, name="sig1"), Signal(16, "sig2"))
 356
 357     def ospec(self):
 358         return Signal(16, "out")
 359
 360     def setup(self, m, i):
 361         self.o = Signal(16)
 362         m.submodules.slt = self.slt
 363         m.d.comb += self.slt.src1.eq(i[0])
 364         m.d.comb += self.slt.src2.eq(i[1])
 365         m.d.comb += self.o.eq(self.slt.output)
 366
 367     def process(self, i):
 368         return self.o
 369
 370
 371 class LTStageDerived(SetLessThan, StageCls):
 372     """ special version of a nmigen module where the module is also a stage
 373
 374         shows that you don't actually need to combinatorially connect
 375         to the outputs, or add the module as a submodule: just return
 376         the module output parameter(s) from the Stage.process() function
 377     """
 378
 379     def __init__(self):
 380         SetLessThan.__init__(self, 16, True)
 381
 382     def ispec(self):
 383         return (Signal(16), Signal(16))
 384
 385     def ospec(self):
 386         return Signal(16)
 387
 388     def setup(self, m, i):
 389         m.submodules.slt = self
 390         m.d.comb += self.src1.eq(i[0])
 391         m.d.comb += self.src2.eq(i[1])
 392
 393     def process(self, i):
 394         return self.output
 395
 396
 397 class ExampleLTPipeline(UnbufferedPipeline):
 398     """ an example of how to use the unbuffered pipeline.
 399     """
 400
 401     def __init__(self):
 402         stage = LTStage()
 403         UnbufferedPipeline.__init__(self, stage)
 404
 405
 406 class ExampleLTBufferedPipeDerived(BufferedPipeline):
 407     """ an example of how to use the buffered pipeline.
 408     """
 409
 410     def __init__(self):
 411         stage = LTStageDerived()
 412         BufferedPipeline.__init__(self, stage)
 413
 414
 415 def test6_resultfn(o_data, expected, i, o):
 416     res = 1 if expected[0] < expected[1] else 0
 417     assert o_data == res, \
 418                 "%d-%d data %x not match %s\n" \
 419                 % (i, o, o_data, repr(expected))
 420
 421
 422 ######################################################################
 423 # Test 7
 424 ######################################################################
 425
 426 class ExampleAddRecordStage(StageCls):
 427     """ example use of a Record
 428     """
 429
 430     record_spec = [('src1', 16), ('src2', 16)]
 431     def ispec(self):
 432         """ returns a Record using the specification
 433         """
 434         return Record(self.record_spec)
 435
 436     def ospec(self):
 437         return Record(self.record_spec)
 438
 439     def process(self, i):
 440         """ process the input data, returning a dictionary with key names
 441             that exactly match the Record's attributes.
 442         """
 443         return {'src1': i.src1 + 1,
 444                 'src2': i.src2 + 1}
 445
 446 ######################################################################
 447 # Test 11
 448 ######################################################################
 449
 450 class ExampleAddRecordPlaceHolderStage(StageCls):
 451     """ example use of a Record, with a placeholder as the processing result
 452     """
 453
 454     record_spec = [('src1', 16), ('src2', 16)]
 455     def ispec(self):
 456         """ returns a Record using the specification
 457         """
 458         return Record(self.record_spec)
 459
 460     def ospec(self):
 461         return Record(self.record_spec)
 462
 463     def process(self, i):
 464         """ process the input data, returning a PlaceHolder class instance
 465             with attributes that exactly match those of the Record.
 466         """
 467         o = PlaceHolder()
 468         o.src1 = i.src1 + 1
 469         o.src2 = i.src2 + 1
 470         return o
 471
 472
 473 class PlaceHolder: pass
 474
 475
 476 class ExampleAddRecordPipe(UnbufferedPipeline):
 477     """ an example of how to use the combinatorial pipeline.
 478     """
 479
 480     def __init__(self):
 481         stage = ExampleAddRecordStage()
 482         UnbufferedPipeline.__init__(self, stage)
 483
 484
 485 def test7_resultfn(o_data, expected, i, o):
 486     res = (expected['src1'] + 1, expected['src2'] + 1)
 487     assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \
 488                 "%d-%d data %s not match %s\n" \
 489                 % (i, o, repr(o_data), repr(expected))
 490
 491
 492 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
 493     """ an example of how to use the combinatorial pipeline.
 494     """
 495
 496     def __init__(self):
 497         stage = ExampleAddRecordPlaceHolderStage()
 498         UnbufferedPipeline.__init__(self, stage)
 499
 500
 501 def test11_resultfn(o_data, expected, i, o):
 502     res1 = expected.src1 + 1
 503     res2 = expected.src2 + 1
 504     assert o_data['src1'] == res1 and o_data['src2'] == res2, \
 505                 "%d-%d data %s not match %s\n" \
 506                 % (i, o, repr(o_data), repr(expected))
 507
 508
 509 ######################################################################
 510 # Test 8
 511 ######################################################################
 512
 513
 514 class Example2OpClass:
 515     """ an example of a class used to store 2 operands.
 516         requires an eq function, to conform with the pipeline stage API
 517     """
 518
 519     def __init__(self):
 520         self.op1 = Signal(16)
 521         self.op2 = Signal(16)
 522
 523     def eq(self, i):
 524         return [self.op1.eq(i.op1), self.op2.eq(i.op2)]
 525
 526
 527 class ExampleAddClassStage(StageCls):
 528     """ an example of how to use the buffered pipeline, as a class instance
 529     """
 530
 531     def ispec(self):
 532         """ returns an instance of an Example2OpClass.
 533         """
 534         return Example2OpClass()
 535
 536     def ospec(self):
 537         """ returns an output signal which will happen to contain the sum
 538             of the two inputs
 539         """
 540         return Signal(16)
 541
 542     def process(self, i):
 543         """ process the input data (sums the values in the tuple) and returns it
 544         """
 545         return i.op1 + i.op2
 546
 547
 548 class ExampleBufPipeAddClass(BufferedPipeline):
 549     """ an example of how to use the buffered pipeline, using a class instance
 550     """
 551
 552     def __init__(self):
 553         addstage = ExampleAddClassStage()
 554         BufferedPipeline.__init__(self, addstage)
 555
 556
 557 class TestInputAdd:
 558     """ the eq function, called by set_input, needs an incoming object
 559         that conforms to the Example2OpClass.eq function requirements
 560         easiest way to do that is to create a class that has the exact
 561         same member layout (self.op1, self.op2) as Example2OpClass
 562     """
 563     def __init__(self, op1, op2):
 564         self.op1 = op1
 565         self.op2 = op2
 566
 567
 568 def test8_resultfn(o_data, expected, i, o):
 569     res = expected.op1 + expected.op2 # these are a TestInputAdd instance
 570     assert o_data == res, \
 571                 "%d-%d data %x not match %s\n" \
 572                 % (i, o, o_data, repr(expected))
 573
 574 def data_2op():
 575         data = []
 576         for i in range(num_tests):
 577             data.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
 578         return data
 579
 580
 581 ######################################################################
 582 # Test 12
 583 ######################################################################
 584
 585 class ExampleStageDelayCls(StageCls):
 586     """ an example of how to use the buffered pipeline, in a static class
 587         fashion
 588     """
 589
 590     def __init__(self):
 591         self.count = Signal(2)
 592
 593     def ispec(self):
 594         return Signal(16, name="example_input_signal")
 595
 596     def ospec(self):
 597         return Signal(16, name="example_output_signal")
 598
 599     @property
 600     def d_ready(self):
 601         return self.count == 2
 602         return Const(1)
 603
 604     @property
 605     def d_valid(self):
 606         return self.count == 0
 607         return Const(1)
 608
 609     def process(self, i):
 610         """ process the input data and returns it (adds 1)
 611         """
 612         return i + 1
 613
 614     def elaborate(self, platform):
 615         m = Module()
 616         m.d.sync += self.count.eq(self.count + 1)
 617         return m
 618
 619
 620 class ExampleBufDelayedPipe(BufferedPipeline):
 621
 622     def __init__(self):
 623         stage = ExampleStageDelayCls()
 624         BufferedPipeline.__init__(self, stage, stage_ctl=True)
 625
 626     def elaborate(self, platform):
 627         m = BufferedPipeline.elaborate(self, platform)
 628         m.submodules.stage = self.stage
 629         return m
 630
 631
 632 class ExampleBufPipe3(ControlBase):
 633     """ Example of how to do delayed pipeline, where the stage signals
 634         whether it is ready.
 635     """
 636
 637     def elaborate(self, platform):
 638         m = ControlBase._elaborate(self, platform)
 639
 640         #pipe1 = ExampleBufPipe()
 641         pipe1 = ExampleBufDelayedPipe()
 642         pipe2 = ExampleBufDelayedPipe()
 643
 644         m.submodules.pipe1 = pipe1
 645         m.submodules.pipe2 = pipe2
 646
 647         m.d.comb += self.connect([pipe1, pipe2])
 648
 649         return m
 650
 651 def data_chain1():
 652         data = []
 653         for i in range(num_tests):
 654             data.append(randint(0, 1<<16-2))
 655         return data
 656
 657
 658 def test12_resultfn(o_data, expected, i, o):
 659     res = expected + 1
 660     assert o_data == res, \
 661                 "%d-%d data %x not match %x\n" \
 662                 % (i, o, o_data, res)
 663
 664
 665 ######################################################################
 666 # Test 13
 667 ######################################################################
 668
 669 class ExampleUnBufDelayedPipe(UnbufferedPipeline):
 670
 671     def __init__(self):
 672         stage = ExampleStageDelayCls()
 673         UnbufferedPipeline.__init__(self, stage, stage_ctl=True)
 674
 675     def elaborate(self, platform):
 676         m = UnbufferedPipeline.elaborate(self, platform)
 677         m.submodules.stage = self.stage
 678         return m
 679
 680 ######################################################################
 681 # Test 999
 682 ######################################################################
 683
 684 class ExampleBufAdd1Pipe(BufferedPipeline):
 685
 686     def __init__(self):
 687         stage = ExampleStageCls()
 688         BufferedPipeline.__init__(self, stage)
 689
 690
 691 class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
 692
 693     def __init__(self):
 694         stage = ExampleStageCls()
 695         UnbufferedPipeline.__init__(self, stage)
 696
 697
 698 class ExampleBufUnBufPipe(ControlBase):
 699     """ Example of how to do delayed pipeline, where the stage signals
 700         whether it is ready.
 701     """
 702
 703     def elaborate(self, platform):
 704         m = ControlBase._elaborate(self, platform)
 705
 706         #pipe1 = ExampleBufPipe()
 707         pipe1 = ExampleBufAdd1Pipe()
 708         pipe2 = ExampleUnBufAdd1Pipe()
 709
 710         m.submodules.pipe1 = pipe1
 711         m.submodules.pipe2 = pipe2
 712
 713         m.d.comb += self.connect([pipe1, pipe2])
 714
 715         return m
 716
 717
 718 ######################################################################
 719 # Unit Tests
 720 ######################################################################
 721
 722 num_tests = 100
 723
 724 if __name__ == '__main__':
 725     print ("test 1")
 726     dut = ExampleBufPipe()
 727     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
 728
 729     print ("test 2")
 730     dut = ExampleBufPipe2()
 731     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
 732     ports = [dut.p.i_valid, dut.n.i_ready,
 733              dut.n.o_valid, dut.p.o_ready] + \
 734              [dut.p.i_data] + [dut.n.o_data]
 735     vl = rtlil.convert(dut, ports=ports)
 736     with open("test_bufpipe2.il", "w") as f:
 737         f.write(vl)
 738
 739
 740     print ("test 3")
 741     dut = ExampleBufPipe()
 742     test = Test3(dut, test3_resultfn)
 743     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
 744
 745     print ("test 3.5")
 746     dut = ExamplePipeline()
 747     test = Test3(dut, test3_resultfn)
 748     run_simulation(dut, [test.send, test.rcv], vcd_name="test_combpipe3.vcd")
 749
 750     print ("test 4")
 751     dut = ExampleBufPipe2()
 752     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
 753
 754     print ("test 5")
 755     dut = ExampleBufPipeAdd()
 756     test = Test5(dut, test5_resultfn, stage_ctl=True)
 757     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd")
 758
 759     print ("test 6")
 760     dut = ExampleLTPipeline()
 761     test = Test5(dut, test6_resultfn)
 762     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
 763
 764     ports = [dut.p.i_valid, dut.n.i_ready,
 765              dut.n.o_valid, dut.p.o_ready] + \
 766              list(dut.p.i_data) + [dut.n.o_data]
 767     vl = rtlil.convert(dut, ports=ports)
 768     with open("test_ltcomb_pipe.il", "w") as f:
 769         f.write(vl)
 770
 771     print ("test 7")
 772     dut = ExampleAddRecordPipe()
 773     data=data_dict()
 774     test = Test5(dut, test7_resultfn, data=data)
 775     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
 776
 777     ports = [dut.p.i_valid, dut.n.i_ready,
 778              dut.n.o_valid, dut.p.o_ready,
 779              dut.p.i_data.src1, dut.p.i_data.src2,
 780              dut.n.o_data.src1, dut.n.o_data.src2]
 781     vl = rtlil.convert(dut, ports=ports)
 782     with open("test_recordcomb_pipe.il", "w") as f:
 783         f.write(vl)
 784
 785     print ("test 8")
 786     dut = ExampleBufPipeAddClass()
 787     data=data_2op()
 788     test = Test5(dut, test8_resultfn, data=data)
 789     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe8.vcd")
 790
 791     print ("test 9")
 792     dut = ExampleBufPipeChain2()
 793     ports = [dut.p.i_valid, dut.n.i_ready,
 794              dut.n.o_valid, dut.p.o_ready] + \
 795              [dut.p.i_data] + [dut.n.o_data]
 796     vl = rtlil.convert(dut, ports=ports)
 797     with open("test_bufpipechain2.il", "w") as f:
 798         f.write(vl)
 799
 800     data = data_chain2()
 801     test = Test5(dut, test9_resultfn, data=data)
 802     run_simulation(dut, [test.send, test.rcv],
 803                         vcd_name="test_bufpipechain2.vcd")
 804
 805     print ("test 10")
 806     dut = ExampleLTBufferedPipeDerived()
 807     test = Test5(dut, test6_resultfn)
 808     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd")
 809     vl = rtlil.convert(dut, ports=ports)
 810     with open("test_ltbufpipe10.il", "w") as f:
 811         f.write(vl)
 812
 813     print ("test 11")
 814     dut = ExampleAddRecordPlaceHolderPipe()
 815     data=data_placeholder()
 816     test = Test5(dut, test11_resultfn, data=data)
 817     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
 818
 819
 820     print ("test 12")
 821     #dut = ExampleBufPipe3()
 822     dut = ExampleBufDelayedPipe()
 823     data = data_chain1()
 824     test = Test5(dut, test12_resultfn, data=data)
 825     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
 826     ports = [dut.p.i_valid, dut.n.i_ready,
 827              dut.n.o_valid, dut.p.o_ready] + \
 828              [dut.p.i_data] + [dut.n.o_data]
 829     vl = rtlil.convert(dut, ports=ports)
 830     with open("test_bufpipe12.il", "w") as f:
 831         f.write(vl)
 832
 833     print ("test 13")
 834     #dut = ExampleBufPipe3()
 835     dut = ExampleUnBufDelayedPipe()
 836     data = data_chain1()
 837     test = Test5(dut, test12_resultfn, data=data)
 838     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
 839     ports = [dut.p.i_valid, dut.n.i_ready,
 840              dut.n.o_valid, dut.p.o_ready] + \
 841              [dut.p.i_data] + [dut.n.o_data]
 842     vl = rtlil.convert(dut, ports=ports)
 843     with open("test_unbufpipe13.il", "w") as f:
 844         f.write(vl)
 845
 846     print ("test 999")
 847     dut = ExampleBufUnBufPipe()
 848     data = data_chain1()
 849     test = Test5(dut, test9_resultfn, data=data)
 850     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
 851     ports = [dut.p.i_valid, dut.n.i_ready,
 852              dut.n.o_valid, dut.p.o_ready] + \
 853              [dut.p.i_data] + [dut.n.o_data]
 854     vl = rtlil.convert(dut, ports=ports)
 855     with open("test_bufunbuf999.il", "w") as f:
 856         f.write(vl)
 857