src/add/test_buf_pipe.py

   1 """ Unit tests for Buffered and Unbuffered pipelines
   2
   3     contains useful worked examples of how to use the Pipeline API,
   4     including:
   5
   6     * Combinatorial Stage "Chaining"
   7     * class-based data stages
   8     * nmigen module-based data stages
   9     * special nmigen module-based data stage, where the stage *is* the module
  10     * Record-based data stages
  11     * static-class data stages
  12     * multi-stage pipelines (and how to connect them)
  13     * how to *use* the pipelines (see Test5) - how to get data in and out
  14
  15 """
  16
  17 from nmigen import Module, Signal, Mux, Const
  18 from nmigen.hdl.rec import Record
  19 from nmigen.compat.sim import run_simulation
  20 from nmigen.cli import verilog, rtlil
  21
  22 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
  23 from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
  24 from example_buf_pipe import ExampleStageCls
  25 from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
  26 from example_buf_pipe import StageChain, ControlBase, StageCls
  27 from singlepipe import UnbufferedPipeline2
  28
  29 from random import randint, seed
  30
  31 seed(0)
  32
  33
  34 def check_o_n_valid(dut, val):
  35     o_n_valid = yield dut.n.o_valid
  36     assert o_n_valid == val
  37
  38 def check_o_n_valid2(dut, val):
  39     o_n_valid = yield dut.n.o_valid
  40     assert o_n_valid == val
  41
  42
  43 def testbench(dut):
  44     #yield dut.i_p_rst.eq(1)
  45     yield dut.n.i_ready.eq(0)
  46     yield dut.p.o_ready.eq(0)
  47     yield
  48     yield
  49     #yield dut.i_p_rst.eq(0)
  50     yield dut.n.i_ready.eq(1)
  51     yield dut.p.i_data.eq(5)
  52     yield dut.p.i_valid.eq(1)
  53     yield
  54
  55     yield dut.p.i_data.eq(7)
  56     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
  57     yield
  58     yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
  59
  60     yield dut.p.i_data.eq(2)
  61     yield
  62     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
  63     yield dut.p.i_data.eq(9)
  64     yield
  65     yield dut.p.i_valid.eq(0)
  66     yield dut.p.i_data.eq(12)
  67     yield
  68     yield dut.p.i_data.eq(32)
  69     yield dut.n.i_ready.eq(1)
  70     yield
  71     yield from check_o_n_valid(dut, 1) # buffer still needs to output
  72     yield
  73     yield from check_o_n_valid(dut, 1) # buffer still needs to output
  74     yield
  75     yield from check_o_n_valid(dut, 0) # buffer outputted, *now* we're done.
  76     yield
  77
  78
  79 def testbench2(dut):
  80     #yield dut.p.i_rst.eq(1)
  81     yield dut.n.i_ready.eq(0)
  82     #yield dut.p.o_ready.eq(0)
  83     yield
  84     yield
  85     #yield dut.p.i_rst.eq(0)
  86     yield dut.n.i_ready.eq(1)
  87     yield dut.p.i_data.eq(5)
  88     yield dut.p.i_valid.eq(1)
  89     yield
  90
  91     yield dut.p.i_data.eq(7)
  92     yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
  93     yield
  94     yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
  95
  96     yield dut.p.i_data.eq(2)
  97     yield
  98     yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
  99     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
 100     yield dut.p.i_data.eq(9)
 101     yield
 102     yield dut.p.i_valid.eq(0)
 103     yield dut.p.i_data.eq(12)
 104     yield
 105     yield dut.p.i_data.eq(32)
 106     yield dut.n.i_ready.eq(1)
 107     yield
 108     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
 109     yield
 110     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
 111     yield
 112     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
 113     yield
 114     yield from check_o_n_valid2(dut, 0) # buffer outputted, *now* we're done.
 115     yield
 116     yield
 117     yield
 118
 119
 120 class Test3:
 121     def __init__(self, dut, resultfn):
 122         self.dut = dut
 123         self.resultfn = resultfn
 124         self.data = []
 125         for i in range(num_tests):
 126             #data.append(randint(0, 1<<16-1))
 127             self.data.append(i+1)
 128         self.i = 0
 129         self.o = 0
 130
 131     def send(self):
 132         while self.o != len(self.data):
 133             send_range = randint(0, 3)
 134             for j in range(randint(1,10)):
 135                 if send_range == 0:
 136                     send = True
 137                 else:
 138                     send = randint(0, send_range) != 0
 139                 o_p_ready = yield self.dut.p.o_ready
 140                 if not o_p_ready:
 141                     yield
 142                     continue
 143                 if send and self.i != len(self.data):
 144                     yield self.dut.p.i_valid.eq(1)
 145                     yield self.dut.p.i_data.eq(self.data[self.i])
 146                     self.i += 1
 147                 else:
 148                     yield self.dut.p.i_valid.eq(0)
 149                 yield
 150
 151     def rcv(self):
 152         while self.o != len(self.data):
 153             stall_range = randint(0, 3)
 154             for j in range(randint(1,10)):
 155                 stall = randint(0, stall_range) != 0
 156                 yield self.dut.n.i_ready.eq(stall)
 157                 yield
 158                 o_n_valid = yield self.dut.n.o_valid
 159                 i_n_ready = yield self.dut.n.i_ready_test
 160                 if not o_n_valid or not i_n_ready:
 161                     continue
 162                 o_data = yield self.dut.n.o_data
 163                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
 164                 self.o += 1
 165                 if self.o == len(self.data):
 166                     break
 167
 168 def test3_resultfn(o_data, expected, i, o):
 169     assert o_data == expected + 1, \
 170                 "%d-%d data %x not match %x\n" \
 171                 % (i, o, o_data, expected)
 172
 173 def data_placeholder():
 174         data = []
 175         for i in range(num_tests):
 176             d = PlaceHolder()
 177             d.src1 = randint(0, 1<<16-1)
 178             d.src2 = randint(0, 1<<16-1)
 179             data.append(d)
 180         return data
 181
 182 def data_dict():
 183         data = []
 184         for i in range(num_tests):
 185             data.append({'src1': randint(0, 1<<16-1),
 186                          'src2': randint(0, 1<<16-1)})
 187         return data
 188
 189
 190 class Test5:
 191     def __init__(self, dut, resultfn, data=None, stage_ctl=False):
 192         self.dut = dut
 193         self.resultfn = resultfn
 194         self.stage_ctl = stage_ctl
 195         if data:
 196             self.data = data
 197         else:
 198             self.data = []
 199             for i in range(num_tests):
 200                 self.data.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
 201         self.i = 0
 202         self.o = 0
 203
 204     def send(self):
 205         while self.o != len(self.data):
 206             send_range = randint(0, 3)
 207             for j in range(randint(1,10)):
 208                 if send_range == 0:
 209                     send = True
 210                 else:
 211                     send = randint(0, send_range) != 0
 212                 send = True
 213                 o_p_ready = yield self.dut.p.o_ready
 214                 if not o_p_ready:
 215                     yield
 216                     continue
 217                 if send and self.i != len(self.data):
 218                     yield self.dut.p.i_valid.eq(1)
 219                     for v in self.dut.set_input(self.data[self.i]):
 220                         yield v
 221                     self.i += 1
 222                 else:
 223                     yield self.dut.p.i_valid.eq(0)
 224                 yield
 225
 226     def rcv(self):
 227         while self.o != len(self.data):
 228             stall_range = randint(0, 3)
 229             for j in range(randint(1,10)):
 230                 ready = randint(0, stall_range) != 0
 231                 ready = True
 232                 yield self.dut.n.i_ready.eq(ready)
 233                 yield
 234                 o_n_valid = yield self.dut.n.o_valid
 235                 i_n_ready = yield self.dut.n.i_ready_test
 236                 if not o_n_valid or not i_n_ready:
 237                     continue
 238                 if isinstance(self.dut.n.o_data, Record):
 239                     o_data = {}
 240                     dod = self.dut.n.o_data
 241                     for k, v in dod.fields.items():
 242                         o_data[k] = yield v
 243                 else:
 244                     o_data = yield self.dut.n.o_data
 245                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
 246                 self.o += 1
 247                 if self.o == len(self.data):
 248                     break
 249
 250 def test5_resultfn(o_data, expected, i, o):
 251     res = expected[0] + expected[1]
 252     assert o_data == res, \
 253                 "%d-%d data %x not match %s\n" \
 254                 % (i, o, o_data, repr(expected))
 255
 256 def testbench4(dut):
 257     data = []
 258     for i in range(num_tests):
 259         #data.append(randint(0, 1<<16-1))
 260         data.append(i+1)
 261     i = 0
 262     o = 0
 263     while True:
 264         stall = randint(0, 3) != 0
 265         send = randint(0, 5) != 0
 266         yield dut.n.i_ready.eq(stall)
 267         o_p_ready = yield dut.p.o_ready
 268         if o_p_ready:
 269             if send and i != len(data):
 270                 yield dut.p.i_valid.eq(1)
 271                 yield dut.p.i_data.eq(data[i])
 272                 i += 1
 273             else:
 274                 yield dut.p.i_valid.eq(0)
 275         yield
 276         o_n_valid = yield dut.n.o_valid
 277         i_n_ready = yield dut.n.i_ready_test
 278         if o_n_valid and i_n_ready:
 279             o_data = yield dut.n.o_data
 280             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
 281                                         % (i, o, o_data, data[o])
 282             o += 1
 283             if o == len(data):
 284                 break
 285
 286 ######################################################################
 287 # Test 2 and 4
 288 ######################################################################
 289
 290 class ExampleBufPipe2(ControlBase):
 291     """ Example of how to do chained pipeline stages.
 292     """
 293
 294     def elaborate(self, platform):
 295         m = Module()
 296
 297         pipe1 = ExampleBufPipe()
 298         pipe2 = ExampleBufPipe()
 299
 300         m.submodules.pipe1 = pipe1
 301         m.submodules.pipe2 = pipe2
 302
 303         m.d.comb += self.connect([pipe1, pipe2])
 304
 305         return m
 306
 307
 308 ######################################################################
 309 # Test 9
 310 ######################################################################
 311
 312 class ExampleBufPipeChain2(BufferedPipeline):
 313     """ connects two stages together as a *single* combinatorial stage.
 314     """
 315     def __init__(self):
 316         stage1 = ExampleStageCls()
 317         stage2 = ExampleStageCls()
 318         combined = StageChain([stage1, stage2])
 319         BufferedPipeline.__init__(self, combined)
 320
 321
 322 def data_chain2():
 323         data = []
 324         for i in range(num_tests):
 325             data.append(randint(0, 1<<16-2))
 326         return data
 327
 328
 329 def test9_resultfn(o_data, expected, i, o):
 330     res = expected + 2
 331     assert o_data == res, \
 332                 "%d-%d received data %x not match expected %x\n" \
 333                 % (i, o, o_data, res)
 334
 335
 336 ######################################################################
 337 # Test 6 and 10
 338 ######################################################################
 339
 340 class SetLessThan:
 341     def __init__(self, width, signed):
 342         self.m = Module()
 343         self.src1 = Signal((width, signed), name="src1")
 344         self.src2 = Signal((width, signed), name="src2")
 345         self.output = Signal(width, name="out")
 346
 347     def elaborate(self, platform):
 348         self.m.d.comb += self.output.eq(Mux(self.src1 < self.src2, 1, 0))
 349         return self.m
 350
 351
 352 class LTStage(StageCls):
 353     """ module-based stage example
 354     """
 355     def __init__(self):
 356         self.slt = SetLessThan(16, True)
 357
 358     def ispec(self):
 359         return (Signal(16, name="sig1"), Signal(16, "sig2"))
 360
 361     def ospec(self):
 362         return Signal(16, "out")
 363
 364     def setup(self, m, i):
 365         self.o = Signal(16)
 366         m.submodules.slt = self.slt
 367         m.d.comb += self.slt.src1.eq(i[0])
 368         m.d.comb += self.slt.src2.eq(i[1])
 369         m.d.comb += self.o.eq(self.slt.output)
 370
 371     def process(self, i):
 372         return self.o
 373
 374
 375 class LTStageDerived(SetLessThan, StageCls):
 376     """ special version of a nmigen module where the module is also a stage
 377
 378         shows that you don't actually need to combinatorially connect
 379         to the outputs, or add the module as a submodule: just return
 380         the module output parameter(s) from the Stage.process() function
 381     """
 382
 383     def __init__(self):
 384         SetLessThan.__init__(self, 16, True)
 385
 386     def ispec(self):
 387         return (Signal(16), Signal(16))
 388
 389     def ospec(self):
 390         return Signal(16)
 391
 392     def setup(self, m, i):
 393         m.submodules.slt = self
 394         m.d.comb += self.src1.eq(i[0])
 395         m.d.comb += self.src2.eq(i[1])
 396
 397     def process(self, i):
 398         return self.output
 399
 400
 401 class ExampleLTPipeline(UnbufferedPipeline):
 402     """ an example of how to use the unbuffered pipeline.
 403     """
 404
 405     def __init__(self):
 406         stage = LTStage()
 407         UnbufferedPipeline.__init__(self, stage)
 408
 409
 410 class ExampleLTBufferedPipeDerived(BufferedPipeline):
 411     """ an example of how to use the buffered pipeline.
 412     """
 413
 414     def __init__(self):
 415         stage = LTStageDerived()
 416         BufferedPipeline.__init__(self, stage)
 417
 418
 419 def test6_resultfn(o_data, expected, i, o):
 420     res = 1 if expected[0] < expected[1] else 0
 421     assert o_data == res, \
 422                 "%d-%d data %x not match %s\n" \
 423                 % (i, o, o_data, repr(expected))
 424
 425
 426 ######################################################################
 427 # Test 7
 428 ######################################################################
 429
 430 class ExampleAddRecordStage(StageCls):
 431     """ example use of a Record
 432     """
 433
 434     record_spec = [('src1', 16), ('src2', 16)]
 435     def ispec(self):
 436         """ returns a Record using the specification
 437         """
 438         return Record(self.record_spec)
 439
 440     def ospec(self):
 441         return Record(self.record_spec)
 442
 443     def process(self, i):
 444         """ process the input data, returning a dictionary with key names
 445             that exactly match the Record's attributes.
 446         """
 447         return {'src1': i.src1 + 1,
 448                 'src2': i.src2 + 1}
 449
 450 ######################################################################
 451 # Test 11
 452 ######################################################################
 453
 454 class ExampleAddRecordPlaceHolderStage(StageCls):
 455     """ example use of a Record, with a placeholder as the processing result
 456     """
 457
 458     record_spec = [('src1', 16), ('src2', 16)]
 459     def ispec(self):
 460         """ returns a Record using the specification
 461         """
 462         return Record(self.record_spec)
 463
 464     def ospec(self):
 465         return Record(self.record_spec)
 466
 467     def process(self, i):
 468         """ process the input data, returning a PlaceHolder class instance
 469             with attributes that exactly match those of the Record.
 470         """
 471         o = PlaceHolder()
 472         o.src1 = i.src1 + 1
 473         o.src2 = i.src2 + 1
 474         return o
 475
 476
 477 class PlaceHolder: pass
 478
 479
 480 class ExampleAddRecordPipe(UnbufferedPipeline):
 481     """ an example of how to use the combinatorial pipeline.
 482     """
 483
 484     def __init__(self):
 485         stage = ExampleAddRecordStage()
 486         UnbufferedPipeline.__init__(self, stage)
 487
 488
 489 def test7_resultfn(o_data, expected, i, o):
 490     res = (expected['src1'] + 1, expected['src2'] + 1)
 491     assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \
 492                 "%d-%d data %s not match %s\n" \
 493                 % (i, o, repr(o_data), repr(expected))
 494
 495
 496 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
 497     """ an example of how to use the combinatorial pipeline.
 498     """
 499
 500     def __init__(self):
 501         stage = ExampleAddRecordPlaceHolderStage()
 502         UnbufferedPipeline.__init__(self, stage)
 503
 504
 505 def test11_resultfn(o_data, expected, i, o):
 506     res1 = expected.src1 + 1
 507     res2 = expected.src2 + 1
 508     assert o_data['src1'] == res1 and o_data['src2'] == res2, \
 509                 "%d-%d data %s not match %s\n" \
 510                 % (i, o, repr(o_data), repr(expected))
 511
 512
 513 ######################################################################
 514 # Test 8
 515 ######################################################################
 516
 517
 518 class Example2OpClass:
 519     """ an example of a class used to store 2 operands.
 520         requires an eq function, to conform with the pipeline stage API
 521     """
 522
 523     def __init__(self):
 524         self.op1 = Signal(16)
 525         self.op2 = Signal(16)
 526
 527     def eq(self, i):
 528         return [self.op1.eq(i.op1), self.op2.eq(i.op2)]
 529
 530
 531 class ExampleAddClassStage(StageCls):
 532     """ an example of how to use the buffered pipeline, as a class instance
 533     """
 534
 535     def ispec(self):
 536         """ returns an instance of an Example2OpClass.
 537         """
 538         return Example2OpClass()
 539
 540     def ospec(self):
 541         """ returns an output signal which will happen to contain the sum
 542             of the two inputs
 543         """
 544         return Signal(16)
 545
 546     def process(self, i):
 547         """ process the input data (sums the values in the tuple) and returns it
 548         """
 549         return i.op1 + i.op2
 550
 551
 552 class ExampleBufPipeAddClass(BufferedPipeline):
 553     """ an example of how to use the buffered pipeline, using a class instance
 554     """
 555
 556     def __init__(self):
 557         addstage = ExampleAddClassStage()
 558         BufferedPipeline.__init__(self, addstage)
 559
 560
 561 class TestInputAdd:
 562     """ the eq function, called by set_input, needs an incoming object
 563         that conforms to the Example2OpClass.eq function requirements
 564         easiest way to do that is to create a class that has the exact
 565         same member layout (self.op1, self.op2) as Example2OpClass
 566     """
 567     def __init__(self, op1, op2):
 568         self.op1 = op1
 569         self.op2 = op2
 570
 571
 572 def test8_resultfn(o_data, expected, i, o):
 573     res = expected.op1 + expected.op2 # these are a TestInputAdd instance
 574     assert o_data == res, \
 575                 "%d-%d data %x not match %s\n" \
 576                 % (i, o, o_data, repr(expected))
 577
 578 def data_2op():
 579         data = []
 580         for i in range(num_tests):
 581             data.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
 582         return data
 583
 584
 585 ######################################################################
 586 # Test 12
 587 ######################################################################
 588
 589 class ExampleStageDelayCls(StageCls):
 590     """ an example of how to use the buffered pipeline, in a static class
 591         fashion
 592     """
 593
 594     def __init__(self):
 595         self.count = Signal(2)
 596
 597     def ispec(self):
 598         return Signal(16, name="example_input_signal")
 599
 600     def ospec(self):
 601         return Signal(16, name="example_output_signal")
 602
 603     @property
 604     def d_ready(self):
 605         return (self.count == 1)# | (self.count == 3)
 606         return Const(1)
 607
 608     @property
 609     def d_valid(self):
 610         return self.count == 3
 611         return Const(1)
 612
 613     def process(self, i):
 614         """ process the input data and returns it (adds 1)
 615         """
 616         return i + 1
 617
 618     def elaborate(self, platform):
 619         m = Module()
 620         m.d.sync += self.count.eq(self.count + 1)
 621         return m
 622
 623
 624 class ExampleBufDelayedPipe(BufferedPipeline):
 625
 626     def __init__(self):
 627         stage = ExampleStageDelayCls()
 628         BufferedPipeline.__init__(self, stage, stage_ctl=True)
 629
 630     def elaborate(self, platform):
 631         m = BufferedPipeline.elaborate(self, platform)
 632         m.submodules.stage = self.stage
 633         return m
 634
 635
 636 class ExampleBufPipe3(ControlBase):
 637     """ Example of how to do delayed pipeline, where the stage signals
 638         whether it is ready.
 639     """
 640
 641     def elaborate(self, platform):
 642         m = ControlBase._elaborate(self, platform)
 643
 644         #pipe1 = ExampleBufDelayedPipe()
 645         pipe1 = ExampleBufDelayedPipe()
 646         pipe2 = ExampleBufPipe()
 647
 648         m.submodules.pipe1 = pipe1
 649         m.submodules.pipe2 = pipe2
 650
 651         m.d.comb += self.connect([pipe1, pipe2])
 652
 653         return m
 654
 655 def data_chain1():
 656         data = []
 657         for i in range(num_tests):
 658             #data.append(1<<((i*2)%15))
 659             data.append(randint(0, 1<<16-2))
 660             print (hex(data[-1]))
 661         return data
 662
 663
 664 def test12_resultfn(o_data, expected, i, o):
 665     res = expected + 1
 666     assert o_data == res, \
 667                 "%d-%d data %x not match %x\n" \
 668                 % (i, o, o_data, res)
 669
 670
 671 ######################################################################
 672 # Test 13
 673 ######################################################################
 674
 675 class ExampleUnBufDelayedPipe(UnbufferedPipeline):
 676
 677     def __init__(self):
 678         stage = ExampleStageDelayCls()
 679         UnbufferedPipeline.__init__(self, stage, stage_ctl=True)
 680
 681     def elaborate(self, platform):
 682         m = UnbufferedPipeline.elaborate(self, platform)
 683         m.submodules.stage = self.stage
 684         return m
 685
 686 ######################################################################
 687 # Test 999 - XXX FAILS
 688 # http://bugs.libre-riscv.org/show_bug.cgi?id=57
 689 ######################################################################
 690
 691 class ExampleBufAdd1Pipe(BufferedPipeline):
 692
 693     def __init__(self):
 694         stage = ExampleStageCls()
 695         BufferedPipeline.__init__(self, stage)
 696
 697
 698 class ExampleUnBufAdd1Pipe(UnbufferedPipeline2):
 699
 700     def __init__(self):
 701         stage = ExampleStageCls()
 702         UnbufferedPipeline2.__init__(self, stage)
 703
 704
 705 class ExampleBufUnBufPipe(ControlBase):
 706
 707     def elaborate(self, platform):
 708         m = ControlBase._elaborate(self, platform)
 709
 710         # XXX currently fails: any other permutation works fine.
 711         # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
 712         # also fails using UnbufferedPipeline as well
 713         #pipe1 = ExampleUnBufAdd1Pipe()
 714         #pipe2 = ExampleBufAdd1Pipe()
 715         pipe1 = ExampleBufAdd1Pipe()
 716         pipe2 = ExampleUnBufAdd1Pipe()
 717
 718         m.submodules.pipe1 = pipe1
 719         m.submodules.pipe2 = pipe2
 720
 721         m.d.comb += self.connect([pipe1, pipe2])
 722
 723         return m
 724
 725
 726 ######################################################################
 727 # Unit Tests
 728 ######################################################################
 729
 730 num_tests = 10
 731
 732 if __name__ == '__main__':
 733     print ("test 1")
 734     dut = ExampleBufPipe()
 735     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
 736
 737     print ("test 2")
 738     dut = ExampleBufPipe2()
 739     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
 740     ports = [dut.p.i_valid, dut.n.i_ready,
 741              dut.n.o_valid, dut.p.o_ready] + \
 742              [dut.p.i_data] + [dut.n.o_data]
 743     vl = rtlil.convert(dut, ports=ports)
 744     with open("test_bufpipe2.il", "w") as f:
 745         f.write(vl)
 746
 747
 748     print ("test 3")
 749     dut = ExampleBufPipe()
 750     test = Test3(dut, test3_resultfn)
 751     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
 752
 753     print ("test 3.5")
 754     dut = ExamplePipeline()
 755     test = Test3(dut, test3_resultfn)
 756     run_simulation(dut, [test.send, test.rcv], vcd_name="test_combpipe3.vcd")
 757
 758     print ("test 4")
 759     dut = ExampleBufPipe2()
 760     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
 761
 762     print ("test 5")
 763     dut = ExampleBufPipeAdd()
 764     test = Test5(dut, test5_resultfn, stage_ctl=True)
 765     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd")
 766
 767     print ("test 6")
 768     dut = ExampleLTPipeline()
 769     test = Test5(dut, test6_resultfn)
 770     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
 771
 772     ports = [dut.p.i_valid, dut.n.i_ready,
 773              dut.n.o_valid, dut.p.o_ready] + \
 774              list(dut.p.i_data) + [dut.n.o_data]
 775     vl = rtlil.convert(dut, ports=ports)
 776     with open("test_ltcomb_pipe.il", "w") as f:
 777         f.write(vl)
 778
 779     print ("test 7")
 780     dut = ExampleAddRecordPipe()
 781     data=data_dict()
 782     test = Test5(dut, test7_resultfn, data=data)
 783     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
 784
 785     ports = [dut.p.i_valid, dut.n.i_ready,
 786              dut.n.o_valid, dut.p.o_ready,
 787              dut.p.i_data.src1, dut.p.i_data.src2,
 788              dut.n.o_data.src1, dut.n.o_data.src2]
 789     vl = rtlil.convert(dut, ports=ports)
 790     with open("test_recordcomb_pipe.il", "w") as f:
 791         f.write(vl)
 792
 793     print ("test 8")
 794     dut = ExampleBufPipeAddClass()
 795     data=data_2op()
 796     test = Test5(dut, test8_resultfn, data=data)
 797     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe8.vcd")
 798
 799     print ("test 9")
 800     dut = ExampleBufPipeChain2()
 801     ports = [dut.p.i_valid, dut.n.i_ready,
 802              dut.n.o_valid, dut.p.o_ready] + \
 803              [dut.p.i_data] + [dut.n.o_data]
 804     vl = rtlil.convert(dut, ports=ports)
 805     with open("test_bufpipechain2.il", "w") as f:
 806         f.write(vl)
 807
 808     data = data_chain2()
 809     test = Test5(dut, test9_resultfn, data=data)
 810     run_simulation(dut, [test.send, test.rcv],
 811                         vcd_name="test_bufpipechain2.vcd")
 812
 813     print ("test 10")
 814     dut = ExampleLTBufferedPipeDerived()
 815     test = Test5(dut, test6_resultfn)
 816     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd")
 817     vl = rtlil.convert(dut, ports=ports)
 818     with open("test_ltbufpipe10.il", "w") as f:
 819         f.write(vl)
 820
 821     print ("test 11")
 822     dut = ExampleAddRecordPlaceHolderPipe()
 823     data=data_placeholder()
 824     test = Test5(dut, test11_resultfn, data=data)
 825     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
 826
 827
 828     print ("test 12")
 829     #dut = ExampleBufPipe3()
 830     dut = ExampleBufDelayedPipe()
 831     data = data_chain1()
 832     test = Test5(dut, test12_resultfn, data=data)
 833     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
 834     ports = [dut.p.i_valid, dut.n.i_ready,
 835              dut.n.o_valid, dut.p.o_ready] + \
 836              [dut.p.i_data] + [dut.n.o_data]
 837     vl = rtlil.convert(dut, ports=ports)
 838     with open("test_bufpipe12.il", "w") as f:
 839         f.write(vl)
 840
 841     print ("test 13")
 842     #dut = ExampleBufPipe3()
 843     dut = ExampleUnBufDelayedPipe()
 844     data = data_chain1()
 845     test = Test5(dut, test12_resultfn, data=data)
 846     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
 847     ports = [dut.p.i_valid, dut.n.i_ready,
 848              dut.n.o_valid, dut.p.o_ready] + \
 849              [dut.p.i_data] + [dut.n.o_data]
 850     vl = rtlil.convert(dut, ports=ports)
 851     with open("test_unbufpipe13.il", "w") as f:
 852         f.write(vl)
 853
 854     print ("test 14")
 855     dut = ExampleBufPipe3()
 856     #dut = ExampleBufDelayedPipe()
 857     data = data_chain1()
 858     test = Test5(dut, test9_resultfn, data=data)
 859     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
 860     ports = [dut.p.i_valid, dut.n.i_ready,
 861              dut.n.o_valid, dut.p.o_ready] + \
 862              [dut.p.i_data] + [dut.n.o_data]
 863     vl = rtlil.convert(dut, ports=ports)
 864     with open("test_bufpipe14.il", "w") as f:
 865         f.write(vl)
 866
 867     print ("test 999 (expected to fail, which is a bug)")
 868     dut = ExampleBufUnBufPipe()
 869     data = data_chain1()
 870     test = Test5(dut, test9_resultfn, data=data)
 871     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
 872     ports = [dut.p.i_valid, dut.n.i_ready,
 873              dut.n.o_valid, dut.p.o_ready] + \
 874              [dut.p.i_data] + [dut.n.o_data]
 875     vl = rtlil.convert(dut, ports=ports)
 876     with open("test_bufunbuf999.il", "w") as f:
 877         f.write(vl)
 878