replace manual pipe-connection with a general-purpose ControlBase.connect
[ieee754fpu.git] / src / add / test_buf_pipe.py
1 """ Unit tests for Buffered and Unbuffered pipelines
2
3 contains useful worked examples of how to use the Pipeline API,
4 including:
5
6 * Combinatorial Stage "Chaining"
7 * class-based data stages
8 * nmigen module-based data stages
9 * special nmigen module-based data stage, where the stage *is* the module
10 * Record-based data stages
11 * static-class data stages
12 * multi-stage pipelines (and how to connect them)
13 * how to *use* the pipelines (see Test5) - how to get data in and out
14
15 """
16
17 from nmigen import Module, Signal, Mux
18 from nmigen.hdl.rec import Record
19 from nmigen.compat.sim import run_simulation
20 from nmigen.cli import verilog, rtlil
21
22 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
23 from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
24 from example_buf_pipe import ExampleStageCls
25 from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
26 from example_buf_pipe import StageChain, ControlBase, StageCls
27
28 from random import randint
29
30
31 def check_o_n_valid(dut, val):
32 o_n_valid = yield dut.n.o_valid
33 assert o_n_valid == val
34
35 def check_o_n_valid2(dut, val):
36 o_n_valid = yield dut.n.o_valid
37 assert o_n_valid == val
38
39
40 def testbench(dut):
41 #yield dut.i_p_rst.eq(1)
42 yield dut.n.i_ready.eq(0)
43 yield dut.p.o_ready.eq(0)
44 yield
45 yield
46 #yield dut.i_p_rst.eq(0)
47 yield dut.n.i_ready.eq(1)
48 yield dut.p.i_data.eq(5)
49 yield dut.p.i_valid.eq(1)
50 yield
51
52 yield dut.p.i_data.eq(7)
53 yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
54 yield
55 yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
56
57 yield dut.p.i_data.eq(2)
58 yield
59 yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
60 yield dut.p.i_data.eq(9)
61 yield
62 yield dut.p.i_valid.eq(0)
63 yield dut.p.i_data.eq(12)
64 yield
65 yield dut.p.i_data.eq(32)
66 yield dut.n.i_ready.eq(1)
67 yield
68 yield from check_o_n_valid(dut, 1) # buffer still needs to output
69 yield
70 yield from check_o_n_valid(dut, 1) # buffer still needs to output
71 yield
72 yield from check_o_n_valid(dut, 0) # buffer outputted, *now* we're done.
73 yield
74
75
76 def testbench2(dut):
77 #yield dut.p.i_rst.eq(1)
78 yield dut.n.i_ready.eq(0)
79 #yield dut.p.o_ready.eq(0)
80 yield
81 yield
82 #yield dut.p.i_rst.eq(0)
83 yield dut.n.i_ready.eq(1)
84 yield dut.p.i_data.eq(5)
85 yield dut.p.i_valid.eq(1)
86 yield
87
88 yield dut.p.i_data.eq(7)
89 yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
90 yield
91 yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
92
93 yield dut.p.i_data.eq(2)
94 yield
95 yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
96 yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
97 yield dut.p.i_data.eq(9)
98 yield
99 yield dut.p.i_valid.eq(0)
100 yield dut.p.i_data.eq(12)
101 yield
102 yield dut.p.i_data.eq(32)
103 yield dut.n.i_ready.eq(1)
104 yield
105 yield from check_o_n_valid2(dut, 1) # buffer still needs to output
106 yield
107 yield from check_o_n_valid2(dut, 1) # buffer still needs to output
108 yield
109 yield from check_o_n_valid2(dut, 1) # buffer still needs to output
110 yield
111 yield from check_o_n_valid2(dut, 0) # buffer outputted, *now* we're done.
112 yield
113 yield
114 yield
115
116
117 class Test3:
118 def __init__(self, dut, resultfn):
119 self.dut = dut
120 self.resultfn = resultfn
121 self.data = []
122 for i in range(num_tests):
123 #data.append(randint(0, 1<<16-1))
124 self.data.append(i+1)
125 self.i = 0
126 self.o = 0
127
128 def send(self):
129 while self.o != len(self.data):
130 send_range = randint(0, 3)
131 for j in range(randint(1,10)):
132 if send_range == 0:
133 send = True
134 else:
135 send = randint(0, send_range) != 0
136 o_p_ready = yield self.dut.p.o_ready
137 if not o_p_ready:
138 yield
139 continue
140 if send and self.i != len(self.data):
141 yield self.dut.p.i_valid.eq(1)
142 yield self.dut.p.i_data.eq(self.data[self.i])
143 self.i += 1
144 else:
145 yield self.dut.p.i_valid.eq(0)
146 yield
147
148 def rcv(self):
149 while self.o != len(self.data):
150 stall_range = randint(0, 3)
151 for j in range(randint(1,10)):
152 stall = randint(0, stall_range) != 0
153 yield self.dut.n.i_ready.eq(stall)
154 yield
155 o_n_valid = yield self.dut.n.o_valid
156 i_n_ready = yield self.dut.n.i_ready
157 if not o_n_valid or not i_n_ready:
158 continue
159 o_data = yield self.dut.n.o_data
160 self.resultfn(o_data, self.data[self.o], self.i, self.o)
161 self.o += 1
162 if self.o == len(self.data):
163 break
164
165 def test3_resultfn(o_data, expected, i, o):
166 assert o_data == expected + 1, \
167 "%d-%d data %x not match %x\n" \
168 % (i, o, o_data, expected)
169
170 def data_placeholder():
171 data = []
172 for i in range(num_tests):
173 d = PlaceHolder()
174 d.src1 = randint(0, 1<<16-1)
175 d.src2 = randint(0, 1<<16-1)
176 data.append(d)
177 return data
178
179 def data_dict():
180 data = []
181 for i in range(num_tests):
182 data.append({'src1': randint(0, 1<<16-1),
183 'src2': randint(0, 1<<16-1)})
184 return data
185
186
187 class Test5:
188 def __init__(self, dut, resultfn, data=None):
189 self.dut = dut
190 self.resultfn = resultfn
191 if data:
192 self.data = data
193 else:
194 self.data = []
195 for i in range(num_tests):
196 self.data.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
197 self.i = 0
198 self.o = 0
199
200 def send(self):
201 while self.o != len(self.data):
202 send_range = randint(0, 3)
203 for j in range(randint(1,10)):
204 if send_range == 0:
205 send = True
206 else:
207 send = randint(0, send_range) != 0
208 o_p_ready = yield self.dut.p.o_ready
209 if not o_p_ready:
210 yield
211 continue
212 if send and self.i != len(self.data):
213 yield self.dut.p.i_valid.eq(1)
214 for v in self.dut.set_input(self.data[self.i]):
215 yield v
216 self.i += 1
217 else:
218 yield self.dut.p.i_valid.eq(0)
219 yield
220
221 def rcv(self):
222 while self.o != len(self.data):
223 stall_range = randint(0, 3)
224 for j in range(randint(1,10)):
225 stall = randint(0, stall_range) != 0
226 yield self.dut.n.i_ready.eq(stall)
227 yield
228 o_n_valid = yield self.dut.n.o_valid
229 i_n_ready = yield self.dut.n.i_ready
230 if not o_n_valid or not i_n_ready:
231 continue
232 if isinstance(self.dut.n.o_data, Record):
233 o_data = {}
234 dod = self.dut.n.o_data
235 for k, v in dod.fields.items():
236 o_data[k] = yield v
237 else:
238 o_data = yield self.dut.n.o_data
239 self.resultfn(o_data, self.data[self.o], self.i, self.o)
240 self.o += 1
241 if self.o == len(self.data):
242 break
243
244 def test5_resultfn(o_data, expected, i, o):
245 res = expected[0] + expected[1]
246 assert o_data == res, \
247 "%d-%d data %x not match %s\n" \
248 % (i, o, o_data, repr(expected))
249
250 def testbench4(dut):
251 data = []
252 for i in range(num_tests):
253 #data.append(randint(0, 1<<16-1))
254 data.append(i+1)
255 i = 0
256 o = 0
257 while True:
258 stall = randint(0, 3) != 0
259 send = randint(0, 5) != 0
260 yield dut.n.i_ready.eq(stall)
261 o_p_ready = yield dut.p.o_ready
262 if o_p_ready:
263 if send and i != len(data):
264 yield dut.p.i_valid.eq(1)
265 yield dut.p.i_data.eq(data[i])
266 i += 1
267 else:
268 yield dut.p.i_valid.eq(0)
269 yield
270 o_n_valid = yield dut.n.o_valid
271 i_n_ready = yield dut.n.i_ready
272 if o_n_valid and i_n_ready:
273 o_data = yield dut.n.o_data
274 assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
275 % (i, o, o_data, data[o])
276 o += 1
277 if o == len(data):
278 break
279
280 ######################################################################
281 # Test 2 and 4
282 ######################################################################
283
284 class ExampleBufPipe2(ControlBase):
285 """
286 connect these: ------|---------------|
287 v v
288 i_p_valid >>in pipe1 o_n_valid out>> i_p_valid >>in pipe2
289 o_p_ready <<out pipe1 i_n_ready <<in o_p_ready <<out pipe2
290 p_i_data >>in pipe1 p_i_data out>> n_o_data >>in pipe2
291 """
292 def __init__(self):
293 ControlBase.__init__(self)
294
295 self.pipe1 = ExampleBufPipe()
296 self.pipe2 = ExampleBufPipe()
297
298 def elaborate(self, platform):
299 m = Module()
300 m.submodules.pipe1 = self.pipe1
301 m.submodules.pipe2 = self.pipe2
302
303 self.connect(m, [self.pipe1, self.pipe2])
304
305 return m
306
307
308 class ExampleBufPipeChain2(BufferedPipeline):
309 """ connects two stages together as a *single* combinatorial stage.
310 """
311 def __init__(self):
312 stage1 = ExampleStageCls()
313 stage2 = ExampleStageCls()
314 combined = StageChain([stage1, stage2])
315 BufferedPipeline.__init__(self, combined)
316
317
318 def data_chain2():
319 data = []
320 for i in range(num_tests):
321 data.append(randint(0, 1<<16-2))
322 return data
323
324
325 def test9_resultfn(o_data, expected, i, o):
326 res = expected + 2
327 assert o_data == res, \
328 "%d-%d data %x not match %s\n" \
329 % (i, o, o_data, repr(expected))
330
331
332 ######################################################################
333 # Test 6 and 10
334 ######################################################################
335
336 class SetLessThan:
337 def __init__(self, width, signed):
338 self.src1 = Signal((width, signed))
339 self.src2 = Signal((width, signed))
340 self.output = Signal(width)
341
342 def elaborate(self, platform):
343 m = Module()
344 m.d.comb += self.output.eq(Mux(self.src1 < self.src2, 1, 0))
345 return m
346
347
348 class LTStage(StageCls):
349 """ module-based stage example
350 """
351 def __init__(self):
352 self.slt = SetLessThan(16, True)
353
354 def ispec(self):
355 return (Signal(16), Signal(16))
356
357 def ospec(self):
358 return Signal(16)
359
360 def setup(self, m, i):
361 self.o = Signal(16)
362 m.submodules.slt = self.slt
363 m.d.comb += self.slt.src1.eq(i[0])
364 m.d.comb += self.slt.src2.eq(i[1])
365 m.d.comb += self.o.eq(self.slt.output)
366
367 def process(self, i):
368 return self.o
369
370
371 class LTStageDerived(SetLessThan, StageCls):
372 """ special version of a nmigen module where the module is also a stage
373
374 shows that you don't actually need to combinatorially connect
375 to the outputs, or add the module as a submodule: just return
376 the module output parameter(s) from the Stage.process() function
377 """
378
379 def __init__(self):
380 SetLessThan.__init__(self, 16, True)
381
382 def ispec(self):
383 return (Signal(16), Signal(16))
384
385 def ospec(self):
386 return Signal(16)
387
388 def setup(self, m, i):
389 m.submodules.slt = self
390 m.d.comb += self.src1.eq(i[0])
391 m.d.comb += self.src2.eq(i[1])
392
393 def process(self, i):
394 return self.output
395
396
397 class ExampleLTPipeline(UnbufferedPipeline):
398 """ an example of how to use the unbuffered pipeline.
399 """
400
401 def __init__(self):
402 stage = LTStage()
403 UnbufferedPipeline.__init__(self, stage)
404
405
406 class ExampleLTBufferedPipeDerived(BufferedPipeline):
407 """ an example of how to use the buffered pipeline.
408 """
409
410 def __init__(self):
411 stage = LTStageDerived()
412 BufferedPipeline.__init__(self, stage)
413
414
415 def test6_resultfn(o_data, expected, i, o):
416 res = 1 if expected[0] < expected[1] else 0
417 assert o_data == res, \
418 "%d-%d data %x not match %s\n" \
419 % (i, o, o_data, repr(expected))
420
421
422 ######################################################################
423 # Test 7
424 ######################################################################
425
426 class ExampleAddRecordStage(StageCls):
427 """ example use of a Record
428 """
429
430 record_spec = [('src1', 16), ('src2', 16)]
431 def ispec(self):
432 """ returns a Record using the specification
433 """
434 return Record(self.record_spec)
435
436 def ospec(self):
437 return Record(self.record_spec)
438
439 def process(self, i):
440 """ process the input data, returning a dictionary with key names
441 that exactly match the Record's attributes.
442 """
443 return {'src1': i.src1 + 1,
444 'src2': i.src2 + 1}
445
446 ######################################################################
447 # Test 11
448 ######################################################################
449
450 class ExampleAddRecordPlaceHolderStage(StageCls):
451 """ example use of a Record, with a placeholder as the processing result
452 """
453
454 record_spec = [('src1', 16), ('src2', 16)]
455 def ispec(self):
456 """ returns a Record using the specification
457 """
458 return Record(self.record_spec)
459
460 def ospec(self):
461 return Record(self.record_spec)
462
463 def process(self, i):
464 """ process the input data, returning a PlaceHolder class instance
465 with attributes that exactly match those of the Record.
466 """
467 o = PlaceHolder()
468 o.src1 = i.src1 + 1
469 o.src2 = i.src2 + 1
470 return o
471
472
473 class PlaceHolder: pass
474
475
476 class ExampleAddRecordPipe(UnbufferedPipeline):
477 """ an example of how to use the combinatorial pipeline.
478 """
479
480 def __init__(self):
481 stage = ExampleAddRecordStage()
482 UnbufferedPipeline.__init__(self, stage)
483
484
485 def test7_resultfn(o_data, expected, i, o):
486 res = (expected['src1'] + 1, expected['src2'] + 1)
487 assert o_data['src1'] == res[0] and o_data['src2'] == res[1], \
488 "%d-%d data %s not match %s\n" \
489 % (i, o, repr(o_data), repr(expected))
490
491
492 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
493 """ an example of how to use the combinatorial pipeline.
494 """
495
496 def __init__(self):
497 stage = ExampleAddRecordPlaceHolderStage()
498 UnbufferedPipeline.__init__(self, stage)
499
500
501 def test11_resultfn(o_data, expected, i, o):
502 res1 = expected.src1 + 1
503 res2 = expected.src2 + 1
504 assert o_data['src1'] == res1 and o_data['src2'] == res2, \
505 "%d-%d data %s not match %s\n" \
506 % (i, o, repr(o_data), repr(expected))
507
508
509 ######################################################################
510 # Test 8
511 ######################################################################
512
513
514 class Example2OpClass:
515 """ an example of a class used to store 2 operands.
516 requires an eq function, to conform with the pipeline stage API
517 """
518
519 def __init__(self):
520 self.op1 = Signal(16)
521 self.op2 = Signal(16)
522
523 def eq(self, i):
524 return [self.op1.eq(i.op1), self.op2.eq(i.op2)]
525
526
527 class ExampleAddClassStage(StageCls):
528 """ an example of how to use the buffered pipeline, as a class instance
529 """
530
531 def ispec(self):
532 """ returns an instance of an Example2OpClass.
533 """
534 return Example2OpClass()
535
536 def ospec(self):
537 """ returns an output signal which will happen to contain the sum
538 of the two inputs
539 """
540 return Signal(16)
541
542 def process(self, i):
543 """ process the input data (sums the values in the tuple) and returns it
544 """
545 return i.op1 + i.op2
546
547
548 class ExampleBufPipeAddClass(BufferedPipeline):
549 """ an example of how to use the buffered pipeline, using a class instance
550 """
551
552 def __init__(self):
553 addstage = ExampleAddClassStage()
554 BufferedPipeline.__init__(self, addstage)
555
556
557 class TestInputAdd:
558 """ the eq function, called by set_input, needs an incoming object
559 that conforms to the Example2OpClass.eq function requirements
560 easiest way to do that is to create a class that has the exact
561 same member layout (self.op1, self.op2) as Example2OpClass
562 """
563 def __init__(self, op1, op2):
564 self.op1 = op1
565 self.op2 = op2
566
567
568 def test8_resultfn(o_data, expected, i, o):
569 res = expected.op1 + expected.op2 # these are a TestInputAdd instance
570 assert o_data == res, \
571 "%d-%d data %x not match %s\n" \
572 % (i, o, o_data, repr(expected))
573
574 def data_2op():
575 data = []
576 for i in range(num_tests):
577 data.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
578 return data
579
580
581 num_tests = 100
582
583 if __name__ == '__main__':
584 print ("test 1")
585 dut = ExampleBufPipe()
586 run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
587
588 print ("test 2")
589 dut = ExampleBufPipe2()
590 run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
591 ports = [dut.p.i_valid, dut.n.i_ready,
592 dut.n.o_valid, dut.p.o_ready] + \
593 [dut.p.i_data] + [dut.n.o_data]
594 vl = rtlil.convert(dut, ports=ports)
595 with open("test_bufpipe2.il", "w") as f:
596 f.write(vl)
597
598
599 print ("test 3")
600 dut = ExampleBufPipe()
601 test = Test3(dut, test3_resultfn)
602 run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
603
604 print ("test 3.5")
605 dut = ExamplePipeline()
606 test = Test3(dut, test3_resultfn)
607 run_simulation(dut, [test.send, test.rcv], vcd_name="test_combpipe3.vcd")
608
609 print ("test 4")
610 dut = ExampleBufPipe2()
611 run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
612
613 print ("test 5")
614 dut = ExampleBufPipeAdd()
615 test = Test5(dut, test5_resultfn)
616 run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd")
617
618 print ("test 6")
619 dut = ExampleLTPipeline()
620 test = Test5(dut, test6_resultfn)
621 run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
622
623 ports = [dut.p.i_valid, dut.n.i_ready,
624 dut.n.o_valid, dut.p.o_ready] + \
625 list(dut.p.i_data) + [dut.n.o_data]
626 vl = rtlil.convert(dut, ports=ports)
627 with open("test_ltcomb_pipe.il", "w") as f:
628 f.write(vl)
629
630 print ("test 7")
631 dut = ExampleAddRecordPipe()
632 data=data_dict()
633 test = Test5(dut, test7_resultfn, data=data)
634 run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
635
636 ports = [dut.p.i_valid, dut.n.i_ready,
637 dut.n.o_valid, dut.p.o_ready,
638 dut.p.i_data.src1, dut.p.i_data.src2,
639 dut.n.o_data.src1, dut.n.o_data.src2]
640 vl = rtlil.convert(dut, ports=ports)
641 with open("test_recordcomb_pipe.il", "w") as f:
642 f.write(vl)
643
644 print ("test 8")
645 dut = ExampleBufPipeAddClass()
646 data=data_2op()
647 test = Test5(dut, test8_resultfn, data=data)
648 run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe8.vcd")
649
650 print ("test 9")
651 dut = ExampleBufPipeChain2()
652 ports = [dut.p.i_valid, dut.n.i_ready,
653 dut.n.o_valid, dut.p.o_ready] + \
654 [dut.p.i_data] + [dut.n.o_data]
655 vl = rtlil.convert(dut, ports=ports)
656 with open("test_bufpipechain2.il", "w") as f:
657 f.write(vl)
658
659 data = data_chain2()
660 test = Test5(dut, test9_resultfn, data=data)
661 run_simulation(dut, [test.send, test.rcv],
662 vcd_name="test_bufpipechain2.vcd")
663
664 print ("test 10")
665 dut = ExampleLTBufferedPipeDerived()
666 test = Test5(dut, test6_resultfn)
667 run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd")
668 vl = rtlil.convert(dut, ports=ports)
669 with open("test_ltbufpipe10.il", "w") as f:
670 f.write(vl)
671
672 print ("test 11")
673 dut = ExampleAddRecordPlaceHolderPipe()
674 data=data_placeholder()
675 test = Test5(dut, test11_resultfn, data=data)
676 run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
677
678