src/add/test_div.py

   1 from nmigen import Module, Signal
   2 from nmigen.compat.sim import run_simulation
   3
   4 from nmigen_div_experiment import FPDIV
   5
   6 class ORGate:
   7     def __init__(self):
   8         self.a = Signal()
   9         self.b = Signal()
  10         self.x = Signal()
  11
  12     def get_fragment(self, platform=None):
  13
  14         m = Module()
  15         m.d.comb += self.x.eq(self.a | self.b)
  16
  17         return m
  18
  19 def check_case(dut, a, b, z):
  20     yield dut.in_a.v.eq(a)
  21     yield dut.in_a.stb.eq(1)
  22     yield
  23     yield
  24     a_ack = (yield dut.in_a.ack)
  25     assert a_ack == 0
  26     yield dut.in_b.v.eq(b)
  27     yield dut.in_b.stb.eq(1)
  28     b_ack = (yield dut.in_b.ack)
  29     assert b_ack == 0
  30
  31     while True:
  32         yield
  33         out_z_stb = (yield dut.out_z.stb)
  34         if not out_z_stb:
  35             continue
  36         yield dut.in_a.stb.eq(0)
  37         yield dut.in_b.stb.eq(0)
  38         yield dut.out_z.ack.eq(1)
  39         yield
  40         yield dut.out_z.ack.eq(0)
  41         yield
  42         yield
  43         break
  44
  45     out_z = yield dut.out_z.v
  46     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
  47
  48 def testbench(dut):
  49     yield from check_case(dut, 0x40000000, 0x3F800000, 0x40000000)
  50     yield from check_case(dut, 0x3F800000, 0x40000000, 0x3F000000)
  51     yield from check_case(dut, 0x3F800000, 0x40400000, 0x3EAAAAAB)
  52     yield from check_case(dut, 0x40400000, 0x41F80000, 0x3DC6318C)
  53
  54 if __name__ == '__main__':
  55     dut = FPDIV(width=32)
  56     run_simulation(dut, testbench(dut), vcd_name="test_div.vcd")
  57