src/add/test_dual.py

   1 from sfpy import Float32
   2 from nmigen.compat.sim import run_simulation
   3 from dual_add_experiment import ALU
   4
   5
   6 def get_case(dut, a, b, c):
   7     yield dut.a.v.eq(a)
   8     yield dut.a.stb.eq(1)
   9     yield
  10     yield
  11     a_ack = (yield dut.a.ack)
  12     assert a_ack == 0
  13
  14     yield dut.b.v.eq(b)
  15     yield dut.b.stb.eq(1)
  16     yield
  17     yield
  18     b_ack = (yield dut.b.ack)
  19     assert b_ack == 0
  20
  21     while True:
  22         out_z_stb = (yield dut.int_stb)
  23         if not out_z_stb:
  24             yield
  25             continue
  26         break
  27
  28     yield dut.c.v.eq(c)
  29     yield dut.c.stb.eq(1)
  30     yield
  31     yield
  32     c_ack = (yield dut.c.ack)
  33     assert c_ack == 0
  34
  35     while True:
  36         yield
  37         out_z_stb = (yield dut.z.stb)
  38         if not out_z_stb:
  39             continue
  40
  41         out_z = yield dut.z.v
  42
  43         yield dut.z.ack.eq(0)
  44         yield dut.a.stb.eq(0)
  45         yield dut.b.stb.eq(0)
  46         yield dut.c.stb.eq(0)
  47         yield
  48         yield
  49         yield
  50         yield
  51         yield
  52         yield
  53         yield dut.z.ack.eq(1)
  54         yield
  55         yield
  56         yield
  57         yield
  58         break
  59
  60     return out_z
  61
  62 def check_case(dut, a, b, c, z):
  63     out_z = yield from get_case(dut, a, b, c)
  64     assert out_z == z, "Output z 0x%x != 0x%x" % (out_z, z)
  65
  66 def testbench(dut):
  67     yield from check_case(dut, 0, 0, 0, 0)
  68     yield from check_case(dut, 0x3F800000, 0x40000000, 0xc0000000, 0x3F800000)
  69
  70 if __name__ == '__main__':
  71     dut = ALU(width=32)
  72     run_simulation(dut, testbench(dut), vcd_name="test_dual_add.vcd")
  73