1 # IEEE Floating Point Divider (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Const
, Cat
6 from nmigen
.cli
import main
, verilog
, rtlil
7 from nmigen
.compat
.sim
import run_simulation
10 from fpbase
import FPNumIn
, FPNumOut
, FPOpIn
, FPOpOut
, FPBase
, FPState
11 from singlepipe
import eq
, SimpleHandshake
, ControlBase
12 from test_buf_pipe
import data_chain2
, Test5
17 def __init__(self
, width
):
21 self
.in_a
= FPOpIn(width
)
22 self
.out_z
= FPOpOut(width
)
26 def add_state(self
, state
):
27 self
.states
.append(state
)
30 def elaborate(self
, platform
=None):
31 """ creates the HDL code-fragment for FPDiv
36 a
= FPNumIn(None, self
.width
, False)
37 z
= FPNumOut(self
.width
, False)
39 m
.submodules
.in_a
= self
.in_a
40 m
.submodules
.out_z
= self
.out_z
44 m
.d
.comb
+= a
.v
.eq(self
.in_a
.v
)
51 with m
.State("get_a"):
52 res
= self
.get_op(m
, self
.in_a
, a
, "add_1")
53 m
.d
.sync
+= eq([a
, self
.in_a
.ready_o
], res
)
55 with m
.State("add_1"):
59 z
.e
.eq(a
.e
), # exponent
60 z
.m
.eq(a
.m
+ 1), # mantissa
67 self
.pack(m
, z
, "put_z")
72 with m
.State("put_z"):
73 self
.put_z(m
, z
, self
.out_z
, "get_a")
77 class FPDIVPipe(ControlBase
):
79 def __init__(self
, width
):
81 self
.fpdiv
= FPDIV(width
=width
)
82 ControlBase
.__init
__(self
, self
)
85 return Signal(self
.width
, name
="a")
88 return Signal(self
.width
, name
="z")
90 def setup(self
, m
, i
):
91 m
.d
.comb
+= self
.fpdiv
.in_a
.v
.eq(i
) # connect input
94 return self
.fpdiv
.out_z
.v
# return z output
96 def elaborate(self
, platform
):
97 self
.m
= m
= ControlBase
.elaborate(self
, platform
)
99 m
.submodules
.fpdiv
= self
.fpdiv
101 # see if connecting to stb/ack works
102 m
.d
.comb
+= self
.p
.ready_o
.eq(self
.fpdiv
.in_a
.ready_o
)
103 m
.d
.comb
+= self
.fpdiv
.in_a
.valid_i
.eq(self
.p
.valid_i_test
)
105 m
.d
.comb
+= self
.n
.valid_o
.eq(self
.fpdiv
.out_z
.valid_o
)
106 m
.d
.comb
+= self
.fpdiv
.out_z
.ready_i
.eq(self
.n
.ready_i_test
)
107 m
.d
.comb
+= self
.n
.data_o
.eq(self
.fpdiv
.out_z
.v
)
111 def resultfn(data_o
, expected
, i
, o
):
113 assert data_o
== res
, \
114 "%d-%d received data %x not match expected %x\n" \
115 % (i
, o
, data_o
, res
)
118 if __name__
== "__main__":
119 dut
= FPDIVPipe(width
=16)
122 vl
= rtlil
.convert(dut
, ports
=ports
)
123 with
open("test_fsm_experiment.il", "w") as f
:
125 test
= Test5(dut
, resultfn
, data
=data
)
126 run_simulation(dut
, [test
.send
, test
.rcv
],
127 vcd_name
="test_fsm_experiment.vcd")