src/add/test_syncops.py

   1 from random import randint
   2 from nmigen import Module, Signal
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog
   5
   6 from inputgroup import FPGetSyncOpsMod
   7
   8
   9 def testbench(dut):
  10     stb = yield dut.stb
  11     assert stb == 0
  12     ack = yield dut.ack
  13     assert ack == 0
  14
  15     yield dut.in_op[0].eq(5)
  16     yield dut.stb.eq(0b01)
  17     yield dut.ack.eq(1)
  18     yield
  19     yield
  20     decode = yield dut.out_decode
  21     assert decode == 0
  22
  23     op0 = yield dut.out_op[0]
  24     op1 = yield dut.out_op[1]
  25     assert op0 == 0 and op1 == 0
  26
  27     yield dut.in_op[1].eq(6)
  28     yield dut.stb.eq(0b11)
  29     yield
  30     yield
  31
  32     op0 = yield dut.out_op[0]
  33     op1 = yield dut.out_op[1]
  34     assert op0 == 5 and op1 == 6
  35
  36     yield dut.ack.eq(0)
  37     yield
  38
  39     op0 = yield dut.out_op[0]
  40     op1 = yield dut.out_op[1]
  41     assert op0 == 0 and op1 == 0
  42
  43 if __name__ == '__main__':
  44     dut = FPGetSyncOpsMod(width=32)
  45     run_simulation(dut, testbench(dut), vcd_name="test_getsyncops.vcd")
  46     vl = verilog.convert(dut, ports=dut.ports())
  47     with open("test_getsyncops.v", "w") as f:
  48         f.write(vl)