src/add/unit_test_single.py

   1 import sys
   2 from sfpy import Float32
   3
   4 def get_mantissa(x):
   5     return 0x7fffff & x
   6
   7 def get_exponent(x):
   8     return ((x & 0x7f800000) >> 23) - 127
   9
  10 def get_sign(x):
  11     return ((x & 0x80000000) >> 31)
  12
  13 def is_nan(x):
  14     return get_exponent(x) == 128 and get_mantissa(x) != 0
  15
  16 def is_inf(x):
  17     return get_exponent(x) == 128 and get_mantissa(x) == 0
  18
  19 def is_pos_inf(x):
  20     return is_inf(x) and not get_sign(x)
  21
  22 def is_neg_inf(x):
  23     return is_inf(x) and get_sign(x)
  24
  25 def match(x, y):
  26     return (
  27         (is_pos_inf(x) and is_pos_inf(y)) or
  28         (is_neg_inf(x) and is_neg_inf(y)) or
  29         (is_nan(x) and is_nan(y)) or
  30         (x == y)
  31         )
  32
  33 def get_case(dut, a, b):
  34     yield dut.in_a.v.eq(a)
  35     yield dut.in_a.stb.eq(1)
  36     yield
  37     yield
  38     a_ack = (yield dut.in_a.ack)
  39     assert a_ack == 0
  40     yield dut.in_b.v.eq(b)
  41     yield dut.in_b.stb.eq(1)
  42     b_ack = (yield dut.in_b.ack)
  43     assert b_ack == 0
  44
  45     while True:
  46         yield
  47         out_z_stb = (yield dut.out_z.stb)
  48         if not out_z_stb:
  49             continue
  50         yield dut.in_a.stb.eq(0)
  51         yield dut.in_b.stb.eq(0)
  52         yield dut.out_z.ack.eq(1)
  53         yield
  54         yield dut.out_z.ack.eq(0)
  55         yield
  56         yield
  57         break
  58
  59     out_z = yield dut.out_z.v
  60     return out_z
  61
  62 def check_case(dut, a, b, z):
  63     out_z = yield from get_case(dut, a, b)
  64     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
  65
  66
  67 def run_test(dut, stimulus_a, stimulus_b):
  68
  69     expected_responses = []
  70     actual_responses = []
  71     for a, b in zip(stimulus_a, stimulus_b):
  72         af = Float32.from_bits(a)
  73         bf = Float32.from_bits(b)
  74         z = af + bf
  75         expected_responses.append(z.get_bits())
  76         #print (af, bf, z)
  77         actual = yield from get_case(dut, a, b)
  78         actual_responses.append(actual)
  79
  80     if len(actual_responses) < len(expected_responses):
  81         print ("Fail ... not enough results")
  82         exit(0)
  83
  84     for expected, actual, a, b in zip(expected_responses, actual_responses,
  85                                       stimulus_a, stimulus_b):
  86         passed = match(expected, actual)
  87
  88         if not passed:
  89
  90             print ("Fail ... expected:", hex(expected), "actual:", hex(actual))
  91
  92             print (hex(a))
  93             print ("a mantissa:", a & 0x7fffff)
  94             print ("a exponent:", ((a & 0x7f800000) >> 23) - 127)
  95             print ("a sign:", ((a & 0x80000000) >> 31))
  96
  97             print (hex(b))
  98             print ("b mantissa:", b & 0x7fffff)
  99             print ("b exponent:", ((b & 0x7f800000) >> 23) - 127)
 100             print ("b sign:", ((b & 0x80000000) >> 31))
 101
 102             print (hex(expected))
 103             print ("expected mantissa:", expected & 0x7fffff)
 104             print ("expected exponent:", ((expected & 0x7f800000) >> 23) - 127)
 105             print ("expected sign:", ((expected & 0x80000000) >> 31))
 106
 107             print (hex(actual))
 108             print ("actual mantissa:", actual & 0x7fffff)
 109             print ("actual exponent:", ((actual & 0x7f800000) >> 23) - 127)
 110             print ("actual sign:", ((actual & 0x80000000) >> 31))
 111
 112             sys.exit(0)
 113