src/add/unit_test_single.py

   1 from sfpy import Float32
   2
   3 def get_mantissa(x):
   4     return 0x7fffff & x
   5
   6 def get_exponent(x):
   7     return ((x & 0x7f800000) >> 23) - 127
   8
   9 def get_sign(x):
  10     return ((x & 0x80000000) >> 31)
  11
  12 def is_nan(x):
  13     return get_exponent(x) == 128 and get_mantissa(x) != 0
  14
  15 def is_inf(x):
  16     return get_exponent(x) == 128 and get_mantissa(x) == 0
  17
  18 def is_pos_inf(x):
  19     return is_inf(x) and not get_sign(x)
  20
  21 def is_neg_inf(x):
  22     return is_inf(x) and get_sign(x)
  23
  24 def match(x, y):
  25     return (
  26         (is_pos_inf(x) and is_pos_inf(y)) or
  27         (is_neg_inf(x) and is_neg_inf(y)) or
  28         (is_nan(x) and is_nan(y)) or
  29         (x == y)
  30         )
  31
  32 def get_case(dut, a, b):
  33     yield dut.in_a.v.eq(a)
  34     yield dut.in_a.stb.eq(1)
  35     yield
  36     yield
  37     a_ack = (yield dut.in_a.ack)
  38     assert a_ack == 0
  39     yield dut.in_b.v.eq(b)
  40     yield dut.in_b.stb.eq(1)
  41     b_ack = (yield dut.in_b.ack)
  42     assert b_ack == 0
  43
  44     while True:
  45         yield
  46         out_z_stb = (yield dut.out_z.stb)
  47         if not out_z_stb:
  48             continue
  49         yield dut.in_a.stb.eq(0)
  50         yield dut.in_b.stb.eq(0)
  51         yield dut.out_z.ack.eq(1)
  52         yield
  53         yield dut.out_z.ack.eq(0)
  54         yield
  55         yield
  56         break
  57
  58     out_z = yield dut.out_z.v
  59     return out_z
  60
  61 def check_case(dut, a, b, z):
  62     out_z = yield from get_case(dut, a, b)
  63     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
  64
  65
  66 def run_test(dut, stimulus_a, stimulus_b):
  67
  68     expected_responses = []
  69     actual_responses = []
  70     for a, b in zip(stimulus_a, stimulus_b):
  71         af = Float32.from_bits(a)
  72         bf = Float32.from_bits(b)
  73         z = af + bf
  74         expected_responses.append(z.get_bits())
  75         #print (af, bf, z)
  76         actual = yield from get_case(dut, a, b)
  77         actual_responses.append(actual)
  78
  79     if len(actual_responses) < len(expected_responses):
  80         print ("Fail ... not enough results")
  81         exit(0)
  82
  83     for expected, actual, a, b in zip(expected_responses, actual_responses,
  84                                       stimulus_a, stimulus_b):
  85         passed = match(expected, actual)
  86
  87         if not passed:
  88
  89             print ("Fail ... expected:", hex(expected), "actual:", hex(actual))
  90
  91             print (hex(a))
  92             print ("a mantissa:", a & 0x7fffff)
  93             print ("a exponent:", ((a & 0x7f800000) >> 23) - 127)
  94             print ("a sign:", ((a & 0x80000000) >> 31))
  95
  96             print (hex(b))
  97             print ("b mantissa:", b & 0x7fffff)
  98             print ("b exponent:", ((b & 0x7f800000) >> 23) - 127)
  99             print ("b sign:", ((b & 0x80000000) >> 31))
 100
 101             print (hex(expected))
 102             print ("expected mantissa:", expected & 0x7fffff)
 103             print ("expected exponent:", ((expected & 0x7f800000) >> 23) - 127)
 104             print ("expected sign:", ((expected & 0x80000000) >> 31))
 105
 106             print (hex(actual))
 107             print ("actual mantissa:", actual & 0x7fffff)
 108             print ("actual exponent:", ((actual & 0x7f800000) >> 23) - 127)
 109             print ("actual sign:", ((actual & 0x80000000) >> 31))
 110
 111             sys.exit(0)
 112