more code-shuffle
[ieee754fpu.git] / src / ieee754 / add / concurrentunit.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from math import log
6 from nmigen import Module
7 from nmigen.cli import main, verilog
8
9 from nmutil.singlepipe import PassThroughStage
10 from nmutil.multipipe import CombMuxOutPipe
11 from nmutil.multipipe import PriorityCombMuxInPipe
12
13
14 def num_bits(n):
15 return int(log(n) / log(2))
16
17 class FPADDInMuxPipe(PriorityCombMuxInPipe):
18 def __init__(self, num_rows, iospecfn):
19 self.num_rows = num_rows
20 stage = PassThroughStage(iospecfn)
21 PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
22
23
24 class FPADDMuxOutPipe(CombMuxOutPipe):
25 def __init__(self, num_rows, iospecfn):
26 self.num_rows = num_rows
27 stage = PassThroughStage(iospecfn)
28 CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
29
30
31 class ReservationStations:
32 """ Reservation-Station pipeline
33
34 Input: num_rows - number of input and output Reservation Stations
35
36 Requires: the addition of an "alu" object, an i_specfn and an o_specfn
37
38 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
39 * ALU pipeline
40 * fan-out on outputs (an array of FPPackData: z,mid)
41
42 Fan-in and Fan-out are combinatorial.
43 """
44 def __init__(self, num_rows):
45 self.num_rows = num_rows
46 self.inpipe = FPADDInMuxPipe(num_rows, self.i_specfn) # fan-in
47 self.outpipe = FPADDMuxOutPipe(num_rows, self.o_specfn) # fan-out
48
49 self.p = self.inpipe.p # kinda annoying,
50 self.n = self.outpipe.n # use pipe in/out as this class in/out
51 self._ports = self.inpipe.ports() + self.outpipe.ports()
52
53 def elaborate(self, platform):
54 m = Module()
55 m.submodules.inpipe = self.inpipe
56 m.submodules.alu = self.alu
57 m.submodules.outpipe = self.outpipe
58
59 m.d.comb += self.inpipe.n.connect_to_next(self.alu.p)
60 m.d.comb += self.alu.connect_to_next(self.outpipe)
61
62 return m
63
64 def ports(self):
65 return self._ports
66
67