src/ieee754/add/fpadd/add1.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Elaboratable
   6 from nmigen.cli import main, verilog
   7 from math import log
   8
   9 from fpbase import FPState
  10 from fpcommon.postcalc import FPAddStage1Data
  11 from fpadd.add0 import FPAddStage0Data
  12
  13
  14 class FPAddStage1Mod(FPState, Elaboratable):
  15     """ Second stage of add: preparation for normalisation.
  16         detects when tot sum is too big (tot[27] is kinda a carry bit)
  17     """
  18
  19     def __init__(self, width, id_wid):
  20         self.width = width
  21         self.id_wid = id_wid
  22         self.i = self.ispec()
  23         self.o = self.ospec()
  24
  25     def ispec(self):
  26         return FPAddStage0Data(self.width, self.id_wid)
  27
  28     def ospec(self):
  29         return FPAddStage1Data(self.width, self.id_wid)
  30
  31     def process(self, i):
  32         return self.o
  33
  34     def setup(self, m, i):
  35         """ links module to inputs and outputs
  36         """
  37         m.submodules.add1 = self
  38         m.submodules.add1_out_overflow = self.o.of
  39
  40         m.d.comb += self.i.eq(i)
  41
  42     def elaborate(self, platform):
  43         m = Module()
  44         m.d.comb += self.o.z.eq(self.i.z)
  45         # tot[-1] (MSB) gets set when the sum overflows. shift result down
  46         with m.If(~self.i.out_do_z):
  47             with m.If(self.i.tot[-1]):
  48                 m.d.comb += [
  49                     self.o.z.m.eq(self.i.tot[4:]),
  50                     self.o.of.m0.eq(self.i.tot[4]),
  51                     self.o.of.guard.eq(self.i.tot[3]),
  52                     self.o.of.round_bit.eq(self.i.tot[2]),
  53                     self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
  54                     self.o.z.e.eq(self.i.z.e + 1)
  55             ]
  56             # tot[-1] (MSB) zero case
  57             with m.Else():
  58                 m.d.comb += [
  59                     self.o.z.m.eq(self.i.tot[3:]),
  60                     self.o.of.m0.eq(self.i.tot[3]),
  61                     self.o.of.guard.eq(self.i.tot[2]),
  62                     self.o.of.round_bit.eq(self.i.tot[1]),
  63                     self.o.of.sticky.eq(self.i.tot[0])
  64             ]
  65
  66         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  67         m.d.comb += self.o.oz.eq(self.i.oz)
  68         m.d.comb += self.o.mid.eq(self.i.mid)
  69
  70         return m
  71
  72
  73 class FPAddStage1(FPState):
  74
  75     def __init__(self, width, id_wid):
  76         FPState.__init__(self, "add_1")
  77         self.mod = FPAddStage1Mod(width)
  78         self.out_z = FPNumBase(width, False)
  79         self.out_of = Overflow()
  80         self.norm_stb = Signal()
  81
  82     def setup(self, m, i):
  83         """ links module to inputs and outputs
  84         """
  85         self.mod.setup(m, i)
  86
  87         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
  88
  89         m.d.sync += self.out_of.eq(self.mod.out_of)
  90         m.d.sync += self.out_z.eq(self.mod.out_z)
  91         m.d.sync += self.norm_stb.eq(1)
  92
  93     def action(self, m):
  94         m.next = "normalise_1"
  95