src/ieee754/add/fpcommon/putz.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Signal
   6 from nmigen.cli import main, verilog
   7 from fpbase import FPState
   8
   9
  10 class FPPutZ(FPState):
  11
  12     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
  13         FPState.__init__(self, state)
  14         if to_state is None:
  15             to_state = "get_ops"
  16         self.to_state = to_state
  17         self.in_z = in_z
  18         self.out_z = out_z
  19         self.in_mid = in_mid
  20         self.out_mid = out_mid
  21
  22     def action(self, m):
  23         if self.in_mid is not None:
  24             m.d.sync += self.out_mid.eq(self.in_mid)
  25         m.d.sync += [
  26           self.out_z.z.v.eq(self.in_z)
  27         ]
  28         with m.If(self.out_z.z.valid_o & self.out_z.z.ready_i_test):
  29             m.d.sync += self.out_z.z.valid_o.eq(0)
  30             m.next = self.to_state
  31         with m.Else():
  32             m.d.sync += self.out_z.z.valid_o.eq(1)
  33
  34
  35 class FPPutZIdx(FPState):
  36
  37     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
  38         FPState.__init__(self, state)
  39         if to_state is None:
  40             to_state = "get_ops"
  41         self.to_state = to_state
  42         self.in_z = in_z
  43         self.out_zs = out_zs
  44         self.in_mid = in_mid
  45
  46     def action(self, m):
  47         outz_stb = Signal(reset_less=True)
  48         outz_ack = Signal(reset_less=True)
  49         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].valid_o),
  50                      outz_ack.eq(self.out_zs[self.in_mid].ready_i_test),
  51                     ]
  52         m.d.sync += [
  53           self.out_zs[self.in_mid].v.eq(self.in_z.v)
  54         ]
  55         with m.If(outz_stb & outz_ack):
  56             m.d.sync += self.out_zs[self.in_mid].valid_o.eq(0)
  57             m.next = self.to_state
  58         with m.Else():
  59             m.d.sync += self.out_zs[self.in_mid].valid_o.eq(1)
  60