src/ieee754/add/function_unit.py

   1 from nmigen import Signal, Cat, Const, Mux, Module, Array
   2 from nmigen.cli import main, verilog
   3
   4 from nmigen_add_experiment import FPADD
   5 from rstation_row import ReservationStationRow
   6
   7 from math import log
   8
   9 class FunctionUnit:
  10
  11     def __init__(self, width, num_units):
  12         """ Function Unit
  13
  14             * width: bit-width of IEEE754.  supported: 16, 32, 64
  15             * num_units: number of Reservation Stations
  16         """
  17         self.width = width
  18
  19         fus = []
  20         bsz = int(log(width) / log(2))
  21         for i in range(num_units):
  22             mid = Const(i, bsz)
  23             rs = ReservationStationRow(width, mid)
  24             rs.name = "RS%d" % i
  25             fus.append(rs)
  26         self.fus = Array(fus)
  27
  28     def elaborate(self, platform=None):
  29         """ creates the HDL code-fragment for ReservationStationRow
  30         """
  31         m = Module()
  32
  33         return m
  34
  35
  36 if __name__ == "__main__":
  37     rs = ReservationStationRow(width=32, id_wid=Const(1,4)
  38     main(alu, ports=[rs.in_a, rs.in_b, rs.out_z]
  39
  40     # works... but don't use, just do "python fname.py convert -t v"
  41     #print (verilog.convert(alu, ports=[
  42     #                        ports=alu.in_a.ports() + \
  43     #                              alu.in_b.ports() + \
  44     #                              alu.out_z.ports())