src/ieee754/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen.cli import main, verilog
   6 from ieee754.fpadd.statemachine import FPADDBase, FPADD
   7 from ieee754.fpadd.pipeline import FPADDMuxInOut
   8
   9 if __name__ == "__main__":
  10     if True:
  11         alu = FPADD(width=32, id_wid=5, single_cycle=True)
  12         main(alu, ports=alu.rs[0][0].ports() + \
  13                         alu.rs[0][1].ports() + \
  14                         alu.res[0].ports() + \
  15                         [alu.ids.in_mid, alu.ids.out_mid])
  16     else:
  17         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
  18         main(alu, ports=[alu.in_a, alu.in_b] + \
  19                         alu.in_t.ports() + \
  20                         alu.out_z.ports() + \
  21                         [alu.in_mid, alu.out_mid])
  22
  23
  24     # works... but don't use, just do "python fname.py convert -t v"
  25     #print (verilog.convert(alu, ports=[
  26     #                        ports=alu.in_a.ports() + \
  27     #                              alu.in_b.ports() + \
  28     #                              alu.out_z.ports())