src/ieee754/add/test_add64.py

   1 from nmigen import Module, Signal
   2 from nmigen.compat.sim import run_simulation
   3 from operator import add
   4
   5 from nmigen_add_experiment import FPADD
   6
   7 import sys
   8 import atexit
   9 from random import randint
  10 from random import seed
  11
  12 from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan,
  13                                 is_inf, is_pos_inf, is_neg_inf,
  14                                 match, get_case, check_case, run_test,
  15                                 run_edge_cases, run_corner_cases)
  16
  17
  18 def testbench(dut):
  19     yield from check_case(dut, 0, 0, 0)
  20     yield from check_case(dut, 0x3FF0000000000000, 0x4000000000000000,
  21                                0x4008000000000000)
  22     yield from check_case(dut, 0x4000000000000000, 0x3FF0000000000000,
  23                                0x4008000000000000)
  24     yield from check_case(dut, 0x4056C00000000000, 0x4042800000000000,
  25                                0x4060000000000000)
  26     yield from check_case(dut, 0x4056C00000000000, 0x4042EA3D70A3D70A,
  27                                0x40601A8F5C28F5C2)
  28
  29     count = 0
  30
  31     #regression tests
  32     stimulus_a = [0x3ff00000000000c5, 0xff80000000000000]
  33     stimulus_b = [0xbd28a404211fb72b, 0x7f80000000000000]
  34     yield from run_test(dut, stimulus_a, stimulus_b, add)
  35     count += len(stimulus_a)
  36     print (count, "vectors passed")
  37
  38     yield from run_corner_cases(dut, count, add)
  39     yield from run_edge_cases(dut, count, add)
  40
  41
  42 if __name__ == '__main__':
  43     dut = FPADD(width=64, single_cycle=False)
  44     run_simulation(dut, testbench(dut), vcd_name="test_add64.vcd")
  45