src/ieee754/add/test_dual.py

   1 # FIXME: This file is on the pytest ignore list in pyproject.toml because it has borked imports
   2 from sfpy import Float32
   3 from nmigen.compat.sim import run_simulation
   4 from dual_add_experiment import ALU
   5
   6
   7 def get_case(dut, a, b, c):
   8     yield dut.a.v.eq(a)
   9     yield dut.a.stb.eq(1)
  10     yield
  11     yield
  12     a_ack = (yield dut.a.ack)
  13     assert a_ack == 0
  14
  15     yield dut.a.stb.eq(0)
  16
  17     yield dut.b.v.eq(b)
  18     yield dut.b.stb.eq(1)
  19     yield
  20     yield
  21     b_ack = (yield dut.b.ack)
  22     assert b_ack == 0
  23
  24     yield dut.b.stb.eq(0)
  25
  26     yield dut.c.v.eq(c)
  27     yield dut.c.stb.eq(1)
  28     yield
  29     yield
  30     c_ack = (yield dut.c.ack)
  31     assert c_ack == 0
  32
  33     yield dut.c.stb.eq(0)
  34
  35     yield dut.z.ack.eq(1)
  36
  37     while True:
  38         out_z_stb = (yield dut.z.stb)
  39         if not out_z_stb:
  40             yield
  41             continue
  42
  43         out_z = yield dut.z.v
  44
  45         yield dut.z.ack.eq(0)
  46         break
  47
  48     return out_z
  49
  50 def check_case(dut, a, b, c, z):
  51     out_z = yield from get_case(dut, a, b, c)
  52     assert out_z == z, "Output z 0x%x != 0x%x" % (out_z, z)
  53
  54 def testbench(dut):
  55     yield from check_case(dut, 0, 0, 0, 0)
  56     yield from check_case(dut, 0x3F800000, 0x40000000, 0xc0000000, 0x3F800000)
  57
  58 if __name__ == '__main__':
  59     dut = ALU(width=32)
  60     run_simulation(dut, testbench(dut), vcd_name="test_dual_add.vcd")
  61