reorganise imports
[ieee754fpu.git] / src / ieee754 / fpadd / addstages.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module
6 from nmigen.cli import main, verilog
7
8 from singlepipe import (StageChain, SimpleHandshake,
9 PassThroughStage)
10
11 from fpbase import FPState
12 from ieee754.fpcommon.denorm import FPSCData
13 from ieee754.fpcommon.postcalc import FPAddStage1Data
14 from .align import FPAddAlignSingleMod
15 from .add0 import FPAddStage0Mod
16 from .add1 import FPAddStage1Mod
17
18
19 class FPAddAlignSingleAdd(FPState, SimpleHandshake):
20
21 def __init__(self, width, id_wid):
22 FPState.__init__(self, "align")
23 self.width = width
24 self.id_wid = id_wid
25 SimpleHandshake.__init__(self, self) # pipeline is its own stage
26 self.a1o = self.ospec()
27
28 def ispec(self):
29 return FPSCData(self.width, self.id_wid)
30
31 def ospec(self):
32 return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
33
34 def setup(self, m, i):
35 """ links module to inputs and outputs
36 """
37
38 # chain AddAlignSingle, AddStage0 and AddStage1
39 mod = FPAddAlignSingleMod(self.width, self.id_wid)
40 a0mod = FPAddStage0Mod(self.width, self.id_wid)
41 a1mod = FPAddStage1Mod(self.width, self.id_wid)
42
43 chain = StageChain([mod, a0mod, a1mod])
44 chain.setup(m, i)
45
46 self.o = a1mod.o
47
48 def process(self, i):
49 return self.o
50
51 def action(self, m):
52 m.d.sync += self.a1o.eq(self.process(None))
53 m.next = "normalise_1"
54
55