src/ieee754/fpadd/test/test_add.py

   1 from operator import add
   2
   3 from nmigen import Module, Signal
   4 from nmigen.compat.sim import run_simulation
   5
   6 from nmigen_add_experiment import FPADD
   7
   8 from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
   9                                 is_inf, is_pos_inf, is_neg_inf,
  10                                 match, get_rs_case, check_rs_case, run_test,
  11                                 run_edge_cases, run_corner_cases)
  12
  13 def testbench(dut):
  14     yield from check_rs_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
  15     yield from check_rs_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
  16     yield from check_rs_case(dut, 0x00000047, 0x80000048, 0x80000001)
  17     yield from check_rs_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
  18     yield from check_rs_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
  19     yield from check_rs_case(dut, 0, 0, 0)
  20     yield from check_rs_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
  21     yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  22     #yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  23     yield from check_rs_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
  24     yield from check_rs_case(dut, 0x42540000, 0xC2540000, 0x00000000)
  25     yield from check_rs_case(dut, 0xC2540000, 0x42540000, 0x00000000)
  26     yield from check_rs_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
  27     yield from check_rs_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
  28     yield from check_rs_case(dut, 0x40000000, 0xc0000000, 0x00000000)
  29     yield from check_rs_case(dut, 0x3F800000, 0x40000000, 0x40400000)
  30     yield from check_rs_case(dut, 0x40000000, 0x3F800000, 0x40400000)
  31     yield from check_rs_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
  32     yield from check_rs_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
  33     yield from check_rs_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
  34     yield from check_rs_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
  35     yield from check_rs_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
  36     yield from check_rs_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
  37     yield from check_rs_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
  38     yield from check_rs_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
  39     yield from check_rs_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
  40     yield from check_rs_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
  41     yield from check_rs_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
  42     yield from check_rs_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
  43     yield from check_rs_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
  44     yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
  45     yield from check_rs_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
  46     yield from check_rs_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
  47     yield from check_rs_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
  48     yield from check_rs_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
  49     yield from check_rs_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
  50     yield from check_rs_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
  51     yield from check_rs_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
  52     yield from check_rs_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
  53     yield from check_rs_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
  54     yield from check_rs_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
  55     yield from check_rs_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
  56     #yield from check_rs_case(dut, 1, 0, 1)
  57     #yield from check_rs_case(dut, 1, 1, 1)
  58
  59     count = 0
  60
  61     #regression tests
  62     stimulus_a = [0x80000000, 0x22cb525a, 0x40000000, 0x83e73d5c,
  63                   0xbf9b1e94, 0x34082401,
  64                     0x5e8ef81, 0x5c75da81, 0x2b017]
  65     stimulus_b = [0xff800001, 0xadd79efa, 0xC0000000, 0x1c800000,
  66                   0xc038ed3a, 0xb328cd45,
  67                     0x114f3db, 0x2f642a39, 0xff3807ab]
  68     yield from run_test(dut, stimulus_a, stimulus_b, add, get_rs_case)
  69     count += len(stimulus_a)
  70     print (count, "vectors passed")
  71
  72     yield from run_corner_cases(dut, count, add, get_rs_case)
  73     yield from run_edge_cases(dut, count, add, get_rs_case)
  74
  75 if __name__ == '__main__':
  76     dut = FPADD(width=32, id_wid=5, single_cycle=True)
  77     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
  78