src/ieee754/fpadd/test/test_add16.py

   1 from operator import add
   2
   3 from nmigen import Module, Signal
   4 from nmigen.compat.sim import run_simulation
   5
   6 from nmigen_add_experiment import FPADD
   7
   8 from unit_test_half import (get_mantissa, get_exponent, get_sign, is_nan,
   9                                 is_inf, is_pos_inf, is_neg_inf,
  10                                 match, get_case, check_case, run_test,
  11                                 run_edge_cases, run_corner_cases)
  12
  13 def testbench(dut):
  14     #yield from check_case(dut, 0x7800, 0xff6f, 0xff6f)
  15     #yield from check_case(dut, 0x0000, 0x7c32, 0x7e32)
  16     #yield from check_case(dut, 0x0000, 0x7da9, 0x7fa9)
  17     #yield from check_case(dut, 0x0000, 0x7ea0, 0x7ea0)
  18     #yield from check_case(dut, 0x7c9a, 0x8000, 0x7e9a)
  19     #yield from check_case(dut, 0x7d5e, 0x0000, 0x7f5e)
  20     #yield from check_case(dut, 0x8000, 0x7c8c, 0x7e8c)
  21     #yield from check_case(dut, 0x8000, 0xfc55, 0xfe55)
  22     #yield from check_case(dut, 0x8000, 0x7e1a, 0x7e1a)
  23
  24     #yield from check_case(dut, 0x8000, 0xfc01, 0x7e00)
  25     yield from check_case(dut, 0xfc00, 0x7c00, 0x7e00)
  26     yield from check_case(dut, 0x8000, 0, 0)
  27     yield from check_case(dut, 0, 0, 0)
  28
  29     count = 0
  30
  31     #regression tests
  32     stimulus_a = [ 0x8000, 0x8000 ]
  33     stimulus_b = [ 0x0000, 0xfc01 ]
  34     yield from run_test(dut, stimulus_a, stimulus_b, add)
  35     count += len(stimulus_a)
  36     print (count, "vectors passed")
  37
  38     yield from run_corner_cases(dut, count, add)
  39     yield from run_edge_cases(dut, count, add)
  40
  41 if __name__ == '__main__':
  42     dut = FPADD(width=16, single_cycle=True)
  43     run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")
  44